ABSTRACT Power reduction has become a popular design goal for advanced design applications, whether mobile or not.

Reducing power consumption in design enables better, cheaper products to be designed and power-related chip failures to be minimized. Researchers have shown that multi-bit flip-flop is an effective method for clock power consumption reduction. The underlying idea behind multi-bit flip-flop method is to eliminate total inverter number by sharing the inverters in the flip-flops. In this paper, we will review multi-bit flip-flop concepts, and introduce the benefits of using multi-bit flip-flops in our design. Then, we will show how to implement multi-bit flip-flop methodology by Synopsys Design Compiler. Experimental results indicate that multi-bit flip-flop is very effective and efficient method in lower-power designs. 1. Introduction With the growing popularity of portable devices, power reduction has become a popular design goal for advanced design application, whether mobile or not. Reducing power consumption in chips enables better, cheaper products to be designed and power-related chip failures to be minimized. As a result, how to minimize power consumption has become an important design goal that every chip designer must take care. Several lower power design techniques have played an important role in the design flow. Clock gating methodology is used for the register bank to replace the multiplexers and it can avoid the operation of reloading the same data value. The clock gating technique could reduce the dynamic power consumption efficiently. The multi-Vth concept is aimed at using multi-Vth cell with satisfying performance to reduce leakage consumption, and replace lower Vth (LVT) cells by high Vth (HVT) ones, if there is room for slack. Multiple Supply Multiple Voltage (MSMV) supplies of different voltages are used for core logic, base on satisfy performance or functional requirement to adjust operating voltage for each domain, even shut off this domain. Figure 1 is an ASIC chip power distribution. We can see that the flip-flops on clock tree accounted for a large proportion of power consumption. Although the power distribution will vary with different ASIC design, reducing power consumption of the flip-flop on clock tree can eliminate total power consumption efficiently.

Figure 1: Example of ASIC chip power distribution

Multi-bit flip-flop is an effective power-saving implementation methodology by merging single-bit flipflops in the design. Using multi-bit flip-flops can reduce clock dynamic power and the total flip-flop area effectively. Synopsys Design Compiler supports users to synthesis their design with multi-bit flip-flop methodology. Since Faraday has provided multi-bit flip-flop library now, it is beneficial to clients to develop their circuit design. The rest of this paper is organized as follows. Section 2 presents the multi-bit flip-flop conceptions. Section 3 presents how to use Synopsys Design Compiler and Faradays multi-bit flip-flop cell library to synthesis netlist. Experiment results are shown in Section 4. Finally, we give concluding remarks in Section 5. 2. MultiBit Flip-Flop Concept In this section, we will introduce multi-bit flip-flop conception. Before that, we will review single-bit flipflop. Figure 2 shows an example of single-bit flip-flop. A single-bit flip-flop has two latches (Master latch and slave latch). The latches need Clk and Clk signal to perform operations, such as Figure2 shows. In order to have better delay from Clk-> Q, we will regenerate Clk from Clk . Hence we will have two inverters in the clock path.

Figure 3 shows an example of merging two 1-bit flip-flops into one 2-bit flip-flop. Each 1-bit flip-flop contains two inverters, master-latch and slave-latch. Due to the manufacturing rules, inverters in flipflops tend to be oversized. As the process technology advances into smaller geometry nodes like 65nm and beyond, the minimum size of clock drivers can drive more than one flip-flop. Merging single-bit flipflops into one multi-bit flip-flop can avoid duplicate inverters, and lower the total clock dynamic power consumption. The total area contributing to flip-flops can be reduced as well.

By using multi-bit flip-flop to implement ASIC design, users can enjoy the following benefits: l l l Lower power consumption by the clock in sequential banked components Smaller area and delay, due to shared transistors and optimized transistor-level layout Reduced clock skew in sequential gates

Figure 3: An example of merging two 1-bit flip-flops into one 2-bit flip-flop. Figure 4 shows an example of dual-bit flip-flop cell. It has two data input pins, two data output pins, one clock pin and reset pin. Use dual-bit flip-flop can get the benefits of lower power consumption then single-bit, and almost no other additional costs to pay. Figure 5 shows the true table of dual-bit flip-flop cell. We could find that when CK is positive edge, the value of Q1 will pass to D1, and the value of Q2 will pass to D2. Or Q1 and Q2 will keep original value

Figure 4: A dual-bit flip-flop cell

Figure 5: The true table of dual-bit flip-flop cell. 3. MultiBit Flip-Flop Methodology In the section, we will introduce that how to use Design Compiler and Faradays multi-bit flip-flop to implement ASIC design. 3.0 The criteria of using multi-bit flip-flop Multi-bit flip-flop cells are capable of decreasing the power consumption because they have shared inverter inside the flip-flop. Meanwhile, they can minimize clock skew at the same time. To obtain these benefits, the ASIC design must meet the following requirements. l The single-bit flip-flops we want to replace with multi-bit flip-flop must have same clock condition and same set/reset condition. l When you set the variable hdlin_infer_multibit as default_all, Design Compiler will use multi-bit flip-flop to replace bus type single-bit flip-flops. For non-bus condition, your must use create_multibit to identify the multi-bit flip-flop candidates. 3.1 The feature of multi-bit flip-flop cell library When your ASIC design is satisfied above two conditions, Design Compiler can invoke multi-bit flip-flop cell library to replace the original single-bit flip-flop structure. Multi-bit flip-flop cell library must have some feature as following: l l The D input pin has to be labeled as bundle. The flip-flops function has be marked as ff_bank

Figure 6 shows a part of Faradays multi-bit flip-flop cell library.

Figure 6: Library requirement in multibit flip-flop. 3.2 Implement ASIC design with multi-bit flip-flop cell library When your ASIC design is satisfied the criteria of invoking multi-bit flip-flop and your library vendor has provided multi-bit flip-flop cell library, your can use Design Compiler to synthesis your ASIC design. Figure 7 shows an example of script Design Compiler can use it to implement ASIC design. First, the script should indicate the link library and target library by setting the link_library and target_library variable. And then, Design Compiler can infer multibit flip-flops that are present in a technology library with the variable hdlin_infer_multibit setting. The syntax is set hdlin_infer_multibit [default_all | default_no] The default value of this variable is default_none. The variable must be set before reading the RTL and following is the sample library cell model: multibit component is a group of cells with identical functionality. Two cells can have identical functionality even if they have different bit-widths. Thus, a group of cells including one 3-bit register and one 5-bit register is a multibit component (assuming identical functionality). It would still be called a multibit component if it were implemented using eight single-bit cells. Multibit library cells consume less power and area and create a more uniform layout structure than single-bit equivalents can.

Figure 7: The script for Design Compiler to synthesis netlist with multi-bit flip-flop 3.3 The Multi-Bit Flip-Flop Methodology Provided by Design Compiler Design Compiler can synthesize the following to multibit library cells:

Flip-flops Latches Master-slave circuits Multiplexers Three-state circuits

Design Compiler provides two methodologies for mapping logic to multibit library cells. (You can use either methodology or a combination of the two.) The first directs cell inference from the HDL source code. This is the best method if you know the designs layout and can determine where multibit cells

might have the most impact. For example, if the data path and control logic are well separated or if you have done early floorplanning. The second methodology directs multibit library cell inference from an already mapped design. This method is most useful after you complete an initial floorplan or placement and determine which areas can benefit from the use of multibit cells. Design Compiler supports only multi-bit cell library that have identical functionality for each bit. The multibit library cell interfaces must be either fully parallel or fully global. For example, if you want to infer a 4-bit banked flip-flop with an asynchronous reset, the rest signal must be either different for each bit or shared among all 4 bits. Design Compiler cannot infer a multibit register if the first and second bits share one asynchronous reset but the third and fourth bits share another reset. In that case, Design Compiler does not infer a multi-bit flip-flop and it will use 4 single-bit flip-flops instead. You can infer a multibit component from the HDL source code by adding command, or you can create it from Design Compiler by using the create_multibit command. For example, in netlist file, you can add the following command. reg [3:0] iAmReg; //synopsys infer_multibit iAmReg In this example, //synopsys infer_multibit iAmReg will try to change multi-bit register iAmReg to multi-bit cell. The compilation process preserves multibit components even if their implementations undergo changes. 3.4 Design Compiler Command for Multi-Bit Flip-Flop Use the report_multibit command to report all multibit components in your current design. The report lists the multibit component name and the cells that implement each bit. (You can use the command on a mapped or an unmapped design.) The syntax is report_multibit [-nosplit] [object_list] Figure 8 shows a sample of report produced by the report_multibit command.

Figure 8: An example of report multibit component Design Compiler uses a colon to identify multibit component registers with consecutive bits (0 through 1 and 2 through 3 in the previous report). Because the colon conflict with our back-end tools naming requirements, we change the colon to underscore by using the bus_range_separator_style variable. The tool uses a comma to separate nonconsecutive bits. For example, if you use bits 0 through 5 and bit 7 in the multibit component, the report lists them as 0:5, 7. The bus_multiple_separator_style variable controls this delimiter. To see a list of all multibit components in the current design, use the find command to do it. The syntax is find multibit *

Figure 9: An example of find multibit component Figure 9 shows an example of find multi-bit; Design Compiler has found reg1_reg_0_1__multibit, reg1_reg_2_3__multibit and reg1_reg_4_5__multibit. To control the Design Compiler process of optimizing the designs multibit components, use the set_multibit_options command. This command sets two attributes on the design: multibit_mode and minimum_multibit_width.

The multibit_mode attribute specifies how multibit components are optimized during the compile run. There are four modes: user_driven, structured, start_multibit, and start_singlebit. The minimum_multibit_width attribute indicates the smallest bit-width that Design Compiler optimizes as a multibit component. You can direct Design Compiler to report the values of the multibit_mode and minimum_multibit_width attributes, using the report_compile_options command. The syntax of the set_multibit_options command is set_multibit_options [-default] [-mode [user_driven | structured | start_multibit | \ start_singlebit]][minimum_width width] You can use report report_compile_options the check the setting. Figure 10 shows the result of using report_compile_options

Figure 10: An example of report_compile_options You might want Design Compiler to infer multibit cell library as multibit components on an already mapped design. To control multibit-component inference, use the create_multibit and remove_multibit commands. To create multibit components in your design, use the create_multibit command. The syntax is create_multibit object_list [-name multibit_name] [-sort] [-no_sort] Figure 11 shows that use the command create_multibit to create multibit components named tt and the component cells are reg7_reg_126_127_[0] and reg7_reg_126_127_[1] respectively..

Figure 11: An example of create multibit component After you use create_multibit command, you can use the command compile or compile incr to recompile new netlist, figure 12 shows the new netlist after recompile. You can find that the single-bit flip-flop has already transferred into multi-bit flip-flop.

Figure 12: Recompile new multibit component. To delete multibit components from your design, use the remove_multibit command. The syntax is remove_multibit object_list Figure 13 shows that use the command remove_multibit to remove multibit components named tt.

Figure 13: An example of remove multibit component After you use the remove_multibit command, you can use the command compile or compile incr to recompile new netlist, figure 14 shows the new netlist after recompile. You can find that the dual-bit flip-flop has already been broken into single-bit flip-flop.

Figure 14: Recompile new multibit component. After you use the create_multibit or remove_multibit command and recompile the design, Design Compiler will build multibit components (or reduce multibit components to single-bit components). And the tool also optimizes other cells in the design. If you want to affect only the multibit components, set a dont_touch attribute on the other cells in the design. Large multibit cells might cause routing congestion or might be too inflexible for your design. For example, in order to prevent Design Compiler to use multibit library cells larger than 8 bits, you can use the set_dont_use command with the multibit_width library attribute, as shown: set_dont_use [get_cells -filter "@multibit_width > 8" library_name/*] 4. Experiment Result We have used two test cases, ShiftReg and RISC32A, for this experiment. We have implemented the two ASIC designs by Synopsys Design Compiler, and involving Faradays multi-bit flip-flop cell library. Figure 15 shows that the single-bit flip-flop and dual-bit flip-flop in this experiment.

Figure 15: Faradays dual-bit flip-flop cell library

The figure 16 shows that we use the dual-bit flip-flop to the synthesis of the results. Replacement rate is shown as: Replacement rate = The higher replacement rate in a case, the more power consumption can be reduced. In the 2 cases, using dual-bit flip-flop in the clock tree could save about 40% and 22% power consumption respectively.

Figure 16: Dual-bit DFF Power Saving in clock tree Figure 17 shows that synthesis with dual-bit flip-flop can save 11% and 10% power consumption respectively. The experimental results also proved that synthesis with Design Compiler and faradays multibit library cell can effectively save the circuit power consumption.

Figure 17: Total power saving by dual-bit flip-flop

Figure 18: Using dual-bit flip-flop cell library can simplify clock tree effectively.

Figure 18 shows that layout of RISC32A, we can find that dual-bit flip-flop cell can effectively reduce the number of flip-flop leaf nodes and the depth of the clock tree. The number of buffers on clock three is also reduced. 5. Conclusion Using Multi-Bit Flip-flop is an effective and efficient implementation methodology to reduce the power consumption by merging single-bit flip-flop. In this paper, we have implemented ASIC design with Synopsys Design Compiler and Faradays multi-bit flip-flop. Experimental results indicate that multi-bit flip-flop is very effective and efficient method in lower-power designs. We will use this methodology to implement real ASIC project in the future.