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# CHAPTER 7

## IMPLEMENTATION AND RESULTS

This chapter deals with implementation and analysis of different types of adders, multipliers, FIR filters and compares the conventional and the newly proposed adder. Here, the main motto behind the adder analysis remains in the fact that adders prove to be the elementary block for building multipliers, which in turn are the functional blocks for FIR filter construction. OrCAD PSPICE 9.1 tool with 0.12m CMOS Technology is used for implementing digital FIR filter.

Here, altogether eight adders are analyzed with respect to number of transistors used, their respective power dissipation and delay including the proposed NEW adder. In this research work, the following 8 different adders are designed. 1. 14 Transistor Full Adder 2. 20 Transistor Full Adder 3. 28 Transistor Full Adder 4. Conventional Full Adder 5. Transmission Functional Full Adder 6. Transmission Gate Full Adder 7. Static Energy Recovery Full Adder

8. NEW Full Adder The following tables show the power dissipation of a particular adder when different combinations of input vectors are provided.Logic0 is represented by 0 volt and Logic 1 is represented by 1.1 volt. Table 7.1 Power Dissipation for 14 Transistors Full Adder INPUT A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 CIN 0 1 0 1 0 1 0 1 0 1 1 0 1 0 0 1 SUM 0.4v 1.1v 0.8v 0.3v 0.8v 0.3v 0.4v 1.1v 0 0 0 1 0 1 1 1 OUTPUT COUT 0v 0.1v 0v 1.1v 0.2v 1.1v 1.1v 1.1v TOTAL POWER DISSIPATION (in Watts) 2.24 E-05 3.60 E-01 4.59 E-01 2.42 E-01 7.42 E-01 2.42 E-01 3.20 E-05 1.10 E-05 2.56 E-01

Average Power

Table 7.2 Delay calculation for 14 Transistors Full Adder OUTPUT SUM CARRY VALUE 0 TO 1 (nS) 0.5 0.5 Total Delay VALUE 1 TO 0 (nS) 1.3 1.3 TOTAL DELAY (nS) 1.8 1.8 3.6

Table 7.3 Power Dissipation for 20 Transistors Full Adder TOTAL POWER INPUT OUTPUT DISSIPATION A B CIN SUM(Volts) COUT(Volts) (in Watts) 0 0 0 0 0.1 0 0 5.16 E-01 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 1 1 0 1 0 0 1 1.1 1.1 0.2 1.1 0.2 0.1 1.1 0 0 1 0 1 1 1 0.1 0 1.1 0.1 1.1 1.1 1.1 6.18 E-01 2.20 E-05 1.92 E-01 3.60 E-01 1.92 E-01 4.51 E-01 1.92 E-01 3.15 E-01

Average Power Table 7.4 Delay Calculation for 20 Transistors Full Adder VALUE 0 TO 1 VALUE 1 TO 0 OUTPUT (nS) (nS) SUM 0.5 1.5 CARRY 1.2 Total Delay Table 7.5 Power Dissipation for 28 Transistors Full Adder INPUT A 0 0 0 0 1 1 1 B 0 0 1 1 0 0 1 CIN 0 1 0 1 0 1 0 OUTPUT SUM((Volts)) 0 1 1 0 1 0 0 0 1.1 1.1 0 1.1 0 0 COUT((Volts)) 0 0 0 1 0 1 1 0 0 0 1.1 0 1.1 1.1 0.5

## TOTAL DELAY (nS) 2.0 1.7 3.7

TOTAL POWER DISSIPATION (in Watts) 1.43 E-02 1.41 E-02 1.52 E-02 1.41 E-02 1.55 E-02 1.52 E-02 1.41 E-02

1.1

1.1

## 1.26 E-02 1.36 E-02

Average Power

Table 7.6 Delay Calculation for 28 Transistors Full Adder OUTPUT SUM CARRY VALUE 0 TO 1(nS) 1.4 1.1 Total Delay VALUE 1 TO 0 (nS) 1.2 0.9 TOTAL DELAY (nS) 2.6 2.0n 3.6

Table 7.7 Power Dissipation for Conventional Full Adder INPUT A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 CIN 0 1 0 1 0 1 0 1 OUTPUT SUM((Volts)) 0 1 1 0 1 0 0 1 0.0 1.0 1.0 0.2 1.1 0.1 0.1 1.1 COUT((Volts)) 0 0 0 1 0 1 1 1 0.2 0.1 0.2 1.0 0.2 1.1 1.1 1.1 Total power Dissipation (in Watts) 1.89 E-01 1.63 E-01 1.72 E-01 1.64 E-01 1.66 E-01 1.73 E-01 1.73 E-01 1.62 E-01 1.70E-01

Average Power

Table 7.8 Delay Calculation for Conventional Full Adder OUTPUT SUM CARRY VALUE 0 TO 1 (nS) 1.3 0.7 Total Delay VALUE 1 TO 0 (nS) 1.1 0.8 TOTAL DELAY (nS) 2.4 1.5 3.9

Table 7.9 Power Dissipation for New Full Adder INPUT A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 CIN 0 1 0 1 0 1 0 1 OUTPUT SUM((Volts)) 0 1 1 0 1 0 0 1 0 1.1 1.1 0 1.1 0 0 1.1 COUT((Volts)) 0 0 0 1 0 1 1 1 0 0 0 1.1 0.3 1.1 0.8 1.1 TOTAL POWER DISSIPATION (in Watts) 8.25 E-04 1.37 E-03 8.25 E-04 1.58 E-03 3.67 E-03 1.51 E-03 1.57 E-03 1.65 E-03 1.63 E-03

Average Power

Table 7.10 Delay Calculation for New Full Adder OUTPUT SUM CARRY VALUE 0 TO 1 (nS) 0.6 0.2 Total Delay VALUE 1 TO 0 (nS) 1.5 0.1 TOTAL DELAY (nS) 2.1 0.3 2.4

Table 7.11 Power Dissipation for SERF INPUT A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 CIN 0 1 0 1 0 1 0 1 OUTPUT SUM((Volts)) 0 1 1 0 1 0 0 1 0.16 1.1 1.1 0 1.1 0.45 0.35 1.1 COUT((Volts)) 0 0 0 1 0 1 1 1 0 0 0 0.65 0.5 1.1 1.1 1.1 TOTAL POWER DISSIPATION (in Watts) 3.03 E-01 6.29 E-01 6.29 E-01 2.21 E-03 1.13 E-05 6.34 E-01 6.34 E-01 3.24 E-06 2.20 E-01

Average Power

Table 7.12 Delay Calculation for SERF OUTPUT SUM CARRY VALUE 0 TO 1 (nS) 0.4 0.3 Total Delay VALUE 1 TO 0 (nS) 1.2 0.3 TOTAL DELAY (nS) 1.6 0.6 2.2

Table 7.13 Power dissipation for Transmission Functional Full Adder INPUT A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 CIN 0 1 0 1 0 1 0 1 OUTPUT SUM((Volts)) 0 1 1 0 1 0 0 1 0 1.1 1.1 0.2 1.1 0.2 0 1.1 COUT((Volts)) 0 0 0 1 0 1 1 1 0 0.2 0 1.1 0.1 1.1 1.1 1.1 TOTAL POWER DISSIPATION ((in Watts) 1.23 E+00 1.47 E+00 2.20 E-05 1.92 E-01 9.79 E-01 8.12 E-01 6.73 E-01 6.60 E-01 0.75 E+00

Average Power

Table 7.14 Delay Calculation for Transmission Functional Full Adder OUTPUT SUM CARRY VALUE 0 TO 1 (nS) 0.5 1.6 Total Delay VALUE 1 TO 0 (nS) 1.5 0.3 TOTAL DELAY (nS) 2.0 1.9 3.9

Table 7.15 Power Dissipation for Transmission Gate Full Adder INPUT A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 CIN 0 1 0 1 0 1 0 1 OUTPUT SUM((Volts)) 0 1 1 0 1 0 0 1 0 1.1 1.1 0 1.1 0 0 1.1 COUT((Volts)) 0 0 0 1 0 1 1 1 0 0 0 1.1 0 1.1 1.1 1.1 TOTAL POWER DISSIPATION (in Watts) 2.40 E-01 4.20 E-01 6.18 E-01 5.22 E-01 6.18 E-01 3.60 E-01 2.53 E-01 3.85 E-01 4.27 E-01

Average Power

Table 7.16 Delay Calculation for Transmission Gate Full Adder OUTPUT SUM CARRY VALUE 0 TO 1 (nS) 1.5 1.5 Total Delay VALUE 1 TO 0 (nS) 1.0 1.0 TOTAL DELAY (nS) 2.5 2.5 5.0

Now the average power and total delay for each of the adders is available and comparison can be done between them, to find out the best adder in terms of power dissipation, number of transistors and delay. The following table 7.17 depicts these features.

Table 7.17 Comparison of different types of Single bit Adders NUMBER OF TRANSISTORS 14 20 28 32 14 10 16 24 TOTAL POWER DISSIPATION (in Watts) 2.56 E-01 3.15 E-01 1.36 E-02 1.70E-01 1.63 E-03 2.20 E-01 0.75 E+00 4.27 E-01 TOTAL DELAY (in nS) 3.6 3.7 3.6 3.9 2.4 2.2 3.9 5.0

ADDER NAME 14 TRANSISTORS 20 TRANSISTORS 28 TRANSISTORS CONVENTIONAL NEW SERF TRANSMISSION FUNCTIONAL TRANSMISSION GATE

It is clear from the table that the proposed NEW adder is efficient, both in terms of total power dissipation and total delay, compared to the other adders except the SERF adder. The SERF adder has less number of transistors than the NEW adder, but it suffers from threshold loss problem.

## 7.2 COMPARISON WITH SERF

The newly designed 1-bit full adders along with the SERF adder and the conventional CMOS adder at the schematic level is experimented. The net lists of those adders are extracted and simulated. Each circuit is simulated with the

same testing conditions and the various results are shown in figure 7.1 and figure 7.2.

## Figure 7.2 Cout comparison between SERF and NEW

Figure 7.1 and Figure 7.2 show the value of Sum and Cout for SERF and new improved 14 T Adder. The SERF does not provide logic 0 (approx 0.6 Volts) and logic 1(approx 0.9 Volts) for sum and Cout for some possible input combinations. But the new improved 14Tadder provides logic 0 (approx 0.3 Volts) and logic 1(1.2 volts) for sum and Cout for the same possible input combinations. Thus the new improved 14T adder improves the threshold loss by 50% as compared to the SERF adder.

## 7.3 MULTIPLIER ANALYSIS

Next the above analyzed adders are used as elementary blocks for building multipliers. The following table compares the power dissipation and delay for 2-Bit multiplier built using the eight types of adders. As the standard structures for multipliers (Array, Baugh wooly, Braun, Wallace tree) are not available for 2-Bit multipliers, thus they are compared generally.

Table 7.18 Delay Comparison table of 4-Bit Multiplier ADDER TYPE 14 TRANSISTOR 20 TRANSISTORS 28 TRANSISTOR CONVENTIONAL NEW TRANSMISSION FUNCTIONAL TRANSMISSION GATE DELAY (in nS) 7.5 5.8 10.4 8.4 5.2 10.0 10.2

From table 7.19, it is clear that the standard Wallace tree multiplier structure, when implemented using the proposed NEW adder proves to be the best among the other combinations when power dissipation and consideration. is taken in to

Table 7.19 Comparison Table of Power dissipation (Watts) for 4Bit Multipliers BAUGH WALLACE ADDER TYPE ARRAY BRAUN WOOLY TREE 14 0.025 0.033 0.026 0.023 TRANSISTORS

## 7.4 FIR FILTER ANALYSIS

The FIR filter analysis is the final stage of my research work. The 4 tap 4 samples and 4 bit digital FIR filter are designed using different types of adder units and multiplier structures. The comparison of delay and power dissipations is shown in table 7.20. Table 7.20 Comparison Table of Power dissipation and delay for 4Bit 4-Tap 4-Samples FIR filter MULTIPLIERS TYPE TOTAL POWER ADDERS TYPE DISSIPATION (in mW) 14 TRANSISTORS 20 TRANSISTORS
ARRAY

BAUGH WOOLY

0.618

10.10

## 14 TRANSISTORS 20 TRANSISTORS 28 TRANSISTORS

BRAUN

0.023 0.025 0.033 0.045 0.023 0.034 0.455 0.019 0.025 0.036 0.048 0.019

8.90 12.10 8.80 9.50 7.10 10.20 9.90 8.80 12.10 8.70 11.30 6.80

CONVENTIONAL NEW TRANSMISSION FUNCTIONAL TRANSMISSION GATE 14 TRANSISTORS 20 TRANSISTORS 28 TRANSISTORS CONVENTIONAL NEW

WALLACE TREE

## TRANSMISSION FUNCTIONAL TRANSMISSION GATE

0.038 0.444

9.60 9.90

The FIR comparisons are discussed and the results are tabulated. Thus, after the multiplier analysis, it is concluded that the implementation of the NEW adder in the Wallace tree multiplier structure gives the demanding result. Next, the NEW adder and Wallace tree multiplier is used to construct FIR filters. This FIR filter proved to be efficient in terms of power consumption and delay, which is the goal of the project.