Lecture 15: Periodic small signal analysis

S.Gambini

EECS 240 Topic 15:Periodic small signal analysis

2011 S.Gambini

Encore: MOS T/H

vclock
How do we simulate this circuit? Several options: 1.Transient Captures Sampling Effect Does not provide transfer function Transient noise simulation inefficient Does not provide a frequency domain view 2.AC analyses (AC,noise) Provides tracking mode bandwidth/tracking mode transfer function Provides noise Does not include effect on sampling Requires special techniques to scale-up to larger blocks (DC bias resistors etc. for amplifiers)

vin

Would like an analysis type that simulates transfer function/noise but keeps into account the sampling effect

EECS 240 Topic 15:Periodic small signal analysis

2011 S.Gambini

Encore: MOS T/H

What is the problem in this circuit? Vclock signal excites hard non-linearity in transistor (switched between on and off modes) Hard to find DC operating point Common problem in RF circuits-solved by RF simulation

vclock

vin

EECS 240 Topic 15:Periodic small signal analysis

2011 S.Gambini

(Simple)Example: Singletransistor mixer

Id

vdrain

Vclock T/2

Vdd T/2

vin

vclock
Id?gm? Assumptions: Vin=VDC+vin vin small,slow on T timescale square law transistor

EECS 240 Topic 15: Periodic small signal analysis

2011 S.Gambini

(Simple)Example: Singletransistor mixer

Id Vclock T/2 Vdd T/2

vin

vclock

Id=!(VDC-Vth+vin)2 =!(VDC)2+2!(VDC-Vth)vin+!(vin)2 Usually gm=, how can we do this here?

EECS 240 Topic 15: Periodic small signal analysis

Id~0

2011 S.Gambini

Example: Single-transistor mixer

2N if KT 3KT 2 Solution: v were constant, Id would be periodicin + Vn (17) f at Charmonics CLef fof vin c Can look f gm Id 1 2 u = (18) I ! (V d= DC-Vth+vin) Cc =!(VDC)2+2!(VDC-Vth)vin+!(vin)2 Cf f= (19) Cs + Cf + C1 1 nd P M tan ( ) (20) u vin gm2 v clock = (21) C2 CLef f CLef f + C2 + Cc 2I1 Id~0 SR = (22) Vclock Vdd Cc
Consider harmonic k of Id,Id(k) and define (k ) I gm(k) = d vin gm has also harmonics, i.e. it is periodic T/2 T/2

Itail F V SR = F

(16)

nd

(23)

EECS 240 Topic 15: Periodic small signal analysis

2011 S.Gambini

CLef f + C2 +

2N KT 3KT + f Cc CLef f Consider harmonic k of Id,Id(k) and define 2 Id=!(VDC-Vth+vin) f gm1 (k ) 2 2 I = =!(V ) +2!(VDC-Vth)vin+!(v u in) gm(k) = d (23) DC Cc vin Cf f= gm has also harmonics, i.e. it is periodic Cs + Cf + C1 DC input-> output at all harmonics of clock 1 nd P M tan ( ) Think about repeating this for every nonlinear element, u gm2 and have a small signal ckt for each harmonicnd = C C f Key: ckts do not depend on vin for vin small CLef f + C2 + 2 CLef c 2I1 Id~0 SR = Vclock Vdd Cc
2 Vn

2I1 SR = Cc

C2 CLef f Cc

SR =

Input/output spectrum
(22)

vin(f)

T/2 For this example

gm(k)

Id (k ) gm = vin = 2 (Vdc Vth )S (k) = gm S (k) S (k )

T/2

(k )

Id(f)

4 1/T

2/T

3/T

S (k) = 0 if k even 4 = if k odd (2k 1)

2011 S.Gambini

EECS 240 Topic 15: Periodic small signal analysis

P M tan1 ( gm2 CLef f + C2 +

nd =

Input/output spectrum
C2 CLef f Cc

(20) (21)

2 I1 with amplitude A? What about sinewave input SR = (22) Cc Multiply the periodic gm with input Sidebands gm(k) Id = vin
(k )

Id

(23) vin

vclock

vin(f) Input at fin gives output at k/T+/-fin Output at fout can arise from input at fout+/k/T

Id(f) 1/T 2/T 3/T

2011 S.Gambini

4 EECS 240 Topic 15: Periodic small signal analysis

CLef f + C2 +

2I1 SR = Cc
(k )

C2 CLef f Cc

Example: noise
(22)
Id

What happens to the source noise?

gm(k)

Id = vin

(23)

Has spectral components at all frequencies

vin

vclock

vin(f) Input at fin gives output at k/T+/-fin Output at fout can arise from input at fout+/k/T What is the PSD at each frequency? Id(f) Obviously we can only do this by hand for small cktsSPECTRE on the other hand.... 2/T 3/T
2011 S.Gambini

4 1/T

EECS 240 Topic 15: Periodic small signal analysis

Frequency book-keeping
Does vin really have to be slow? how many harmonics should we consider? vin can be arbitrary But: cannot choose independently input frequency, output frequency and number of harmonics Example:clock period=1MHz Desired output frequency= 0-1MHz Input frequency =1GHz #Harmonics?

vin(f) You need to set these parameters correctly in SPECTRE to get the right result Id(f) 1/T 2/T 3/T
2011 S.Gambini

EECS 240 Topic 15: Periodic small signal analysis

Periodic small signal analyses

Used when circuit has a large, periodic input (at frequency fLO )
that generates significant non-linearity and a second input that excites a linear response Large signal determines a periodic operating point Id(t),gm(t) which can be decomposed in harmonics of fLO Small signal input at fIN generates output at fIN+/-k fLO vLARGE vSMALL

EECS 240 Topic 15:Periodic small signal analysis

2011 S.Gambini

Reprise: MOS T/H

Use spectre periodic noise analysis to solve this problem Requires two/three simulations PSS (Periodic steady state):Solves quickly for circuit response due to clock only PAC/Pnoise (Periodic AC/Periodic noise) Solves periodically linearized circuit for noise,
transfer function

vclock

vin

EECS 240 Topic 15: Periodic small signal analysis

2011 S.Gambini

Simulator Setup
Pnoise Analysis Sampled-Data System:fmax=fS/2 Good starting point for low error

Adds ideal S/H function,needed for SC Forces simulator to run a specific sampling point
EECS 240 Topic 15: Periodic small signal analysis 2011 S.Gambini

Periodic Noise Analysis

"=RC=3.8nS

fS=10MHz fS=400MHz

EECS 240 Topic 15: Periodic small signal analysis

2011 S.Gambini

Capacitive feedback amplier

Initialization switches

Initialization switches HW4 OTA

EECS 240 Topic 15: Periodic small signal analysis

2011 S.Gambini

HW4 OTA Design procedure

Cf gmp Vi Cp 2Cf Gm +

CL

gmn Vx

Let us choose as primary variable Cp/Cf

EECS 240 Topic 15: Periodic small signal analysis

2011 S.Gambini

HW4 OTA Design procedure

gmp 2Cf Vi Cp Gm + Cf

CL

gmn Vx

+ Derive specifications: (Arbitrary) assign 0.4% error to static, 0.1% to settling Static accuracy fA0>250 over output range settling time: feedthrough &slewing small (verify!) Use table in Lecture 12 to determine for 0.1% optimal phase-margin 75 degrees settling time ~4 "- "=1nS (fu=160MHz)

EECS 240 Topic 15: Periodic small signal analysis

2011 S.Gambini

2I HW4 OTA Design procedure SR = (22)

1

CLef f + C2 +

C2 CLef f Cc

Cf gmp Vi 2Cf

Cc

gmn Vx

- gm(k) = Id vin Gm (k ) (k )L C gm(k) = 2 ( V V ) S = gm S th + Cp dc S (k) = 0 if k even 4 (k ) S = if k odd (2k 1) Let us choose as primary variable x=Cp/Cf Then we have: Cf 1 f= = Cf + Cs + Cp 1 + Gcl + x 2nF KT 2 Von = f CLef f Gcl + x CLef f = CL + Cf 1 + Gcl + x

(k )

(23) (24) (25) (26) (27) (28) (29) (30)

4
EECS 240 Topic 15: Periodic small signal analysis 2011 S.Gambini

HW4 OTA Design procedure

Cf gmp Vi Cp 2Cf Gm + CL

gmn Vx

Therefore, fixed x 1.Pick device L (based on gain) 2.Calculate f 3.Calculate CLeff to meet noise 4.Calculate Cf 5.Calculate gm required to meet BW 6.from L,x, gm, Cf calculate device V*

EECS 240 Topic 15: Periodic small signal analysis

2011 S.Gambini

Results
gmp 75u/1u
75u/1u

40u/400n

gmn 40u/400n Vx 200uA

Cf=Cp=300fF Cs=600fF

EECS 240 Topic 15: Periodic small signal analysis

2011 S.Gambini

Results

EECS 240 Topic 15: Periodic small signal analysis

2011 S.Gambini

Settling error
In cadence define output: EpsDyn=log10(abs(getData(/on ?result tran)-getData(/op ?result tran)-value(getData(/on ?result tran)getData(/op ?result tran) 20n))/value(getData(/on ?result tran)-getData(/op ?result tran) 20n)))

EECS 240 Topic 15: Periodic small signal analysis

2011 S.Gambini