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APPLICATION OF S-R LATCH

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Digital systems use switches to input values and to control the output. For example, a keypad uses 10 switches to enter decimal numbers 0 to 9. When a switch is closed the switch contacts physically vibrate or bounce before making a solid contact. The switch bounce causes the voltage at the output of the switch to vary between logic low and high for a very short duration before it settles to a steady state. Figure 23.1a. The variation in the voltage causes the digital circuit to operate in an erratic manner. An S-R latch connected between the switch and the digital circuit prevents the varying switch output from reaching the digital circuit. Figure 23.1b.

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In the figure 23.1a when the switch is moved up to connect the resistor to the ground, the output voltage fluctuates between logic 1 and 0 for a very brief period of time when the switch vibrates before making a solid contact. The output voltage settles to logic 0 when a solid contact is made. The active-low input S-R latch shown in figure 23.1b prevents the output signal from varying between logic 1 and 0. When the switch is moved from down position to up position, the R input is set to 1 and S input is set to 0, which sets the Q output of the S-R latch
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APPLICATION OF S-R LATCH | Digital Logic & Design

to 1. The S input varies between 0 and 1 due to switch bounce, however the S-R latch doesnt change its output state Q when S = 1 and R = 1.

Figure 23.1a The output of a switch connected to Logic High +5 v

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Figure 23.1c The switch connected through an S-R latch

The circuit diagram in figure 23.1c shows a burglar alarm circuit. The alarm switch is connected to logic high connecting the S input to logic high. The alarm is activated by setting the reset switch to ground connecting the R input to 0 volts. This sets the Q output of the latch to 0. The switch is reset to logic high. When an intruder opens a door the alarm switch is connected to ground or logic 0. The set input is set to logic 0, setting the Q output to logic 1 and activating the alarm. If the door is closed the alarm switch is reconnected to logic 1, however the Q output is maintained at logic 1 and the alarm continues to sound as S=1 and R=1 which maintains the output. The alarm can only be disabled by reconnecting the reset switch to ground.

The S-R NAND gate based latch is available in the form of an Integrated Circuit. The 74LS279 IC has four S-R latches which can be used
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APPLICATION OF S-R LATCH | Digital Logic & Design

independently.

The Gated S-R Latch

The gated S-R latch has an enable input which has to be activated to operate the latch. The circuit diagram of the gated S-R latch is shown. Figure 23.2. In the gated S-R circuit, the S and R inputs are applied at the inputs of the NAND gates 1 and 2 when the enable input is set to active-high. If the enable input is disabled by setting it to logic low the output of NAND gates 3 and 4 remains logic 1, what ever the state of S and R inputs. Thus logic 1 applied at the

inputs of NAND gates 1 and 2 keeps the Q and Q outputs to the previous state. The logic symbol of a gated S-R latch is shown in figure 23.3. The Truth Table of the gated S-R latch is shown in table 23.1. The timing diagram showing the operation of the gated S-R latch is shown in figure 23.4

Input EN 0 S x R x

Output Qt+1 Qt

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APPLICATION OF S-R LATCH | Digital Logic & Design

1 1 1 1

0 0 1 1

0 1 0 1

Qt 0 1 invalid

Table 23.1 Truth-Table of a gated S-R Latch

The Gated D Latch

If the S and R inputs of the gated S-R latch are connected together using a NOT gate then there is only a single input to the latch. The input is represented by D instead of S or R. Figure 23.5. The gated D-latch can either have D set to 0 or 1, thus the four input combinations applied at the S-R inputs of an S-R latch reduce to only two input combinations. Table 23.2. The logic symbol of a gated D-latch is shown in figure 23.6. The timing diagram of the operation of a D-latch is shown in figure 23.7. The Q output of the D latch is seen to be following the D input.

Input EN 0 1 1 1 1 Input EN 0 1 1 D x 0 1 S (D) x 0 0 1 1 R X 0 1 0 1 Output Qt+1 Qt 0 1

Output Qt+1 Qt Qt 0 1 Invalid

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APPLICATION OF S-R LATCH | Digital Logic & Design

Figure 23.7 Timing diagram of a gated D latch

Application of Gated D Latch

The D latch is available in the form of an Integrated Circuit. The 74LS75 has four D latches which can be used independently. The gated D latch can be used to store binary information. The circuit shown in figure 23.8 uses the gated D-latches connected at the input of 1-of-8 multiplexer to store a byte value (parallel). The multiplexer accesses each bit value stored in the D-latch and routes it to the output. Thus the 8-bit (byte) parallel data is converted into serial data.

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APPLICATION OF S-R LATCH | Digital Logic & Design

Edge-Triggered Flip-Flop

Flip-Flops are synchronous bi-stable devices, known as bi-stable multivibrators. Flip-flops have a clock input instead of a simple enable input as discussed earlier. The output of the flip-flop can only change when appropriate inputs are applied at the S and R inputs and a clock signal is applied at the clock input. Flip-flops with enable inputs can change their state at any instant when the enable input is active. Digital circuits that change their outputs when the enable input is active are difficult to design and debug as different parts of the digital circuit operate at different times.

In Synchronous systems, the output of all the digital circuits changes when a clock signal is applied instead of the enable signal. The change in the state of the digital circuit occurs either at the low-to-high or high-to-low transition of the clock signal. Since the transition of the clock signal is for a very short a precise time intervals thus all digital parts of a Digital system change their states simultaneously. The low to high or high to low transition of the clock is considered to be an edge. Three different types of edge-triggered flip-flops are generally used in digital logic circuits.

S-R edge-triggered flip-flop D edge-triggered flip-flop J-K edge-triggered flip-flop

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APPLICATION OF S-R LATCH | Digital Logic & Design

Each flip-flop has two variations, that is, it is either positive edge-triggered or negative edge triggered. A positive edge-triggered flip-flop changes its state on a low-to-high transition of the clock and a negative edge-triggered flip-flop changes its state on a high-to-low transition of the clock. The edge-detection circuit which allows a flip-flop to change its state on either the positive or the negative transition of the clock is implemented using a simple combinational circuit. The edge detection circuit that detects the positive and the negative clock transition are shown in figure 23.9.

Figure 23.9a Positive clock edge detection circuit

CLK

CLK

CLKPULSE

Figure 23.9b Timing diagram of the Positive clock edge detection circuit

Figure 23.9c Negative clock edge detection circuit

CLK

CLK

CLK

PULSE

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APPLICATION OF S-R LATCH | Digital Logic & Design

Figure 23.9d Timing diagram of the Negative clock edge detection circuit

Edge-Triggered S-R Flip-flop

The Logic symbols of a positive edge and a negative edge triggered S-R flip-flops are shown in figure 23.10. The truth table of the two S-R flip-flops are shown. Table 23.3. The timing diagrams of the two S-R flip-flops are shown in figure 23.11.

Input CLK 0 1 Input CLK 0 1 S x x 0 0 1 1 R x x 0 1 0 1 S X X 0 0 1 1 R X X 0 1 0 1

Output Qt+1 Qt Qt Qt 0 1 invalid Output Qt+1 Qt Qt Qt 0 1 invalid

Table 23.3 Truth-Table of Positive and Negative Edge triggered S-R flip-flops

Edge-Triggered D Flip-flop

The Logic symbols of a positive edge and a negative edge triggered D flip-flops are shown in figure 23.12. The truth table of the two D flipflops are shown. Table 23.4. The timing diagrams of the two D flip-flops are shown

Input CLK 0 1 D X X

Output Qt+1 Qt Qt

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APPLICATION OF S-R LATCH | Digital Logic & Design

Input CLK 0 1

0 1 D X X 0 1

0 1 Output Qt+1 Qt Qt 0 1

Table 23.4 Truth-Table of Positive and Negative Edge triggered D flip-flops

Edge-Triggered J-K Flip-flop

The J-K flip-flop is widely used in digital circuits. Its operation is similar to that of the SR flip-flop except that the J-K flip-flop doesnt have an invalid state, instead it toggles its state. The circuit diagram of a J-K edge-triggered flip-flop is shown

J = 0 and K =0

With Q=1 and Q =0, on a clock transition the outputs of NAND gates 3 and 4 are set to

logic 1. With logic 1 value at the inputs of NAND gates 1 and 2 the output Q and Q remains

unchanged. With Q=0 and Q =1, on a clock transition the outputs of the NAND gates 3 and 4

are set to logic 1. With logic 1 value at the inputs of NAND gates 1 and 2 the output Q and Q remains unchanged.

Thus when J=0 and K=0 the previous state is maintained and there is no change in the output.

J = 0 and K =1

With Q=1 and Q =0, on a clock transition the output of NAND gate 3 is set to logic 1. The output of the NAND gate 4 is set to 0 as all three of its inputs are at logic 1. The logic 1 and 0 at the inputs of the NAND gates 3 and 4 respectively resets the Q output to 0 and Q to

1. With Q=0 and Q =1, on a clock transition the output of NAND gate 3 is set to logic 1. The

output of the NAND gate 4 is also set to 1 as the input of the NAND gate 4 is connected to Q=0. The logic 1 and 1 at the inputs of the NAND
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APPLICATION OF S-R LATCH | Digital Logic & Design

gates 3 and 4 respectively retains the Q and

Q to 0 and 1 respectively.

Thus when J=0 and K=1 the J-K flip-flop irrespective of its earlier state is rest to state Q=0 and Q =1.

J = 1 and K =0

With Q=1 and Q =0, on a clock transition the output of NAND gate 4 is set to logic 1.

The output of the NAND gate 3 is also set to 1 as its input connected to Q is at logic 0. Thus

inputs 1 and 1 at inputs of NAND gates 1 and 2 retain the Q and Q output to 1 and 0

respectively. With Q=0 and Q =1, on a clock transition the output of NAND gate 4 is set to logic 1. The output of the NAND gate 3 is set to 0 as all its input are at logic 1. Thus inputs 0

and 1 at inputs of NAND gates 1 and 2 sets the flip-flop to Q=1 and Q =0.

Thus when J=1 and K=0 the J-K flip-flop irrespective of its output state is set to state Q=1 and Q =0.

J = 1 and K =1

With Q=1 and Q =0, on a clock transition the output of the NAND gates 3 and 4 depend

on the outputs Q and Q . The output of NAND gate 3 is set to 1 as Q is connected to its input. The output of NAND gate 4 is set to 0 as all its inputs including Q is at logic 1. A logic 1 and 0 at the input of gates 1 and 2 toggles the outputs Q and Q from logic 1 and 0 to 0 and 1

respectively. With Q=0 and Q =1, on a clock transition the output of NAND gate 3 is set to 0 as Q and the output of NAND gate 4 is set to 1. A logic 0 and 1 at the input toggles the outputs Q and Q from logic 0 and 1 to 1 and 0 respectively.

In summary when J-K inputs are both set to logic 0, the output remains unchanged. At J=0 and K=1 the J-K flip-flop is reset to Q=0 and Q =1. At J=1 and K=0 the flip-flop is set to Q=1 and Q =0. With J=1 and K=1 the output toggles from the previous state. The truth tables of the positive and negative edge triggered J-K flip-flops are shown in table 23.5. The logic symbols of the J-K flip-flops are shown in figure 23.15.
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APPLICATION OF S-R LATCH | Digital Logic & Design

The timing diagrams of the J-K flip-flops are shown

Input CLK 0 1 Input CLK 0 1 J x x 0 0 1 1 K x x 0 1 0 1 J x x 0 0 1 1 K X X 0 1 0 1

Output Qt+1 Qt Qt Qt 0 1 tQ Output Qt+1 Qt Qt Qt 0 1 tQ

Table 23.5 Truth-Table of Positive and Negative Edge triggered J-K flip-flops

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