Improving Priority Lot Cycle Times

Kilian Schmidt AMD Saxony LLC & Co. KG, MS I11-IE Wilschdorfer Landstrasse 101 D-01109 Dresden, Germany
Abstract-ISMI member companies defined two master goals for the 300mm Prime initiative (see [2]): 50% Cycle Time Reduction and 30% Cost Reduction. Combining these conflicting goals into a holistic approach represents a major challenge. This paper outlines how this goal can be targeted for priority lots. Though only a small share of WIP is priority lots, the benefit of short priority lot cycle time can be very persuading and the impact on overall costs very significant.

lyzed in Section IV. Section V concentrates on cycle time improvement methodology and Section VI reflects on cost reduction. Finally, Section VII sets the above in the 300 Prime context before Section VIII summaries the whole paper. II. CURRENT CYCLE TIME Cycle time performance of both normal and priority lots are performance metrics that IC makers dont openly communicate. Therefore there is no real-fab data available for the analysis. However the International Technology Roadmap (ITRS) gives cycle time targets which indicate current thinking on cycle time needs (see Fig. 1). For this paper it is assumed that the 2005 ITRS cycle time targets are a reasonable abstraction of current performance and that future targets are aggressive though realistic expectations. Depending on the specific use case of the priority lot, the cycle time requirement of the priority lot varies. Therefore priority lots are grouped into at least two subcategories. ITRS [2] defines Super-hot lots representing 1% of all lots and Hot lots representing 5% of all lots. These two groups have different handling policies. The specific policies differ between companies but have common key elements. Hot lots jump to the head of the lot queue once
1.8

I. INTRODUCTION Priority lots play an important role in the operational success of a Semiconductor Fab. Their task is to provide an exceptionally short cycle time for lots where this is critical. This is achieved by them having priority over normal lots and spending less time in queue. Use cases are widespread; most important are development lots for important process improvements, qualification and customer sample lots, lots which have to meet a very aggressive customer due date. However, short cycle time comes at a price. Capacity and/or normal lot cycle time is sacrificed to enable this performance. Therefore a balance between the benefit of short priority lot cycle times and the negative impact has to be found. Depending on the individual business model of the IC maker, this balance can look quite different. Independent of the business model, the whole industry searches for possibilities to decrease cycle time without or with limited capacity drawbacks and to increase capacity utilization without cycle time degradation and significant additional cost. This exploration gets specific focus with the possible development of the 300 Prime generation equipment and fabs. 300 Prime equipment and fabs could feature significantly different factory architecture elements, giving more degrees of freedom in shaping future fabs and their operation. This paper focuses on priority lot cycle times in such a new environment. Reducing priority lot cycle times is not a defined major goal of 300 Prime, but priority cycle time improvements are needed as well and more importantly the negative impact on capacity which directly translates into cost needs to be limited. This paper is organized as follows. Section II gives an overview of current cycle time performance while Section III focuses future needs. Current capacity consumption is ana-

Cycle time per mask layer (days)

1.5 1.2 0.9

1.60 1.50 1.50 1.50 1.40 1.40 1.20 0.62 1.20 1.20 1.13

0.55

0.55

0.55

0.6 0.3
0.33 0.32 0.32 0.32

0.51

0.51

0.47

0.47

0.47

0.44

0.31

0.31

0.3

0.3

0.3

0.3

0 05 06 07 08 09 10 Hot lot 11 12 13 14

Super hot lot

Normal lot

Fig. 1. ITRS Cycle Time Targets for priority and normal lots for the period 2005 - 2014 [5]

1-4244-0653-6/07/$20.00 2007 IEEE

117

2007 IEEE/SEMI Advanced Semiconductor Manufacturing Conference

they reach the operation, but have to wait there until a load port on the equipment becomes available. On the load port the hot lot again jumps to the head of the queue of all lots on that tool that are currently not in access. Yet the lot has to wait again until all wafers of the current job are loaded into the tool. Fig. 2. illustrates this behavior. There are two waiting times, at the head of queue and on the load port. On the load port the hot lot waits until all wafers of lot A are fed into the tool. Lot B which is not yet in access is blocked however. Super-hot lots in contrast have operators whose sole task is to baby-sit these lots and to ensure that a tool is kept empty prior to the arrival of a super-hot lot. (This is often facilitated by supporting IT systems; see [6].) In this way the super-hot lots dont have to wait in queues before or at the tool and start processing without delay. Fig. 3. illustrates this behavior. The empty tool awaits the super hot lot which bypasses the lot queue and starts processing without delay. Both policies ensure that these priority lots have a much shorter cycle time than normal lots only varying in the extent to which they are queued. Out of these different policies follow different contributions of cycle time components to total cycle time. Fig. 4. groups the cycle time components into the four categories raw process time, on-equipment queue time, transport time, and in-storage queue time. Contrary to many analyses queue time is split into onequipment queue time and in-storage queue time here, as this is helpful in the further analysis in this paper. The onequipment queue time represents the time that a lot sits waiting on the load port but is not accessed. The in-storage queue time is the time that the lot is stored in a stocker or another storage location. Raw process time and transport time are defined (as usual) as time absolutely necessary to process the lot and the time necessary to transport the lot between tools respectively.

Empty Tool

Lot Queue Normal lot Super hot lot

Fig. 3. Sequence of events for super-hot lot processing

Tool

One actual category is missing in this overview: lots also spend a significant amount of time in hold. However this category has no dependency on architectural considerations and solely relies on the quality of hold lot management. Therefore it is left out to facilitate transparency. Super-hot lot cycle time consists only of raw process time and transport time, provided the policy is followed. Raw process time of super hot lots is shorter than for the other lot types as they have significantly smaller lot size, e.g. ITRS targets are derived on the assumption of 5 wafer lot size for super-hot lots (see [5]). Transport time is also shorter than for other lots as super-hot lots per definition have direct tool-totool transports only and dont visit a storage location in between or are even hand-carried. Hot lots are assumed to have 25 wafer lot size as normal lots, too (see [5]), therefore raw process time is the same. They spend some time in queue waiting for a load port to become available or for the tool becoming ready to access it, yet this time is much less than for normal lots.

B
Cycle Time

Lot Queue
Super Hot Hot Normal Transport Time In-Storage Queue Time

Normal lot

Hot lot

Raw Process Time On-Equipment Queue Time

Fig. 2. Sequence of events for hot lot processing

Fig. 4. Qualitative view of cycle time components per lot priority

118

This qualitative overview on cycle time components is the basis for the improvement efforts outlined in Section V. III. FUTURE CYCLE TIME NEEDS ITRS gives cycle time targets (see Fig. 1) that seek to combine needs and realistically possible improvements into a roadmap. This results in a continuous improvement path, however, with 300 Prime the degrees of freedom available should allow for a step-function cycle time improvement that IC makers seek. Therefore for 300 Prime the real target should lie significantly below ITRS targets. IV. CURRENT CAPACITY CONSUMPTION The exceptionally short cycle time for priority lots comes at a cost. For super-hot lots downstream tools are kept empty prior to the arrival. This is a rather expensive policy because equipment capacity is lost during the waiting time. The sum of this waiting time can be quite significant. In an optimal environment exactly one lot is restrained from processing on the tool at an instant that on average leads to waiting time equivalent to half the tool capacity consumption of this lot. Variability processing time and transport time of the superhot lot compared to average expectations lead to a higher actual loss. Although super-hot lots represent only 1% of lots, they contribute to ~5% of lot activities, because of the much shorter cycle time. Taking into account the waiting time estimated above, this leads to a capacity loss of ~2.5% across all tools in the fab for the optimum case. In reality ~3.5% is more realistic considering the variability impact. Additionally super-hot lots also consume more setup time than normal lots as they have to be processed immediately whether they match the setup of a previous recipe on the tool or not. However at most current toolsets the amount of setup required for recipe changes is negligible or can be performed in the waiting time with the prominent exception of implant tools. (It has to be noted though, that not all tools are capable of performing every setup in advance.) Hot lots dont lead to a similar capacity loss. Tools are not held idle for them, so no extra tool waiting time occurs. Yet, setup time is more significant than for super-hot lots because it cannot be performed within the waiting time. Moreover lotto-lot changeover times delay the processing of hot lots at some tools and cost capacity. This can for example be at a wet bench, when the hot lot flow and the flow of the previous lot dont match and the hot lot breaks the cascade of normal lots with matching flows. Then an additional delay occurs for the hot lot, in order to avoid the hot lot and the previous lot needing to use the same processing resource at the same time. Also for the same flow some negative interdependences caused by different process times can cause delays impacting capacity. The size of this capacity impact is more difficult to estimate on a high level than for super-hot lots, the best shot is to use a similar methodology. Again, the shorter cycle time

transfers the 5% lot share to a higher lot activity level, in this case ~12.5%. Assuming that setup and lot-to-lot changeover times add 10% on average to the capacity consumption of hot lots, then this represents a 1.25% capacity loss across all tools in the fab. Combined, the two priority lot subcategories cost nearly 5% of tool capacity. The specific capacity loss will vary across fabs. Depending on the business model as well as current fab loading and customer demand, IC makers will choose to have more or less priority lots than defined for ITRS targets and will tighten or soften the particular application of the handling policies. Without detailed data for real cycle time and lot share of priority lots, this remains the best shot though. V. IMPROVING CYCLE TIME Numerous studies have focused on the impact that different percentages of priority lots have on normal and priority lot cycle times (e.g. [4]), yet there has been hardly any work done on architectural ideas to improve priority lot cycle time. The architectural challenge and possible ideas to overcome them will be the focus of this section. For normal lot cycle time, smaller lot sizes and single wafer processing tools only have been identified by a number of IC manufacturers as key architectural elements to improve normal lot cycle time (see [1],[7] or [9]). But how promising are these changes for priority lots? For super-hot lots this analysis is fairly easy. The transport time component offers little scope for improvement as the lots already travel tool-to-tool or are hand-carried. So there is only one component to analyze, the raw process time. Even smaller lot sizes provide a comparably small leverage as five wafers is already considered to be a small size, and the share of raw process time influenced by lot sizes becomes less at smaller lot size. With no other variables in the overall equation, the only remaining option is to switch to single wafer tools. This however proves to be a very powerful leverage. Ref. [7] shows that at a near-equal lot size of six wafers more than 75% of process time occurs on batch tools. Therefore the possible raw process time reduction is very significant and [7] estimates it at 67% for the six wafer lot size and a complete switch from a toolset including batch tools to a single wafer toolset. For hot lots, the analysis is more complicated. The instorage queue time depends on how frequently tool load ports become available and the on-equipment queue time depends on how frequently a lot finishes processing at the tool, which is essentially the same. This frequency is the normal lot service rate and directly depends on the lot size of normal lots. So a reduction of normal lot size by 50% also reduces both these queue time components by 50%. (It has to be noted that this change only happens at single wafer tools and not batch tools.) For transport time there is no apparent reason to change significantly. The slowing impact by higher transport

119

Tool
Cycle Time

-59%

-53%

Super Hot

new Super Hot

Hot

new Hot

Raw Process Time On-Equipment Queue Time

Transport Time In-Storage Queue Time

Lot Queue Normal lot Super hot lot

Fig. 5. Cycle time improvements for priority lots

volume at smaller lot size could be offset by more advanced technology. Raw process time of hot lots can be influenced by both single wafer processing tools only and smaller lot size (as they are still 25 wafer lots). Both prove to be very effective. Ref. [7] gives a 64% reduction of raw process time for a switch from 25 to 12 wafer lot size and to a single wafer tools only. Fig. 5. summarizes the improvements identified to 59% for super-hot lots and 53% for hot lots.

Fig. 6. New sequence of events for super-hot lot processing

VI. DECREASING COST The key to decreasing the cost of priority lots has to be tackling the capacity losses identified in Section IV. The most significant cost contributor is holding tools empty prior to the arrival of super-hot lots. The solution to this problem seems to be obvious, yet it has not been implemented in equipments or at least a non-standardized back-door implementation has to be used. The basic idea is to use the tool capacity until the arrival of the super-hot lot and then interrupt the processing of the current normal lot to immediately start processing the super-hot lot. When all wafers of the super-hot lot are in the tool, then the remaining wafers of the interrupted lot are fed into the tool. In this way only a tool load port but not the complete tool has to be reserved. Fig. 6. illustrates this behavior. Processing of lot A is interrupted as soon as the super hot lot arrives at the tool. If no setup times or lot-to-lot changeover times are necessary, then this method is applicable without loss of super-hot cycle time and significantly improves equipment capacity. If setup or lot-to-lot changeover times occur then the solution can be more difficult if a small loss in super-hot lot cycle time is unacceptable. Then for example an outside system could send an interrupt-signal to the tool as soon as necessary, triggered by completion of a previous operation or similar event. However, it is improbable that such a system would yield optimal results and prevent the capacity loss completely.

For hot lots, its the other way around. As stated in Section IV, it is not justifiable to hold a tool empty because of the lower priority of hot lot processing. With this new method hot lots can make use of the cycle time advantage of immediate processing start without sacrificing capacity. Therefore at tools without setup/lot-to-lot changeover issues, hot lots could be upgraded to the more aggressive policy without equipment capacity loss. The cycle time savings at these operations can then be used to downgrade hot lot urgency at tools with setup and/or lot-to-lot changeover times to insert them into lot chains that dont cause setup or lot-to-lot changeover times. Of course, if it better matches the overall strategy the cycle time savings can also be conserved with continued acceptance of setup and lot-to-lot changeover losses. I300I proposed a processing order control system that enables ordering of unaccessed carriers or batches independent of its delivery. It demanded that production equipment must be able to set and change the order of processing as directed by the host and the operator interface. This is applicable to carriers waiting on load ports or equipment-internal buffers. It should be noted that not all tools support this ordering of unaccessed jobs at the load port/equipment buffer proposed by I300I yet, which is unacceptable from the IC maker perspective as this partially prevents the beneficial hot lot preferential treatment described in Section II/ Fig. 2. The new method proposed here simply goes one step further. Urgent lots can not only jump to the head of queue, they can also interrupt current lot processing. This interruption of lot processing can for example be triggered statically by lot priority or a specific job priority similar to the processing order control system for equipment buffer proposed by I300I in [3]. The obviousness of this solution leads to an obvious question: Why was this not done in the past or is not commonly done today? The answer is missing prerequisites and a different focus. The past focused on simplification and clear-cut

120

differentiation to avoid miss processing. Additionally difficulties of software and controls to track wafers properly limited the operational design flexibility. Therefore in the past, the proposed solution might have come as a trade-off with control or reliable operation. Now that the foundation of reliable, controlled processing is set, the priority can move to fab agility added on top of this foundation with the presented solution as one of its enablers. The solution discussed in this Section also highlights an important productivity detractor that needs resolution in 300 Prime. Setup and lot-to-lot changeover time have been noted several times as obstacles hindering efficient production. The urgency of solving this productivity challenge is intensified with this new method and with small lot size manufacturing in general. Examples of these detractors are recipe download length or equipment preparation activities such as conditioning or cleaning. Summarized, this new equipment functionality has the capability of eliminating most of the nearly 5% capacity losses described in Section II thereby decreasing overall fab costs by nearly the same amount. Alternatively, at slightly less capacity and cost savings, hot lot cycle time can be significantly sped up by achieving near-zero queue time. VII. 300 PRIME While the plan of accomplishing 50% cycle time reduction will clearly be shaped by transitioning away from batch tools by their replacement with single wafer tools and smaller lot sizes, the picture is somewhat less clear with regard to the desired 30% cost reduction at 300 Prime. Only a number of far reaching measures identified by equipment supplier and IC makers in cooperation can achieve such a target. The outlined methodology can be an essential part of the desired cost reduction, yet only a combination of improvements will enable the visionary target to be achieved. Among others, the opportunities and functionalities identified in this paper shaped AMDs 300 Prime vision. The complete view towards 300 Prime functionality and productivity includes the following seven items: 1. 100% single wafer processing toolset at competitive cost of ownership, with no large lot size batching/cascading required to achieve todays factory throughput levels 2. Rapid lot-to-lot setup/changeover allowing small lot manufacturing lot sizes 3. High volume, high speed, low variability AMHS suitable to small lot size manufacturing traffic 4. Predictable high-availability tools capable of meeting pre-scheduled frequency of production timing with near-zero maintenance variability 5. Flexibility to adapt quickly and synchronize the manufacturing flow with scheduling of components (WIP-incl. priority lots, tool qualifications, predictive maintenance, reticles) 6. Standardized, high frequency tool-parameter data use to populate tool health models to achieve predictive

maintenance control prior to tool failure or scrap of material 7. Continued waste reduction in areas of tool installation speed/standardization, TW usage, supply system configuration, utility consumption, layout standardization, and factory control systems setup VIII. SUMMARY This paper shows how substantial cycle time benefits for super-hot and hot lots can be achieved with a single wafer toolset and smaller lot size. These benefits can easily reach the 50% CT reduction range. Furthermore the paper emphasizes that the size of some hot lot cycle time components is driven by normal lot size while others depend on hot lot size only. Additionally, a new system of interrupting current jobs in process has been proposed to save cost associated with priority lot cycle time. Other benefits of this interruption system will be subject to future work. ACKNOWLEDGMENT The author wants to thank AMDs Industrial Engineering and Global Manufacturing Services teams for their tireless discussion and helpful contributions. Special thanks go to Thomas Alfieri, Gerald Goff, Les Marshall, Thomas Quarg, Oliver Rose and Ken Wallers for their valuable suggestions. REFERENCES
[1] O. Bonnin, D. Mercier, D. Levy, M. Henry, I. Pouilloux, E. Mastromatteo, Single-Wafer/Mini-Batch Approach for Fast Cycle Time in Advanced 300-mm Fab, IEEE Transactions on Semiconductor Manufacturing, Vol. 16, No. 2, pp. 111-120, 2000. J. Draina, ISMI 300 Prime / 450mm industry briefing, SEMICON Japan, 2006. J. Ferrell, M. Pratt, I300I Factory Guidelines: Version 5.0. Technology Transfer Document, International 300mm Initiative, International Sematech, 2000. D. Fronckowiak, A. Peikert, K. Nishinohara, Using discrete event simulation to analyze the impact of job priorities on cycle time in semiconductor manufacturing, IEEE/SEMI Advanced Semiconductor Manufacturing Conference, 1996. International Technology Roadmap for Semiconductors: 2005. L. Lee, K. Hsieh, M. Lin, R. Luoh, A. Ling, S. Huang, Super-hot-runs management system, The Ninth International Symposium on Semiconductor Manufacturing, Tokyo, 2000. K. Schmidt, O. Rose, Development and simulation assessment of semiconductor fab architectures for fast cycle times, Simulation and Visualization Conference, Magdeburg, 2007. K. Schmidt, O. Rose, Queue time and X-factor characteristics at smaller lot sizes, unpublished. T. Wakabayashi, S. Watanabe, Y. Kobayashi, T. Okabe, A. Koike, High-speed AMHS and its operation method for 300mm QTAT fab, IEEE Transactions on Semiconductor Manufacturing, Vol. 17, No. 3, pp. 25-28, 2004.

[2] [3]

[4]

[5] [6]

[7]

[8] [9]

121