SIRISHA KURAKULA G00831237 PROJECT

ADAPTIVE NOISE CANCELLATION

ABSTRACT The project deals with the hardware/software implementation of the Least Mean Square (LMS) adaptive filter based on the Adaptive Noise Canceller on the FPGAs using VHDL Hardware Description Language. The paper also provides details to implement adaptive filters using variations of the least mean square (LMS) and also the use of adaptive filters designed using this algorithm in the adaptive noise cancellation design. Blocks: adaptive filters, adaptive noise cancelling, FPGA, Xilinx system generator. Adaptive filters are essential components including : 1) signal detection; 2) echo cancellation; 3) noise cancellation; 4) channel equalization ; 5) system identification and inverse modeling of unknown systems; 6) forward and backward predictions and 6) spectral analysis. 1.ADAPTIVE LMS ALGORITHM The most commonly used algorithm to design least-mean-square (LMS) algorithm originally developed by Widrow and Hoff. One of the advantages of the LMS algorithm is its computational simplicity, ease of implementation, unbiased convergence, and the existence of a stationary environment. A block diagram of a typical adaptive noise cancellation system is shown below. Desired Signal d(k) + Adaptive Input Signal x(n) Output Signal y(n) error signal e(n) Filter

Adaptive Algorithm
Figure: Block diagram of an adaptive noise cancellation 1.1 Adaptive Noise Cancellation system In the noise cancellation, the adaptive filter is designed as a transversal FIR filter structure. This filter consists of three basic elements like unit delay elements, multipliers and adders. The unit delay elements are designed using the unit-delay operator z-1. The output of the unit-delay operator is a delayed copy of its input.

The method used to cancel the noise signal is known as adaptive filtering. Adaptive filters are dynamic filters which iteratively alter their characteristics in order to achieve an optimal desired output. An adaptive filter algorithmically alters its parameters in order to minimize a function of the difference between the desired output d(n) and its actual output y(n) . This function is known as the objective function of the adaptive algorithm. Where the x(n) is input signal, the filter H(n) represents the impulse response of the acoustic environment, W(n) represents the adaptive filter used to cancel the echo signal. The adaptive filter aims to equate its output y(n) to the desired output d(n). The external noise input n0(n) is neglected here. At each iteration the error signal, y(n) = xT(n)W(n), e(n) = d(n)-y(n) , is fed back into the filter, where the filter characteristics are altered accordingly. 2. Software model discussion This shows how to use the Least Mean Square (LMS) algorithm to subtract noise from an input signal. The LMS adaptive filter uses the reference signal on the Input port and the desired signal on the desired port to automatically match the filter response. As it converges to the correct filter model, the filtered noise is subtracted and the error signal should contain only the original signal. 2.1 Exploring the Model In the model, the signal output at the upper port of the Acoustic Environment subsystem is white noise. The signal output at the lower port is composed of colored noise and a signal from a .wav file. This model uses an adaptive filter to remove the noise from the signal output at the lower port. When you run the simulation, you hear both noise and a person playing the drums. Over time, the adaptive filter in the model filters out the noise so you only hear the drums. 2.2 Acoustic Noise Canceller Model The all-platform floating-point version of the model is shown below.

2.3 Utilizing Your Audio Device By running this model, we can listen to the audio signal in real time (while running the simulation). The stop time is set to infinity. This allows us to interact with the model while it is running. For example, we can change the filter or alternate from slow adaptation to fast adaptation (and vice versa), and get a sense of the real-time audio processing behavior under these conditions. 2.4 Color Codes of the Blocks Notice the colors of the blocks in the model. These are sample time colors that indicate how fast a block executes. Here, the fastest discrete sample time (e.g., the 8 kHz audio signal processing portion) is red, and the second fastest discrete sample time is green. You can see that the color changes from red to green after down-sampling by 32 (in the Downsample block before the Waterfall Scope block). Further information on displaying sample time colors can be found in the Simulink documentation. 2.5 Waterfall Scope The Waterfall window displays the behavior of the adaptive filter's filter coefficients. It displays multiple vectors of data at one time. These vectors represent the values of the filter's coefficients of a normalized LMS adaptive filter, and are the input data at consecutive sample times. The data is displayed in a three-dimensional axis in the Waterfall window. By default, the x-axis represents amplitude, the y-axis represents samples, and the z-axis represents time. The Waterfall window has toolbar buttons that enable you to zoom in on displayed data, suspend data capture, freeze the scope's display, save the scope position, and export data to the workspace.

2.6 Acoustic Environment Subsystem You can see the details of the Acoustic Environment subsystem by double clicking on that block. Gaussian noise is used to create the signal sent to the Exterior Mic output port. If the input to the Filter port changes from 0 to 1, the Digital Filter block changes from a lowpass filter to a bandpass filter. The filtered noise output from the Digital Filter block is added to the signal coming from a .wav-file to produce the signal sent to the Pilot's Mic output port. 3. FPGA IMPLEMENTATION OF LMS ALGORITHM 3.1 Processing of positive and negative number The data is processed by FPGA such as the input signal, the coefficients of filter may be positive or negative. Accordingly, it is necessary to employ sign number for expressing the all data inside FPGA. Based on the expression method of the sign number, the highest bit is used as sign bit. In the highest bit, binary digit "0" denotes positive number and binary digit "1" expresses negative number. 3.2 Floating-point representation of Data All the data is represented as floating point numbers. IEEE 754 format is used for the representation of data. It is a 32 bit binary number with 32th bit indicating the sign bit- "1" indicating a negative number and "0" a positive number. The value of a IEEE-754 number is computed as: sign 2exponent mantissa. The sign is stored in bit 32. The exponent can be computed from bits 24-31 by subtracting 127. The mantissa (also known as significand or fraction) is stored in bits 1-23. An invisible leading bit (i.e. it is not actually stored) with value 1.0 is placed in front, then bit 23 has a value of 1/2, bit 22 has value 1/4 etc. As a result, the mantissa has a value between 1.0 and 2. If the exponent reaches -127 (binary 00000000), the leading 1 is no longer used to enable gradual underflow. 3.3 FPGA-based system structure of LMS algorithm The whole system is divided into data storage module, state control module, output computation module, error adjustment module, and weight update module, and each module has itself function. The whole system is shown in Fig.2. 3.3.1 Data storage module Data storage module is employed for storing input signal x(k) , the desired signal d(k) , and the weight value w(k). At the same time, for providing the data for the latter operation, based on the number system of the floating-point operation, the extendibility of data bit corresponding to the data must be carried out. Embedded Array Block(EAB) inside FPGA is used as assuming the function of data storage. 3.3.2 State control module The function of state control module consists in the initialization of system and controlling the time sequence of each module. On the basis of analyzing detailed the computation process of LMS algorithm and the time sequence relations among modules, the strict state control method that make the system, which is controlled by the clock signal and the signals of functionality, work in pipeline manner of series-parallel combination.

3.3.3 Output computation module Output computation module, in the action of control signals, completes convulsion operation between the input signal x(k) and the weight value w(k) and exports the computation results to the error adjustment module or the output port. This logic cell needs a mass of multiplication operations. Although the parallel-adopted system can improve the real-time processing performance of the system, it enhances the spending of FPGA resource. For example, eight-order FIR requiring eight multipliers can complete a computation of the output. Accordingly, the processing of the global parallel or local parallel is adopted, weight vector is divided into some groups, and each group includes two weight values. Serial operation is designed within a group and parallel operation is carried out among groups. The multiplier works in the manner of timesharing multiplexing in order to reduce number of multipliers, to improve the availability of the FPGA resource, and to make use of the advantages of the FPGA modularization at the same time, so it is fit for the expanding the system. 3.3.4 Error adjustment module First, we can obtain the output error (k) from error adjustment module according to the desired signal d(k) and the output y(k) to the filter. Then, 2 k calculated and used as the iterative factor of weight vector. The function of this logic cell consists in realizing subtraction and multiplication operation. 4. VHDL IMPLEMENTATION DISCUSSION A VHDL description has two main parts. They are the entity part and the architecture part. The entity describes the system as a single component as seen by external devices. This part provides information about the systems interface while revealing nothing about its internal structure and behavior. The architecture part of a VHDL description is used to specify the behavior and the internal structure of the system. Steps a) VHDL is conductive to top-down design. So the whole system is described at the block diagram level and each component in the diagram is described in further detail. b) The system can be simulated at each level of design to observe the output. The design flow can be illustrated in the code. c) Once the design of the system is completed, the corresponding program is entered and synthesized. d) The Xilinx ISE 14.2i software package is used in this project to implement the VHDL program. e) The system is simulated to observe and verify its behavior. The design is then implemented on the FPGA chip. 5. PERFORMANCE COMPARISONS -Area (LUT space, etc.) -Critical Path (how fast can it be clocked) -Latency (# clock cycles before output is available) -Throughput (Number of outputs per cycle)

6. Conclusion and Final Thoughts The FPGA platform is well suited for the complex real time audio processing. An adaptive noise cancellation process has successfully been implemented. When tested with different signals the system showed improved performance compared to original signal. For future work, I think that it should be implemented with LMS algorithm and try to remove The Adaptive filter is designed using VHDL where the inputs are, i) Distorted signal, r(n) 32 bits. ii) Desired signal, d(n) 32 bits. iii) Clock 1 bit. And the outputs are, i) Output, y(n) 32 bits. ii) Ready output 1 bit. Future Work This method is mostly used in the noise cancellation in the headset. At present, most of this method is used in the most popular headphone seller beats. In the future, we will be using more precise microphone to acquire more accurate measurements. References 1. Acoustic Noise Cancellation (LMS) Software Model using Simulink http://www.mathworks.com/help/dsp/examples/acoustic-noise-cancellationlms.html?searchHighlight=dspanc#zmw57dd0e4637 2. Using Simulink in Signal Processing Applications http://faculty.nps.edu/fargues/teaching/ec4440/SimulinkIntroFallFY12.pdf 3. Adaptive Noise Cancellation http://www.cs.cmu.edu/~aarti/pubs/ANC.pdf 4. Adaptive Noise Cancelling for Speech Signals http://www.csie.ntu.edu.tw/~b96066/homework/DSignalP/Adaptive%20Noise%20Canceling%2 0for%20Speech%20Signals.pdf 5. Software/ Hardware Implementation of an Adaptive Noise Cancellation Using LMS algorithm https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=5&cad=rja&uact=8&ve d=0CFYQFjAE&url=http%3A%2F%2Fwww.asee.org%2Fpublic%2Fconferences%2F20%2Fpa pers%2F6147%2Fdownload&ei=d5ZdU5q8FrGmsAS2noGYBg&usg=AFQjCNFv74XxvCoC9 DWwSEn4_PN0tIMVrA&sig2=C7cnpXuHcpbbjEkgbvC6iQ Appendix A: software model in zip file Appendix B: VHDL code, testbench, and testvectors in zip file

ADAPTIVE NOISE FILTER CANCELLATON VHDL CODE ----------------------------------------------------------------adaptivefilter.vhd ----------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity adaptivefilter is port ( A1: in std_logic_vector(31 downto 0); B1: in std_logic_vector(31 downto 0); mult: in std_logic_vector(31 downto 0); nfi: in std_logic; rffi: out std_logic; clk: in std_logic; resultfi: out std_logic_vector(31 downto 0); rdyfi: out std_logic); end adaptivefilter; architecture Behavioral of adaptivfilter is signal xin0 : std_logic_vector(31 downto 0):= "11000000000000000000000000000000"; signal xin1 : std_logic_vector(31 downto 0):= "11000000000000000000000000000000"; signal wt0 : std_logic_vector(31 downto 0):= "11000000000000000000000000000000"; signal wt1 : std_logic_vector(31 downto 0):= "11000000000000000000000000000000"; signal rfmul0, rfmul1, rfmul2, rfmul3, rfmul4, rfad0, rfad1, rfad2, rfsub0 : std_logic:=1; signal resultad0, resultad1, resultad2, resultmul0, resultmul1, resultmul2, resultmul3, resultmul4, resultsub0 : std_logic_vector(31 downto 0):= "11000000000000000000000000000000"; signal nfi2, nadd, nsub0, rdymul0, rdymul1, rdymul2, rdymul3, rdymul4,rdyad0, rdyad1, rdyad2, rdysub0:std_logic:=0; component fadder port ( a: in std_logic_vector(31 downto 0);

b: in std_logic_vector(31 downto 0); operation: in std_logic_vector(5 downto 0); operation_n: in std_logic; operation_rf: out std_logic; clk: in std_logic; result: out std_logic_vector(31 downto 0); rdy: out std_logic); end component; component fmultiplier port ( a: in std_logic_vector(31 downto 0); b: in std_logic_vector(31 downto 0); operation_n: in std_logic; operation_rf: out std_logic; clk: in std_logic; result: out std_logic_vector(31 downto 0); rdy: out std_logic); end component; begin mul0: fmultiplier port map(xin0,wt0,nfi2,rfmul0,clk,resultmul0,rdymul0); mul1: fmultiplier port map(xin1,wt1,nfi2,rfmul1,clk,resultmul1,rdymul1); nadd<=rdymul0; add0: fadder port map (resultmul0,resultmul1,"000000",nadd,rfad0,clk,resultad0,rdyad0); add1: fadder port map (wt0,resultmul3,"000000",rdymul4,rfad1,clk,resultad1,rdyad1); add2: fadder port map (wt1,resultmul4,"000000",rdymul4,rfad2,clk,resultad2,rdyad2); sub: fadder port map (B1,resultad0,"000001",rdyad0,rfsub0,clk,resultsub0,rdysub0); mul2: fmultiplier port map (mult,resultsub0,rdysub0,rfmul2,clk,resultmul2,rdymul2); mul3: fmultiplier port map (resultmul2,xin0,rdymul2,rfmul3,clk,resultmul3,rdymul3); mul4: fmultiplier port map (resultmul2,xin1,rdymul2,rfmul4,clk,resultmul4,rdymul4); resultfi<=resultad0; rdyfi<=rdyad2;--last ready output rffi<=rdyad0;--last ready for data;not giving; process( nfi) begin nfi2<=nfi; end process;

READ_NET: process begin wait until nfi = 1; xin1<=xin0; xin0<= A1; end process READ_NET; READ_wt: process begin wait until rdyad2= 1; wt0<=resultad1; wt1<=resultad2; end process READ_wt; end Behavioral;

-----------------------------------------------------------testbench.vhd -----------------------------------------------------------LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values USE ieee.numeric_std.ALL; ENTITY testbench is END testbench; ARCHITECTURE behavior OF testbench IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT adaptivefilter PORT( A1 : IN std_logic_vector(31 downto 0); B1 : IN std_logic_vector(31 downto 0); mult : IN std_logic_vector(31 downto 0); nfi : IN std_logic; rffi : OUT std_logic; clk : IN std_logic; resultfi : OUT std_logic_vector(31 downto 0); rdyfi : OUT std_logic); END COMPONENT; signal A1 : std_logic_vector(31 downto 0) := (others => 0); signal B1 : std_logic_vector(31 downto 0) := (others => 0); signal mult : std_logic_vector(31 downto 0) := "00111110000110011001100110011010"; --(0.15)

signal signal signal signal signal

nfi : std_logic := 0; clk: std_logic := 0; rffi : std_logic; resultfi : std_logic_vector(31 downto 0); rdyfi : std_logic;

-- Clock period definitions constant clk_period: time := 2000 ns; constant nd_period: time := 0.02 ms; BEGIN -- Instantiate the Unit Under Test (UUT) uut: adaptivfilter PORT MAP ( A1 => A1, B1 => B1, mult => mult, nfi => nfi, rffi => rffi, clk => clk, resultfi => resultfi, rdyfi => rdyfi); -- Clock process definitions clk_process :process begin clk <= 0; wait for clk_period/2; clk <= 1; wait for clk_period/2; end process; nfi_process :process begin nfi <= 0; wait for 500 ns ; nfi <= 1; wait for clk_period; nfi <= 0; wait for 0.175 ms ; end process; REA_NET: process begin A1 <="00111111100000000000000000000000"; B1 <="00111110100111100011011101111010"; wait for nd_period; A1 <="00111110100111100011011101111010"; B1 <="00111111100000000000000000000000"; wait for nd_period; A1 <="10111111010011110001101110111101";

B1 <="00111110100111100011011101111010" ; wait for nd_period; A1 <="10111111010011110001101110111101"; B1 <="10111111010011110001101110111101"; wait for nd_period; A1 <="00111110100111100011011101111010"; B1 <="10111111010011110001101110111101"; wait for nd_period; end process REA_NET; END behavior;