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Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Computer Architecture and

Organization

Miles Murdocca and Vincent Heuring

Appendix A Digital

Logic

A-2 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Chapter Contents

A.1 Introduction

A.2 Combinational Logic

A.3 Truth Tables

A.4 Logic Gates

A.5 Properties of Boolean

Algebra

A.6 The Sum-of-Products Form

and Logic Diagrams

A.7 The Product-of-Sums Form

A.8 Positive vs. Negative Logic

A.9 The Data Sheet

A.10 Digital Components

A.11 Sequential Logic

A.12 Design of Finite State

Machines

A.13 Mealy vs. Moore Machines

A.14 Registers

A.15 Counters

A.16 Reduction of Combinational

Logic and Sequential Logic

A.17 Reduction of Two-Level

Expressions

A.18 State Reduction

A-3 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Some Denitions

Combinational logic: a digital logic circuit in which logical decisions

are made based only on combinations of the inputs. e.g. an adder.

Sequential logic: a circuit in which decisions are made based on

combinations of the current inputs as well as the past history of

inputs. e.g. a memory unit.

Finite state machine: a circuit which has an internal state, and

whose outputs are functions of both current inputs and its internal

state. e.g. a vending machine controller.

A-4 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

The Combinational Logic Unit

Translates a set of inputs into a set of outputs according to one or

more mapping functions.

Inputs and outputs for a CLU normally have two distinct (binary)

values: high and low, 1 and 0, 0 and 1, or 5 V. and 0 V. for example.

The outputs of a CLU are strictly functions of the inputs, and the

outputs are updated immediately after the inputs change. A set of

inputs i

0

i

n

are presented to the CLU, which produces a set of

outputs according to mapping functions f

0

f

m.

A-5 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Truth Tables

Developed in 1854 by George Boole

further developed by Claude Shannon (Bell Labs)

Outputs are computed for all possible input combinations (how

many input combinations are there?

Consider a room with two light switches. How must they work

Don't show this to your electrician, or wire your house this way. This circuit denitely

violates the electric code. The practical circuit never leaves the lines to the light "hot"

when the light is turned off. Can you gure how?

A-6 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Alternate Assignments of Outputs to

Switch Settings

Logically identical truth table to the original (see previous slide), if

the switches are congured up-side down.

A-7 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Truth Tables Showing All Possible

Functions of Two Binary Variables

The more frequently used functions have names: AND, XOR, OR,

NOR, XOR, and NAND. (Always use upper case spelling.)

A-8 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Logic Gates and Their Symbols

Note the use of the inversion bubble.

(Be careful about the nose of the gate when drawing AND vs. OR.)

Logic symbols

for AND, OR,

buffer, and NOT

Boolean

functions

A-9 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Logic symbols for NAND, NOR, XOR,

and XNOR Boolean functions

A-10 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Variations of Basic Logic Gate

Symbols

A-11 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

The Inverter at the Transistor Level

Transistor

Symbol

Power

Terminals

A Transistor Used

as an Inverter

Inverter Transfer

Function

A-12 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Allowable Voltages in Transistor-

Transistor-Logic (TTL)

Assignments of logical 0 and 1 to voltage ranges (left) at the output of a

logic gates, (right) at the input to a logic gate.

A-13 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Transistor-Level Circuits For

2-Input NAND and NOR Gates

A-14 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

CMOS Congurations

CMOS congurations for (a) NOT, (b) NOR, and (c) NAND gates.

Schematic symbols for (left) n-channel transistor and (right) p-channel

transistor.

A-15 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Tri-State Buffers

Outputs can be 0, 1, or electrically disconnected.

A-16 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

The Basic Properties of Boolean

Algebra

A, B, etc. are

literals; 0 and 1

are constants.

Principle of

duality: The dual

of a Boolean

function is made

by replacing AND

with OR and OR

with AND,

constant 1s by 0s,

and 0s by 1s

A-17 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

DeMorgan!s Theorem

Discuss: Applying DeMorgan!s theorem by pushing the bubbles,

and bubble tricks.

A-18 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

NAND Gates Can Implement AND and

OR Gates

Inverted inputs to a NAND gate are implemented with NAND gates.

A-19 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

The Sum-of-Products (SOP) Form

Transform the function into a two-level AND-OR equation

Implement the function with an arrangement of logic gates from the

set {AND, OR, NOT}

M is true when A=0, B=1, and C=1, or when A=1, B=0, and C=1,

and so on for the remaining cases.

Represent logic equations by using the sum-of-products (SOP)

form

Truth Table for The

Majority Function

A-20 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

The SOP Form of the Majority Gate

The SOP form for the 3-input majority gate is:

M = ABC + ABC + ABC + ABC = m3 + m5 +m6 +m7 = ! (3, 5, 6, 7)

Each of the 2

n

terms are called minterms, running from 0 to 2

n

- 1

Note the relationship between minterm number and boolean value.

Discuss: common-sense interpretation of equation.

A-21 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

A 2-Level AND-OR Circuit Implements

the Majority Function

The encircled T intersections are electrically common (see next slide).

A-22 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Notation Used at Circuit Intersections

A-23 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

A 2-Level OR-AND Circuit Implements

the Majority Function

A-24 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Positive vs. Negative Logic

Positive logic: truth, or assertion is represented by logic 1, higher voltage;

falsity, de- or unassertion, logic 0, is represented by lower voltage.

Negative logic: truth, or assertion is represented by logic 0 , lower

voltage; falsity, de- or unassertion, logic 1, is represented by lower voltage

A-25 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Positive and Negative Logic (Cont!d.)

A-26 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Bubble Matching

Active low signals are signied by a prime or overbar or /.

Active high: enable

Active low: enable!, enable, enable/

Ex: microwave oven control:

Active high: Heat = DoorClosed Start

Active low: ? (hint: begin with AND gate as before.)

A-27 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Bubble Matching (Cont!d.)

A-28 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

The Data

Sheet

A-29 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Digital Components

High level digital circuit designs are normally made using collections

of logic gates referred to as components, rather than using

individual logic gates. The majority function can be viewed as a

component.

Levels of integration (numbers of gates) in an integrated circuit (IC):

Small scale integration (SSI): 10-100 gates.

Medium scale integration (MSI): 100 to 1000 gates.

Large scale integration (LSI): 1000-10,000 logic gates.

Very large scale integration (VLSI): 10,000-upward.

These levels are approximate, but the distinctions are useful in

comparing the relative complexity of circuits.

Let us consider several useful MSI components:

A-30 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

The Multiplexer

A-31 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Gate-Level Layout of Multiplexer

A-32 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Implementing the Majority Function

with an 8-1 Mux

Principle: Use the mux select to pick out the selected minterms of the

function.

A-33 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Efciency: Using a 4-1 Mux to

Implement the Majority Function

Principle: Use the A and B inputs to select a pair of minterms.

The value applied to the MUX input is selected from {0, 1, C, C}

to pick the desired behavior of the minterm pair.

A-34 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

The Demultiplexer (DEMUX)

A-35 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

The Demultiplexer is a Decoder with

an Enable Input

A-36 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

A 2-to-4 Decoder

A-37 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Using a 3-to-8 Decoder to Implement

the Majority Function

A-38 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

The Priority Encoder

An encoder translates a set of inputs into a binary encoding,

Can be thought of as the converse of a decoder.

A priority encoder imposes an order on the inputs.

A

i

has a higher priority than A

i+1

A-39 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Programmable Logic Arrays (PLAs)

A PLA is a

customizable AND

matrix followed by a

customizable OR

matrix:

A-40 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Using a PLA to Implement the Majority

Function

A-41 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Using PLAs to Implement an Adder

A-42 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

A Multi-Bit Ripple-

Carry Adder

PLA Realization of a

Full Adder

A-43 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Sequential Logic

The combinational logic circuits we have been studying so far have

no memory. The outputs always follow the inputs.

There is a need for circuits with memory, which behave differently

depending upon their previous state.

An example is a vending machine, which must remember how many

coins and what kinds of coins have been inserted. The machine

should behave according to not only the current coin inserted, but also

upon how many coins and what kinds of coins have been inserted

previously.

These are referred to as nite state machines, because they can

have at most a nite number of states.

A-44 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Classical Model of a Finite State

Machine

An FSM is

composed of a

combinational logic

unit and delay

elements (called ip-

ops) in a feedback

path, which

maintains state

information.

A-45 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

NOR Gate with Lumped Delay

The delay between input and output (which is lumped at the output

for the purpose of analysis) is at the basis of the functioning of an

important memory element, the ip-op.

A-46 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

S-R Flip-Flop

The S-R ip-op is an active high (positive logic) device.

A-47 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

NAND Implementation of S-R Flip-Flop

A NOR implementation of an S-R ip-op is converted into a NAND

implementation.

A-48 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

A Hazard

It is desirable to be able to turn off the ip-op so it does not respond

to such hazards.

A-49 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

A Clock Waveform: The Clock Paces

the System

In a positive logic system, the action happens when the clock is

high, or positive. The low part of the clock cycle allows propagation

between subcircuits, so that the signals settle at their correct values

when the clock next goes high.

A-50 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Scientic Prexes

For computer memory, 1K = 2

10

= 1024. For everything else, like clock

speeds, 1K = 1000, and likewise for 1M, 1G, etc.

A-51 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Clocked S-R Flip-Flop

The clock signal, CLK, enables the S and R inputs to the ip-op.

A-52 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Clocked D Flip-Flop

The clocked D ip-op, sometimes called a latch, has a potential

problem: If D changes while the clock is high, the output will also

change. The Master-Slave ip-op (next slide) addresses this problem.

A-53 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Master-Slave Flip-Flop

The rising edge of the clock loads new data into the master, while the

slave continues to hold previous data. The falling edge of the clock

loads the new master data into the slave.

A-54 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Clocked J-K Flip-Flop

The J-K ip-op eliminates the disallowed S=R=1 problem of the S-R

ip-op, because Q enables J while Q! disables K, and vice-versa.

However, there is still a problem. If J goes momentarily to 1 and then

back to 0 while the ip-op is active and in the reset state, the ip-op will

catch the 1. This is referred to as 1!s catching.

The J-K Master-Slave ip-op (next slide) addresses this problem.

A-55 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Master-Slave J-K Flip-Flop

A-56 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Clocked T Flip-Flop

The presence of a constant 1 at J and K means that the ip-op will

change its state from 0 to 1 or 1 to 0 each time it is clocked by the T

(Toggle) input.

A-57 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Negative Edge-Triggered D Flip-Flop

When the clock is high,

the two input latches

output 0, so the Main

latch remains in its

previous state, regardless

of changes in D.

When the clock goes

high-to-low, values in the

two input latches will

affect the state of the

Main latch.

While the clock is low,

D cannot affect the Main

latch.

A-58 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Example: Modulo-4 Counter

Counter has a clock input (CLK) and a RESET input.

Counter has two output lines, which take on values of 00, 01, 10, and 11

on subsequent clock cycles.

A-59 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

State

Transition

Diagram for

Mod-4

Counter

A-60 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

State Table for Mod-4 Counter

A-61 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

State Assignment for Mod-4 Counter

A-62 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Truth Table for Mod-4 Counter

A-63 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Logic Design for Mod-4 Counter

A-64 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Example: A Sequence Detector

Example: Design a machine that outputs a 1 when exactly two of the last

three inputs are 1.

e.g. input sequence of 011011100 produces an output sequence of

001111010.

Assume input is a 1-bit serial line.

Use D ip-ops and 8-to-1 multiplexers.

Start by constructing a state transition diagram (next slide).

A-65 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Sequence Detector State Transition

Diagram

Design a machine that

outputs a 1 when exactly

two of the last three inputs

are 1.

A-66 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Sequence Detector State Table

A-67 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Sequence Detector State Assignment

A-68 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Sequence Detector Logic Diagram

A-69 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Example: A Vending Machine

Controller

Example: Design a nite state machine for a vending machine controller

that accepts nickels (5 cents each), dimes (10 cents each), and quarters

(25 cents each). When the value of the money inserted equals or exceeds

twenty cents, the machine vends the item and returns change if any, and

waits for next transaction.

Implement with a PLA and D ip-ops.

A-70 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Vending Machine State Transition

Diagram

A-71 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Vending Machine State Table and

State Assignment

A-72 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

PLA Vending Machine Controller

A-73 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Moore Counter

Mealy Model: Outputs are functions of Inputs and Present State.

Previous FSM designs were Mealy Machines, in which next state was

computed from present state and inputs.

Moore Model: Outputs are functions of Present State only.

A-74 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Four-Bit Register

Makes use of tri-state buffers so that multiple registers can gang their

outputs to common output lines.

A-75 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Left-Right Shift Register with Parallel

Read and Write

A-76 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Modulo-8 Counter

Note the use of the T ip-ops, implemented as J-K!s. They are used to

toggle the input of the next ip-op when its output is 1.

A-77 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Reduction (Simplication) of

Boolean Expressions

It is often possible to simplify the canonical SOP (or POS) forms.

A smaller Boolean equation generally translates to a lower gate count in

the target circuit.

We cover three methods: algebraic reduction, Karnaugh map reduction,

and tabular (Quine-McCluskey) reduction.

A-78 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Reduced Majority Function Circuit

Compared with the AND-OR circuit for the unreduced majority function,

the inverter for C has been eliminated, one AND gate has been

eliminated, and one AND gate has only two inputs instead of three

inputs. Can the function by reduced further? How do we go about it?

A-79 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

The Algebraic Method

Consider the majority function, F. We apply the algebraic method to

reduce F to its minimal two-level form:

A-80 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

The Algebraic Method

This majority circuit is functionally equivalent to the previous majority

circuit, but this one is in its minimal two-level form:

A-81 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Karnaugh Maps: Venn Diagram

Representation of Majority Function

Each distinct region in the Universe represents a minterm.

This diagram can be transformed into a Karnaugh Map.

A-82 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

K-Map for Majority Function

Place a 1 in each cell that corresponds to that minterm.

Cells on the outer edge of the map wrap around

A-83 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Adjacency Groupings for Majority

Function

F = BC + AC + AB

A-84 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Minimized AND-OR Majority

Circuit

F = BC + AC + AB

The K-map approach yields the same minimal two-level form as the

algebraic approach.

A-85 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

K-Map Groupings

Minimal grouping is on the left, non-minimal (but logically equivalent) grouping

is on the right.

To obtain minimal grouping, create smallest groups rst.

A-86 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

K-Map Corners are Logically

Adjacent

A-87 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

K-Maps and Don!t Cares

There can be more than one minimal grouping, as a result of don!t

cares.

A-88 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

3-Level Majority Circuit

K-Kap Reduction results in a reduced two-level circuit (that is, AND

followed by OR. Inverters are not included in the two-level count).

Algebraic reduction can result in multi-level circuits with even fewer

logic gates and fewer inputs to the logic gates.

A-89 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Truth Table with Don!t Cares

A truth table

representation of a

single function with

don!t cares.

A-90 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Tabular (Quine-McCluskey)

Reduction

Tabular reduction begins

by grouping minterms for

which F is nonzero

according to the number

of 1!s in each minterm.

Don!t cares are

considered to be

nonzero.

The next step forms a

consensus (the logical

form of a cross product)

between each pair of

adjacent groups for all

terms that differ in only

one variable.

A-91 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Table of Choice

The prime implicants form a set that completely covers the function,

although not necessarily minimally.

A table of choice is used to obtain a minimal cover set.

A-92 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Reduced Table of Choice

In a reduced table of choice, the essential prime implicants and the

minterms they cover are removed, producing the eligible set.

F = ABC + ABC + BD + AD

A-93 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Multiple Output Truth Table

The power of tabular reduction comes into play for multiple functions,

in which minterms can be shared among the functions.

A-94 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Multiple Output Table of Choice

F

0

(A,B,C) = ABC + BC

F

1

(A,B,C) = AC + AC + BC

F

2

(A,B,C) = B

A-95 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Speed and Performance

The speed of a digital system is governed by:

the propagation delay through the logic gates, and

the propagation delay across interconnections.

We will look at characterizing the delay for a logic gate, and a method

of reducing circuit depth using function decomposition.

A-96 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Propagation Delay for a NOT Gate

(Adapted from: Hamacher et. al. 2001)

A-97 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

MUX Decomposition

A-98 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

OR-Gate Decomposition

Fanin affects circuit depth.

A-99 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

State Reduction

Description of state machine M

0

to be reduced.

A-100 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Distinguishing Tree

A next state tree for M

0

.

A-101 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Reduced State Table

A reduced state table for machine M

1

.

A-102 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Sequence Detector State

Transition Diagram

A-103 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Sequence Detector State Table

A-104 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Sequence Detector Reduced State

Table

A-105 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Sequence Detector State

Assignment

A-106 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Sequence Detector K-Maps

K-map reduction

of next state and

output functions

for sequence

detector.

A-107 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Sequence

Detector

Circuit

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