signal integrity analyzer is a core nanometer technology in
the Cadence
Encounter
digital IC design platform. It identifies nets with low
noise immunity to avert potential noise-related problems and lethal silicon failures before tapeout. The CeltIC analyzer accurately calculates the impact of noise on both the delay and functionality of cell-based designs. It performs SoC noise analysis and generates repairs back into place-and-route. KEY FEATURES AND BENEFITS Isolates and repairs crosstalk-induced functional and delay failures Calculates the impact of noise on delay and slew for feedback to STA Reduces SI closure iterations by filtering false failures by over 10 to 100X versus other crosstalk analyzers Predicts functional, timing, and yield problems resulting from bootstrap and overshoot/undershoot noise Performs accurate glitch propagation to verify noise immunity with no additional overhead characterization Performs internal timing window convergence to reduce pessimism Automates noise library creation for cells, memories, I/Os, and custom macros Handles multimillion SoC designs flat or hierarchically using ECHO models NOISE IN DIGITAL DESIGN As designs migrate to nanometer technologies, the amount of coupling capacitance between wires increases to more than 70% of the total wire capacitance. Combined with increases in on-chip slew rates, this leads to a dramatic increase in on-chip noise. As a result, chips are now failing, under-performing, or suffering from low yields. DELAY UNCERTAINTY Coupling noise can change critical path delays and lead to unforeseen setup or hold violations. This delay uncertainty can result in additional iterations to achieve timing, or in missed performance targets. CeltIC analyzer calculates the impact of crosstalk on delay and slew for all nets using a combination of cell- and transistor-level models. For very noisy nets that exhibit non-linear behavior, CeltIC analyzer uses an on-the-fly fast transient simulation engine to calculate noise-on-delay effects and ensure SPICE-like accuracy. CeltIC Timing windows, slews SPEF SDF Repairs Synthesis/ place-and-route RC extraction CeltIC Static timing LVS/DRC Tapeout CeltIC CeltIC Virtual prototyping Figure 1: CeltIC design flow GLITCH PROPAGATION Coupling noise can be severe enough to cause functional failures. The problem is exacerbated with IR drop, which makes the design more susceptible to noise. CeltIC analyzer accurately calculates the worst-case glitch created by the combined impact of instance-specific IR drop and coupling aggressors. CeltIC analyzer guarantees functional validity by performing glitch noise propagation to register endpoints and ensuring that the register is not driven unstable. Using noise propagation to register endpoints reduces the number of false noise violations by an order of magnitude compared to using glitch peak, area-based, or rejection curve-based checks. This translates to less work for place-and-route systems and reduced SI closure iterations. NOISE LIBRARY CeltIC analyzer is designed to handle multimillion-gate designs. To efficiently support large designs, it uses a characterized noise library that is especially tailored for accurate noise analysis. The library contains each cell's holding strength using a series of I/V curves along with input noise thresholds. CeltIC analyzer supplies the utility to create this noise library (.cdB) directly from analysis of the extracted netlist view of each cell. The noise library creation process is very efficient, taking only minutes to characterize a complete standard cell library. The CeltIC characterization utility can also create noise views for memories, I/Os, and custom macros. In addition, pre- characterized CeltIC noise libraries are available from popular standard cell and memory IP vendors. DATA FLOW CeltIC analyzer requires a cell-level netlist with coupled RC parasitics in SPEF format, a noise library, and a Tcl control file. Verilog
DSPF, and DEF
netlist formats are also supported. CeltIC analyzer can generate timing windows from design constraints in SDC format and timing libraries in Liberty (.lib) format. It will iterate between noise-on-delay calculation and internal timing analysis to create a converged set of timing windows. Timing windows are used to improve the realism of the analysis and to reduce false failures. Alternatively, timing windows and slews can be imported from external static timing analyzers using the provided Tcl utilities. CeltIC analyzer outputs a sorted noise report in HTML format which details the peak noise for each victim net and the noise contributors. The glitch noise waveform can be displayed graphically by clicking the appropriate link in the HTML report. It also outputs a delay uncertainty report in HTML format sorted by relative or absolute delay change. The delay changes can be exported as SDF to static timing analyzers for final static timing verification. Additionally, CeltIC analyzer reports the effective impact of crosstalk on slew. The output reports can also be customized using a Tcl API. HIERARCHICAL CROSSTALK ANALYSIS CeltIC analyzer supports two hierarchical noise models: a user- defined noise (UDN) model and an ECHO model. UDNs can be used for portions of a design that are not yet complete, or for non-digital blocks such as analog cores. ECHO models can be created by CeltIC analyzer or from transistor-level noise analysis of custom digital cores with PacifIC analyzer. Through the use of these modeling schemes, CeltIC analyzer is capable of performing full-chip noise analysis of very large SoC designs. CROSSTALK FIXING CeltIC analyzer generates fixes for both crosstalk-induced timing and functional problems. It generates repair commands to drive both Cadence third-party place-and-route systems. Repairs include buffer insertion, driver sizing, wire spacing, and shielding. PLATFORMS Unix (32-bits, 64-bits) Linux (32-bits, 64-bits) FOR MORE INFORMATION Email us at icinfo@cadence.com or log on to www.cadence.com 2V 1V 0V 1 0ns 1 2ns 1 4ns 1 6ns TIME a1, a2 Victim (no coupling) in Victim Impact of noise on delay Figure 3: Noise caused by coupling can increase the delay of a single logic stage by over 100% Figure 2: CeltIC analyzer accuracy and false-failure filtering reduces violations by 10 to 100x 2003 Cadence Design Systems, Inc. All rights reserved. Cadence, Verilog, and the Cadence logo are registered trademarks and CeltIC, Encounter, and PacifIC are trademarks of Cadence Design Systems, Inc. All others are properties of their respective holders. 3073G 11/03 a1 in a2 victim out 115K nets .18mm 174K nets .15mm 1.4M nets 457K nets .130nm 532K nets .130nm 176 100,000 10,000 1,000 100 10 1 401 1,083 9,760 6,500 1 1 40 21 4