NATIONAL INSTIUTTE OF TECHOLOGY: TIRUCHIRAPALLI-15

DEPARTMENT OF COMPUTER SCIENCE AND ENGG

B. Tech. ( CSE ) - IV SEMESTER
DIGITAL SYSTEM DESGIN
A!"#$e#% &'e%!(#

R()) #(: F*($ 1+,111++1 %( 1+,111+1-

1.Design a circuit for BCD to Excess-3 code conversion.
2.Implement the boolean expression
!"#$B$C$D% & "'$($)$13$1*%
d"#$B$C$D% & "2$*$1'% using decoder.
3.Design a ) bit magnitude comparator.
*.Design the se+uential circuit specified b, the state according to the diagram.
-.Design a *-bit Binar, .ipple counter.
(.Design a se+uential circuit /hich /ill output 0&1 for the input se+uence that ends in
either '1' or 1''1$ other/ise 0&'.
1.Define a function to multipl, t/o *-bit numbers a and b. 2he output is an )-bit value.
Invo3e the function b, using stimulus and chec3 results.
).cloc3 -4 + & - for d & 15b'$ cloc3 -4 +& (
other/ise
cloc3 -4 +bar & * for d & 15b'$ cloc3 -4+bar & 1
other/ise
#ll other dela,s are - units.
6.Design a divide-b,-1* ripple up counter.
1'.Design a circuit using the behavioral modeling to describe the follo/ing table
I7p 8-state 9-state o7p
: 9:;:9E 9:;:9E '
1 9:;:9E :9E;:9E '
' :9E;:9E 9:;:9E '
1 :9E;:9E 2<:;:9E '
' 2<:;:9E 9:;:9E '
1 2<:;:9E 2=.EE;:9E 1
' 2=.EE;:9E 9:;:9E '
1 2=.EE;:9E 2=.EE;:9E 1
R()) #(: F*($ 1+,111+1. %( 1+,111+-/
1. Implement the follo/ing Boolean function
!"#$B$C$D$E%& >"'$1$*$-$1($11$21$2-$26% using multiplexer.
2. Design a circuit for )*21 to )*-2-1 code conversion.
3. Design a *?1( decoder using t/o 3?) decoder.
*. Design a *-bit s,nchronous binar, counter.
-. Design a combinational circuit that has * inputs "#$ B$ C$ D%$ /hich represent a BCD
digit. 2he circuit has t/o groups of *- outputs @ A$2$B$C and <$D$E$F. Each group
represents a decimal number /hich is five times the input number. !or example$ if
#BCD&'111 the outputs are ''11 '1'1. #ssume that the invalid BCD digits do not occur
as inputs.
(. # full subtractor has three 1- bit inputs x,y$ and z "previous borro/% and t/o 1- bit
output D"difference% and b"borro/%.2he logic e+uation for D and B are as follo/s
D& x.y.z+x.y.z+x.y.z+x.y.z
B& x.y+x.z+y.z
<rite the full Cerilog description for the full subtractor module.
1. Design a negative edge-triggered D-flip flop /ith as,nchronous clear "D;!! clears
/henever clear goes high. It does not /ait for next negative edge%.
). Consider the negative edge triggered /ith the as,nchronous reset D-flipflop. <rite the
Cerilog description for the module D;!!. Describe the dela, path $ using parallel
connection.
6. Define a positive edge triggered D-flipflop /ith clear as a BD8. Aignal clear is a active
lo/. Bse shorthand notation /herever possible.
1'. Design the decoder circuit using s/itch level modeling.
R()) #(: F*($ 1+,111+-5 %( 1+,111+.,
1.Design a circuit for gra, to binar, code conversion.
2.Design a --32 line decoder using four 3-) line decoders /ith enable and one 2-* line
decoder.
3.# se+uential circuit has one input and one output. 2he state diagram is sho/n . Design
the circuit.
*.Design a *-bit BCD ripple counter.
-.Design a se+uential circuit /hich gives the output as 1 /hen the number of 1Gs is odd
and it has received at least 2 consecutive 'Gs.
(.Design a 1-bit full adder using basic primitives.
1.Design a negative edge triggered $ as,nchronous reset D flip flop .#ssume that a six-
dela, specification is to be specified for all path dela,s. #ll path dela,s are e+ual. In the
specif, bloc3$ define parameters t;'1&*$t;1'&-$t;'0&1$t;01&2$t;10&3$t;0'&).<rite
dela, specification using full connections.
).!or a given D flip flop$add timing chec3s for the D-flip flop in the specif, bloc3 as
follo/s
a.2he minimum setup time for d /ith respect to cloc3 is ).
b.2he minimum hold time for d /ith respect to cloc3 is *.
c.2he reset signal is active high. 2he minimum /idth of a reset pulse is *2.
6. Implement the Boolean function
!"a$b$c$d$e%&sigma"'$2$($)$1'$11$12$13$1*$1($1)$16$26$3'%Hd"*$6$21%
Bsing BD8.
1'. Design a divide b, ( ripple do/n counter.
R()) #(: F*($ 1+,111+.0 %( 1+,111+/1
1. # maIorit, logic function is a boolean function that is e+ual to 1 if the maIorit, of the
variables are 1. 2he function is ' other/ise. <rite an =DJ user-defined primitive for
a 3-bit maIorit, function.
2. Design a code converter that converts a decimal digit from the )$*$-2$-1 code to BCD.
3. <rite an =DJ behavioral description of a *-bit comparator /ith a (-bit output. Bit -
is for e+ual$ bit * for une+ual$ bit 3 for greater than$ bit 2 for less than$ bit 1 for greater
than or e+ual$ bit ' for less than or e+ual.
*. Design a Iohnson counter.
-. Design a circuit /hich /ill add a *-bit binar, number to a --bit binar, number. Bse
five full adders.
(. Design a se+uence detector that detects an, input se+uence ending in 1'1 and
produces an output 0&1. :verlapping is permitted.
1. Design a negative edge triggered D-filpflop /ith s,nchronous clear$ active high. Bse
behavioral statements onl,.
). Design a traffic signal controller using if and else statements.
6. using nmos and pmos implement a xor gate.
1'. <rite a program that displa,s the time /henever a ' to 1 transition occurs on an input
cloc3.
R()) #(: F*($ 1+,111+/2 %( 1+,111+,+
1.Design a circuit for BCD to seven segment decoder
2.Design a * input priorit, encoder using BD8
3.<rite an =DJ behavioral description of the KL flipflop using if-else statement based on
the value of the present state."=intConsider the characteristic e+uation /hen M&' or
M&1%
*.Implement a serial adder circuit.
-.Design a )-bit ring counter.
(.Design a counter /ith the follo/ing repeated binar, se+uence '$1$2$3$*$-$(. Bse KL
flipflops.
1.Design a circuit to convert #lphanumeric character to its corresponding #ACII code.
).Define a tas3 to compute the factorial of a *-bit number. 2he output is a 32-bit value.
2he result is assigned to the output after a dela, of 1' time units. #lso design a circuit for
fibonacci series generation.
6.Design a *-bit bidirectional bus s/itch that has t/o buses$ Bus# and BusB$ on one side
and a single bus$BBA$ on the other side. # 1-bit control signal is used for s/itching.
Bus# and BBA are connected if control&1.BusB and BBA are connected if control&'.
#ppl, stimulus and test the design.
1'.<rite the truth table for the boolean function E&"#NB%O"CPD%. Define a BD8 that
implements this Boolean function. #ssume that the inputs /ill never ta3e the value x.
R()) #(: F*($ 1+,111+,1 %( 1+,111+0-
1% Design a *-bit bcd adder
2% Design a *-bit 2Gs complement combinational circuit
3% Design a combinational circuit that generates the 6Gs complement of a bcd digit
*% Design a se+uence detector to detect 3 or more consecutive 1Gs
-% # se+uential circuit has 3 flip-flops$ 1 input and 1 output. Bse d flip-flops and design
the circuit.
(% Design a *-bit up do/n s,nchronous counter
1% <rite a module to convert a positive integer to roman numeral
)% Design a *-bit parallel shift register
6% Design a 2 to 1 multiplexer using bufif' and bufif1 gates
1'% Design a KL counter that goes through the states
1$*$)$3$6$2$1'$1$11$'$1$*Q.
R()) #(: F*($ 1+,111+0. %( 1+,111+1/
1% Design an excess-3-to-binar, decoder using the unused combinations of the code as
donGt care conditions.
2% Implement a full adder /ith t/o * D 1 multiplexers.
3% Design a se+uential circuit /ith t/o K L flip-flops # and B and t/o inputs E and x. If
E & '$ the circuit remains in the same state regardless of the value of x. <hen E & 1 and x
& 1$ the circuit goes through the state transitions from '' to '1 to 1' to 11 bac3 to ''$
and repeats. <hen E & 1 and x & '$ the circuit goes through the state transitions from ''
to 11 to 1' to '1 and bac3 to '' $ and repeats.
*% Design an as,nchronous se+uential circuits /ith t/o inputs$ x1 and x2$ and one output$
0. Initiall,$ both inputs and output are e+ual to '. <hen x1 or x2 becomes 1$ 0 becomes
1. <hen the second input also becomes 1$ the output changes to '. 2he output sta, sat '
until the circuit goes bac3 to the initial state.
-% Design a - bit s,nchronous Binar, counter using 2 flip flop.
(% <rite the Cerilog description for the .A latch. Include dela,s of 1 unit /hen
instantiating the #(* gates. <rite the stimulus module for the .A latch$ using the
follo/ing table"page 9o )( Ex *%$ and verif, the outputs.
1%# synchronous counter can be designed b, using master slave JK flipflops. Design a
*- bit s,nchronous counter. Circuit diagrams for the s,nchronous counter and the KL
flipflop are given in figure "page 9o 111$ Ex 3%. 2he clear signal is active lo/. Data gets
latched on the positive edge of the cloc3 and the output of the flipflop appears on the
negative edge of cloc3. Counting is disabled /hen count_enable signal is lo/. <rite the
dataflo/ description for the s,nchronous counter. <rite a stimulus file that exercises
clear and count_enable. Displa, the output count MR3'S.
)% Tiven a memor, si0e (* /ords$ /ith ) bits per /ord$ /rite verilog code to s/ap the
contents of memor, in reverse order$ that is$ transfer /ord at ' to /ord at (3$ /ord 1 to
/ord (2 and so on.
6% <rite a dataflo/ model for the 6 @ bit parit, generator circuit.

1'% Design a circuit that /ill give output 1 an,time a letter /ithin the string UDigital
A,stem DesignV$ appears at the input in #ACII code.
R()) #(: F*($ 1+,111+15 %( 1+,111+2,
1.Design a * bit b, 3 bit Binar, multiplier.
2.Dra/ a se+uential circuit /ith t/o D flip flops and one input x;in.
a% <hen x;in is '$ the state of the circuit remains the same. <hen x;in is 1$ the circuit
goes through the state transitions '' to '1$ to 11$ to 1'$ bac3 to '' and repeats.
b% <hen x;in is '$ the state of the circuit remains the same. <hen x;in is 1$ the circuit
goes through the state transitions from '' to 11$ to '1$ to 1'$ bac3 to '' and repeats.
3. Design a gra, code converter to drive a seven segment indicator. 2he four inputs to the
converter circuit "#$ B$ C$ D% represent a decimal digit coded using the Tra, code.
#ssume that onl, i7p combinations representing the digits ' to 6 can occur as inputs$ so
that the unused combinations are don5t care terms.
*. Bse the /ait statement to design a level sensitive latch that ta3es cloc3 and d as inputs
and + as output$ +&d /henever cloc3&1.
-. Design a ) bit counter b, using forever loop$ named bloc3 and disabling of named
bloc3. 2he counter starts counting at count & - and finishes at count & (1. 2he count is
incremented at positive edge of cloc3. 2he cloc3 has a time period of 1'. 2he counter
counts through the loop onl, once before it gets disabled.
(. Design a tas3 to compute even parit, of a 1(-bit number. 2he result is a 1-bit value that
is assigned to the output after three positive edges of cloc3. "Bse a repeat statement%
1.Design a maIorit, circuit. 2he input is a 12 bit vector. If the number of 15s exceeds the
no. of '5s$ the output is set to 1. 2he i7p data is chec3ed onl, /hen Data;read, is a 1.
). Design a )-bit Ker3, ring counter.
6. Design a KL counter that must go through states '$3$($'...if a control line is high and
'$2$*$($'...if the control line is lo/.
1'. 2/o levels W and 9 enter a logic circuit. Design an as,nchronous circuit such
that if 9 goes high before W$ the output /ill be #9D of W and 9. =o/ever if W
goes high before 9 the o7p must be '.
R()) #(: F*($ 1+,111+20 %( 1+,111+1+0
1. Design a * bit adder subtractor circuit.
2. # se+uential circuit has t/o KL flip flops # and B and one input x. 2he circuit is
defined b, the follo/ing flip-flop input e+uations
K
a
&x L
a
&BG
K
b
&x L
b
&#
3. Create a design that uses the full adder example above. Bse a conditional
compilation "Xifdef%. Compile the fulladd* /ith defparam statements if the text
macro D8#.#W is defined b, the Xdefine statementY other/ise$ compile the
fulladd* /ith module instance parameter values.
*. i.% Define a function to calculate the factorial of a * @ bit number. 2he output is a
32 @ bit value. Invo3e the function b, using stimulus and chec3 results.
ii.% 2o chec3 /hether a number is a !ibonacci number.
-. Describe a generic 9-bit counter /ith as,nchronous negative level reset. Instantiate
this generic counter as a --bit counter. Cerif, this - @ bit counter using a test
bench.
(. <rite a program to find the si0e of the largest gap bet/een t/o successive 1s in a
1( @ bit /ord.
1. Design a circuit that can shift a * @ bit vector /&/
3
/
2
/
1
/
'
one bit position to the
right /hen a control signal shift is e+ual to 1. Jet the outputs of the circuit be a *
@ bit vector E&,
3
,
2
,
1
,
'
and a signal L$ such that if shift & 1 then ,
3
&'$ ,
2
&/
3
$
,
1
&/
2
$ ,
'
&/
1
and L&/
'
. If shift&'$ then E&/ and L&'.
). <rite and verif, a verilog model that /ill assert its output if a * @ bit input /ord is
not a valid binar, coded decimal code.
6. Design a KL Counter for states '$ )$ 6$ -$ 1'$ 12$ 1*$ 1-$ '$ . .
1'. Design a * @ bit register /ith parallel load.