Introduction to Hardware Description Language

Classical design methods relied on schematics and manual methods to design a circuit,
but today computer-based languages are widely used to design circuits of enormous size and
complexity. There are several reasons for this shift in practice. No team of engineers can
correctly design and manage, by manual methods, the details of state-of-the-art integrated
circuits (ICs) containing several million gates, but using hardware description languages (HDLs)
designers easily manage the complexity of large designs. Even small designs rely on language-
based descriptions, because designers have to quickly produce correct designs targeted for an
ever-shrinking window of opportunity in the marketplace.
Language-based designs are portable and independent of technology, allowing design
teams to modify and re-use designs to keep pace with improvements in technology. As physical
dimensions of devices shrink, denser circuits with better performance can be synthesized from an
original HDL-based model. HDLs are a convenient medium for integrating intellectual property
(IP) from a variety of sources with a proprietary design. By relying on a common design
language, models can be integrated for testing and synthesized separately or together, with a net
reduction in time for the design cycle. Some simulators also support mixed descriptions based on
multiple languages.
The most significant gain that results from the use of an HDL is that a working circuit
can be synthesized automatically from a language-based description, bypassing the laborious
steps that characterize manual design methods (e.g., logic minimization with Karnaugh maps).
HDL-based synthesis is now the dominant design paradigm used by industry.
Today, designers build a software prototype/model of the design, verify its
functionality, and then use a synthesis tool to automatically optimize the circuit and create a
netlist in a physical technology.
HDLs and synthesis tools focus an engineer's attention on functionality rather than on
individual transistors or gates; they synthesize a circuit that will realize the desired functionality,
and satisfy area and/or performance constraints. Moreover, alternative architectures can be
generated from a single HDL model and evaluated quickly to perform design tradeoffs.
Functional models are also referred to as behavioral models.
HDLs serve as a platform for several tools: design entry, design verification, test
generation, fault analysis and simulation, timing analysis and/or verification, synthesis, and
automatic generation of schematics. This breadth of use improves the efficiency of the design
flow by eliminating translations of design descriptions as the design moves through the tool
chain.
Two languages enjoy widespread industry support: Verilog and VHDL. Both languages
are IEEE (Institute of Electrical and Electronics Engineers) standards; both are supported by
synthesis tools for ASICs (application-specific integrated circuits) and FPGAs (field-
programmable gate arrays). Languages for analog circuit design, such as Spice, play an
important role in verifying critical timing paths of a circuit, but these languages impose a
prohibitive computational burden on large designs, cannot support abstract styles of design, and
become impractical when used on a large scale. Hybrid languages (e.g., Verilog-A) are used in
designing mixed-signal circuits, which have both digital and analog circuitry. System-level
design languages, such as SystemC and Superlog, are now emerging to support a higher level of
design abstraction than can be supported by Verilog or VHDL.

What is the main difference between HDL and other software languages:

The main difference with the traditional programming languages is HDLs representation
of extensive parallel operations whereas traditional ones represents mostly serial
operations.

Importance of HDLs:
HDLs have many advantages compared to traditional schematic-based design
Designs can be described at a very abstract level by use of HDLs. Designers can write
their RTL description without choosing a specific fabrication technology. Logic synthesis
tools can automatically convert the design to any fabrication technology. If a new
technology emerges, designers do not need to redesign their circuit. They simply input
the RTL description to the logic synthesis tool and create a new gate-level netlist, using
the new fabrication technology. The logic synthesis tool will optimize the circuit in area
and timing for the new technology.
By describing designs in HDLs, functional verification of the design can be done early in
the design cycle. Since designers work at the RTL level, they can optimize and modify
the RTL description until it meets the desired functionality. Most design bugs are
eliminated at this point. This cuts down design cycle time significantly because the
probability of hitting a functional bug at a later time in the gate-level netlist or physical
layout is minimized.
Designing with HDLs is analogous to computer programming. A textual description with
comments is an easier way to develop and debug circuits. This also provides a concise
representation of the design, compared to gate-level schematics. Gate-level schematics
are almost incomprehensible for very complex designs.
Importance of Computer-Aided Digital Design:
The earliest digital circuits were designed with vacuum tubes and transistors. Integrated
circuits were then invented where logic gates were placed on a single chip. The first integrated
circuit (IC) chips were SSI (Small Scale Integration) chips where the gate count was very small.
As technologies became sophisticated, designers were able to place circuits with hundreds of
gates on a chip. These chips were called MSI (Medium Scale Integration) chips. With the advent
of LSI (Large Scale Integration), designers could put thousands of gates on a single chip. At this
point, design processes started getting very complicated, and designers felt the need to automate
these processes. Electronic Design Automation (EDA) techniques began to evolve. Chip
designers began to use circuit and logic simulation techniques to verify the functionality of
building blocks of the order of about 100 transistors. The circuits were still tested on the
breadboard, and the layout was done on paper or by hand on a graphic computer terminal.
With the advent of VLSI (Very Large Scale Integration) technology, designers could
design single chips with more than 100,000 transistors. Because of the complexity of these
circuits, it was not possible to verify these circuits on a breadboard. Computer-aided techniques
became critical for verification and design of VLSI digital circuits. Computer programs to do
automatic placement and routing of circuit layouts also became popular. The designers were now
building gate-level digital circuits manually on graphic terminals. They would build small
building blocks and then derive higher-level blocks from them. This process would continue
until they had built the top-level block. Logic simulators came into existence to verify the
functionality of these circuits before they were fabricated on chip.
What is gate-level netlist:
A gate-level netlist is a description of the circuit in terms of gates and connections between them.
Logic synthesis tools convert the RTL description to a gate-level netlist.
Problems associated with conventional approach to digital design:
Digital ICs of SSI and MSI types have become universally standardized and have been
accepted for use. Whenever a designer has to realize a digital function, he uses a standard set of
ICs along with a minimal set of additional discrete circuitry.
Consider a simple example of realizing a function as Q n+1 = Q n + (A.B)
Here Qn, A, and B are Boolean variables, with Q n being the value of Q at the nth time step. Here
A.B signifies the logical AND of A and B; the + symbol signifies the logical OR of the logic
variables on either side. A circuit to realize the function is shown in Figure 1.1. The circuit can
be realized in terms of two ICs an A-O-I gate and a flip-flop. It can be directly wired up, tested,
and used.


Fig. 1.1 A simple digital circuit
The accepted approach to digital design here is a mix of the top-down and bottom-up
approaches as follows:
1. Decide the requirements at the system level and translate them to circuit requirements.
2. Identify the major functional blocks required like timer, DMA unit, register file etc., say
as in the design of a processor.


3. Whenever a function can be realized using a standard IC, use the same for example
programmable counter, mux, demux, etc.
4. Whenever the above is not possible, form the circuit to carry out the block functions
using standard SSI for example gates, flip-flops, etc.
5. Use additional components like transistor, diode, resistor, capacitor, etc., wherever
essential.
Once the above steps are gone through, a paper design is ready. Starting with the paper
design, one has to do a circuit layout. The physical location of all the components is tentatively
decided; they are interconnected and the circuit-on paper is made ready. Once a paper design is
done, a layout is carried out and a net-list prepared. Based on this, the PCB is fabricated and
populated and all the populated cards tested and debugged. The procedure is shown as a process
flowchart in Figure 1.2.



Fig.1.2 Sequence of steps in conventional electronic circuit design.





At the debugging stage one may encounter three types of problems:
1. Functional mismatch: The realized and expected functions are different. One may have
to go through the relevant functional block carefully and locate any error logically.
Finally the necessary correction has to be carried out in hardware.
2. Timing mismatch: The problem can manifest in different forms. One possibility is due to
the signal going through different propagation delays in two paths and arriving at a point
with a timing mismatch. This can cause faulty operation. Another possibility is a race
condition in a circuit involving asynchronous feedback. This kind of problem may call
for elaborate debugging. The preferred practice is to do debugging at smaller module
stages and ensuring that feedback through larger loops is avoided: It becomes essential to
check for the existence of long asynchronous loops.
3. Overload: Some signals may be overloaded to such an extent that the signal transition
may be unduly delayed or even suppressed. The problem manifests as reflections and
erratic behavior in some cases (The signal has to be suitably buffered here.). In fact,
overload on a signal can lead to timing mismatches.
The above have to be carried out after completion of the prototype PCB
manufacturing;it involves cost, time, and also a redesigning process to develop a bug free
design.
Logic simulation and synthesis:
There are two applications of HDL processing: Simulation and Synthesis
Simulation Simulation is used to verify the functionality of the circuit
A) Functional Simulation: study of circuits operation independent of timing parameters and
gate delays.
B) Timing Simulation: study including estimated delays; verify setup, hold and other timing
requirements of devices like flip flops are met.
Synthesis :
One of the foremost in back end steps where by synthesizing is nothing but converting VHDL or
VERILOG description to a set of primitives(equations as in CPLD) or components(as in
FPGA'S)to fit into the target technology. Basically the synthesis tools convert the design
description into equations or components
Basic Concepts:
Verilog HDL is a case-sensitive language. All keywords are in lowercase.
Verilog contains a stream of tokens. Tokens can be
1. comments,
2. delimiters,
3. numbers,
4. strings,
5. identifiers,
6. Keywords.

1. Comments
Comments can be inserted in the code for readability and documentation.
There are two ways to write comments.
A one-line comment starts with "//". Verilog skips from that point to the end of line.
A multiple-line comment starts with "/*" and ends with "*/".
Multiple-line comments cannot be nested.
However, one-line comments can be embedded in multiple-line comments.
a = b && c; // This is a one-line comment

/* This is a multiple line
comment */

/* This is /* an illegal */ comment */

/* This is //a legal comment */


2. Number Specification
There are two types of number specification in Verilog: sized and unsized. Sized numbers
Sized numbers are represented as <size> '<base format> <number>.
<size> is written only in decimal and specifies the number of bits in the number.
Legal base formats are decimal ('d or 'D), hexadecimal ('h or 'H), binary ('b or 'B) and octal ('o
or 'O). The number is specified as consecutive digits from 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b, c, d, e, f.
Only a subset of these digits is legal for a particular base. Uppercase letters are legal for number
specification.
4'b1111 // This is a 4-bit binary number
12'habc // This is a 12-bit hexadecimal number
16'd255 // This is a 16-bit decimal number.
Unsized numbers
Numbers that are specified without a <base format> specification are decimal numbers by
default. Numbers that are written without a <size> specifications have a default number of bits
that is simulator- and machine-specific (must be at least 32).
23456 // This is a 32-bit decimal number by default
'hc3 // This is a 32-bit hexadecimal number
'o21 // This is a 32-bit octal number

X or Z values
Verilog has two symbols for unknown and high impedance values. These values are very
important for modeling real circuits. An unknown value is denoted by an x. A high impedance
value is denoted by z.
12'h13x // This is a 12-bit hex number; 4 least significant bits unknown
6'hx // This is a 6-bit hex number
32'bz // This is a 32-bit high impedance number
An x or z sets four bits for a number in the hexadecimal base, three bits for a number in the octal
base, and one bit for a number in the binary base. If the most significant bit of a number is 0, x,
or z, the number is automatically extended to fill the most significant bits, respectively, with 0, x,
or z. This makes it easy to assign x or z to whole vector. If the most significant digit is 1, then it
is also zero extended.
Negative numbers
Negative numbers can be specified by putting a minus sign before the size for a constant number.
Size constants are always positive. It is illegal to have a minus sign between <base format>
and <number>. An optional signed specifier can be added for signed arithmetic.

-6'd3 // 8-bit negative number stored as 2's complement of 3
-6'sd3 // Used for performing signed integer math
4'd-2 // Illegal specification
Underscore characters and question marks
An underscore character "_" is allowed anywhere in a number except the first character.
Underscore characters are allowed only to improve readability of numbers and are ignored by
Verilog.
A question mark "?" is the Verilog HDL alternative for z in the context of numbers. The ? is
used to enhance readability in the casex and casez statements, where the high impedance value is
a don't care condition. (Note that ? has a different meaning in the context of user-defined
primitives, , User-Defined Primitives.)
12'b1111_0000_1010 // Use of underline characters for readability
4'b10?? // Equivalent of a 4'b10zz


Whitespace
Blank spaces (\b), tabs (\t) and newlines (\n) comprise the whitespace.
Whitespace is ignored by Verilog except when it separates tokens.
Whitespace is not ignored in strings.
Identifiers and Keywords
Keywords are special identifiers reserved to define the language constructs. Keywords are in
lowercase.
Identifiers are names given to objects so that they can be referenced in the design. Identifiers are
made up of alphanumeric characters, the underscore ( _ ), or the dollar sign ( $ ).
Identifiers are case sensitive.
Identifiers start with an alphabetic character or an underscore.
They cannot start with a digit or a $ sign (The $ sign as the first character is reserved for system
tasks, which are explained later in the book).
reg value; // reg is a keyword; value is an identifier
input clk; // input is a keyword, clk is an identifier

Escaped Identifiers
Escaped identifiers begin with the backslash ( \ ) character and end with whitespace (space, tab,
or newline).
All characters between backslash and whitespace are processed literally.
Any printable ASCII character can be included in escaped identifiers.
Neither the backslash nor the terminating whitespace is considered to be a part of the identifier.
\a+b-c
\**my_name**
Verilog supports four values:
Value Level Condition in Hardware Circuits
0 Logic zero, false condition
1 Logic one, true condition
x Unknown logic value
z High impedance, floating state
Data Types:
The data handled in Verilog fall into two categories:
1. Net data type
2. Register data type (according to 1995 standardization), but according to 2001 language
standardization it is Variable data type.
Nets (sometimes called wires) are the most common data object in Verilog. Nets are used to
interconnect modules and primitives

Net types are listed in the following Table 1c-A



Table 1c-A
wire is the default net type
wire and tri are the same type of net. The reason for having two names for this type of net is that
to distinguish designs those nets that are expected to tri-state from those that do not.

wand and triand are wires that represent wired AND logic. Wired AND logic is similar to open-
collector TTL logic. If any driver on the net is 0, the resulting value is 0. Verilog does not
distinguish between wand and triand. The different names are only for use in documenting your
model.

Wired OR logic is represented with the wor and trior net types. With these net types, if any
driver is a 1, the result is 1. As with the previous net types, wor and trior are equivalent.

If nothing is driving a wire in TTL logic, the inputs default to 1. You can use the tril net type to
model this situation. If nothing is driving a net of type tril, the default value is 1. As with tril, if
nothing is driving a net of type tri0, the value is 0.

Use the supply1 and supply0 net types to model power supply nets. These nets are always 1 or 0
with a strength of supply. Even if you drive something onto these nets, they always retain their
distinct values.
The trireg net type is used in switch-level modeling for storage nodes. The trireg net has a
capacitive size associated with it. Because trireg is an abstraction of a storage node, the
capacitors never decay.

In Verilog, a wire can be 1 bit wide or much wider. A wire that is more than 1 bit wide is called a
vector in Verilog.

Register data type or Variable data type:
Registers represent data storage elements. Registers retain value until another value is placed
onto them. Do not confuse the term registers in Verilog with hardware registers built from edge-
triggered flipflops in real circuits. In Verilog, the term register merely means a variable that can
hold a value. Unlike a net, a register does not need a driver. Verilog registers do not need a clock
as hardware registers do. Values of registers can be changed anytime in a simulation by
assigning a new value to the register.
1. reg
2. time,
3. integer,
4. real,
5. realtime

reg data type:
Regs are used for modeling in procedural blocks.
The reg data type does not always imply modeling of a flip-flop, latch, or other form of register.
The reg data type can also be used to model combinatorial logic.
A register can be 1 bit wide or declared a vector, just as with nets.

Example 1c-1:
reg a, b, c; // Three 1-bit registers.
reg [8:15] d, e, f; // Three 8-bit registers.

NOTE:
Part of a reg can be referenced or assigned to by using a bit- or part-select notation.
Remember that the leftmost bit is the most significant, regardless of how the range is declared.
When you select a part or slice of a register, be sure the range of the part matches the range
direction (ascending or descending) of the original register.
Also, if you select a range that is not within the original register, the result will be x, and is not an
error.
Example 1c-2: Selecting Bits and Parts of a Reg
e[15] // Refers to the least significant bit of e.
d[8:ll] // Refers to the four most significant bits of d.
Initial Value of Regs
The initial value of a reg or array of regs is 'bx (unknown).
IEEE1364-2001 defines a method to initialize a reg as part of the declaration.
Example 1c-3 shows the declaration of five regs, a, b, c, d, and e:
Regs a and c are not given initial values and default to unknown.
As with the other IEEE1364-2001 changes tool support for these language features may not be
immediate or complete.
The standard does not specify an order of evaluation of these initial values versus an initial block
with a procedural assignment to the same reg.

Example 1c-3: Reg Declaration with Initialization

reg [7:0] a; // initial value will be 8'bx;
reg [7:0] b = 8'd3; // initial value will be 3
reg [3:0] c, d=3, e=4;

Integers and Reals:
Integers in Verilog are usually 32 bits wide. Strictly speaking, the number of bits in an integer is
machine-dependent.
Verilog was created when 36-bit machines were common, so a 36-bit machine would have an
integer of 36 bits.
Today most machines work with 32-bit integers. So the integers are 32 bits wide.
A real holds a floating-point number in IEEE format.
Integers are declared with the integer keyword
Reals are declared with the real keyword.

Example 1c-4: Declaring Integers and Reals
integer i, j, k;
real x, y;

Integer:
An integer is a general purpose register data type used for manipulating quantities.
Integers are declared by the keyword integer.
Although it is possible to use reg as a general-purpose variable, it is more convenient to declare
an integer variable for purposes such as counting.
The default width for an integer is the host-machine word size, which is implementation-specific
but is at least 32 bits.
Registers declared as data type reg store values as unsigned quantities, whereas integers store
values as signed quantities.
integer counter; // general purpose variable used as a counter.
initial
counter = -1; // A negative one is stored in the counter
Real:
Real number constants and real register data types are declared with the keyword real.
They can be specified in decimal notation
e.g., 3.14
or in scientific notation
e.g., 3e6, which is 3 x 10
6
.
Real numbers cannot have a range declaration, and their default value is 0.
When a real value is assigned to an integer, the real number is rounded off to the nearest integer.
real delta; // Define a real variable called delta
initial
begin
delta = 4e10; // delta is assigned in scientific notation
delta = 2.13; // delta is assigned a value 2.13
end
integer i; // Define an integer i
initial
i = delta; // i gets the value 2 (rounded value of 2.13)

Time and Realtime:
Verilog uses the timekeyword to represent the current simulation time.
time is double the size of an integer (usually 64 bits) and is unsigned.
If your model uses a timescale you can use realtime to store the simulation time and time units.
You can declare variables of type timeor realtimein your models for timing checks, or in any
other operations you need to do with time.

Example 1c-5 : Declaring Variables of Type time
time t1, t2;
realtime rt1, rt2;

MODULES
Any Verilog program begins with a keyword called a module. A module is the name given
to any system considering it as a black box with input and output terminals as shown in Figure
1c-1. The terminals of the module are referred to as ports. The ports attached to a module can
be of three types:
input ports through which one gets entry into the module; they signify the input signal
terminals of the module.
output ports through which one exits the module; these signify the output signal terminals of
the module.
inout ports: These represent ports through which one gets entry into the module or exits the
module; These are terminals through which signals are input to the module sometimes; at
some other times signals are output from the module through these.



Figure 1c-1
Whether a module has any of the above ports and how many of each type are present depend
solely on the functional nature of the module.
Thus one module may not have any port at all; another may have only input ports, while a third
may have only output ports, and so on.

GATE DELAYS
Verilog has the facility to account for different types of propagation delays of circuit elements.
Any connection can cause a delay due to the distributed nature of its resistance and capacitance.
Due to the manufacturing tolerances, these can vary over a range in any given circuit.
Similar delays are present in gates too. These manifest as propagation delays in the 0 to 1
transitions and 1 to 0 transitions from input to the output. Such propagation delays can differ for
the two types of transitions.
A variety of such delays can be accommodated in Verilog. Sometimes manufacturers adjust
input and output impedances of circuit elements to specific levels and exploit them to reduce
interface hardware. These too can be accommodated in Verilog design descriptions.
There are three types of delays from the inputs to the output of a primitive gate.
1. Rise Delay
2. Fall Delay
3. Turn-off Delay
Rise delay
The rise delay is associated with a gate output transition to a 1 from another value.

Fall delay
The fall delay is associated with a gate output transition to a 0 from another value.

Turn-off delay
The turn-off delay is associated with a gate output transition to the high impedance value (z)
from another value.
If the value changes to x, the minimum of the three delays is considered.
NOTE:
Three types of delay specifications are allowed.
If only one delay is specified, this value is used for all transitions.
If two delays are specified, they refer to the rise and fall delay values.
The turn-off delay is the minimum of the two delays.
If all three delays are specified, they refer to rise, fall, and turn-off delay values.
If no delays are specified, the default value is zero.


Example 1d-1 Types of Delay Specification
// Delay of delay_time for all transitions

and # (delay_time) a1 (out, i1, i2);

// Rise and Fall Delay Specification.

and # (rise_val, fall_val) a2 (out, i1, i2);

// Rise, Fall, and Turn-off Delay Specification

bufif0 # (rise_val, fall_val, turnoff_val) b1 (out, in, control);
Examples of delay specification are shown below.
and #(5) a1(out, i1, i2); //Delay of 5 for all transitions; a1 is instantiation name
and #(4,6) a2(out, i1, i2); // Rise = 4, Fall = 6 ; a2 is instantiation name
bufif0 # (3, 4, 5) b1 (out, in, control); // Rise = 3, Fall = 4, Turn-off = 5; b1 is instantiation name

Normally the delay time of any IC varies over a range for ICs from different production batches
(as well as in any one batch).
It is customary for manufacturers to specify delays and their range in the following manner:
Max delay: The maximum value of the delay in a batch; that is, the delay encountered in
practice is guaranteed to be less than this in the worst case.
Min. delay: Minimum value of delay in a batch; that is, the specified signal is guaranteed to
be available only after a minimum of time specified.
Typ. delay: Typical or representative value of the delay.

Min, Max, and Typical Delay Values:
Verilog provides an additional level of control for each type of delay mentioned above.
For each type of delayrise, fall, and turn-offthree values, min, typ, and max, can be
specified.
Any one value can be chosen at the start of the simulation.
Min value
The min value is the minimum delay value that the designer expects the gate to have.
Typ val
The typ value is the typical delay value that the designer expects the gate to have.
Max value
The max value is the maximum delay value that the designer expects the gate to have.
NOTE:
Min, typ, or max values can be chosen at Verilog run time.
This allows the designers the flexibility of building three delay values for each transition into
their design.
The designer can experiment with delay values without modifying the design.
Note that the colon that separates the numbers signifies that the timings specified are the
minimum, typical, and maximum values.
At the time of simulation, one can specify the simulation to be carried out with any of these three
delay values. If the same is not specified, the simulation is carried out with the typical delay
value.
The group of minimum, typical, and maximum delay values for the propagation delays can be
specified separately for any gate primitive.

Thus an AND gate primitive can be specified as
and #(1:2:3, 2:4:6) g2(b0, b1, b2);
Here for the 0 to 1 transition of the output (rise time) the gate has a minimum
delay value of 1 ns, a typical value of 2 ns, and a maximum value of 3 ns.
Similarly, for the 1 to 0 transition (fall time) the gate has a minimum delay value
of 2 ns, a typical delay value of 4 ns, and a maximum delay value of 6 ns.
SYSTEM TASKS AND COMPILER DIRECTIVES
System Tasks
Verilog has a number of System Tasks and Functions . They are for taking
1. output from simulation,
2. control simulation,
3. debugging design modules,
4. testing modules for specifications, etc.
A $ sign preceding a word or a word group signifies a system task or a system function.
All system tasks or a system function appear in the form $<keyword>.
Operations such as displaying on the screen, monitoring values of nets, stopping, and finishing
are done by system tasks.
Displaying information
$display is the main system task for displaying values of variables or strings or expressions. This
is one of the most useful tasks in Verilog.
Usage: $display(p1, p2, p3,....., pn);
p1, p2, p3,..., pn can be quoted strings or variables or expressions.
Monitoring information
Verilog provides a mechanism to monitor a signal when its value changes. This facility is
provided by the $monitor task.
Usage: $monitor(p1,p2,p3,....,pn);
The parameters p1, p2... pn can be variables, signal names, or quoted strings.
A format similar to the $display task is used in the $monitor task.
$monitor continuously monitors the values of the variables or signals specified in the parameter
list and displays all parameters in the list whenever the value of any one variable or signal
changes.
Unlike $display, $monitor needs to be invoked only once.
Only one monitoring list can be active at a time. If there is more than one $monitor statement in
your simulation, the last $monitor statement will be the active statement. The earlier $monitor
statements will be overridden.
$stop and $finish Tasks
The $stop task suspends simulation. The compiled design remains active; simulation can be
resumed through commands available in the simulator.
In contrast $finish stops simulation, closes the simulation environment, and reverts to the
operating system.
Compiler Directives
A number of compiler directives are available in Verilog. They allow for macros, inclusion of
files, and timescale-related parameters for simulation.
All compiler directives are preceded by the ` (accent grave or backquote) character.
All compiler directives are defined by using the `<keyword> construct.
`define
The `define directive is used to define text macros in Verilog
`define Directive
//define a text macro that defines default word size
`define WORD_SIZE 32 //Used as ` WORD_SIZE in the code
`define S $stop //define an alias. A $stop will be substituted wherever `S appears
`include
The `include directive allows you to include entire contents of a Verilog source file in another
Verilog file during compilation. This directive is typically used to include header files, which
typically contain global or commonly used definitions.
`include Directive
// Include the file header.v, which contains declarations in the
// main verilog file design.v.
'include header.v
...
...
<Verilog code in file design.v>
...
...
`timescale
The `timescale compiler directive allows the time scale to be specified for the design.
`timescale 1 ms/100 s
implies that in the following design all the time values specified are in ms and they have a
precision of 100 s.
Thus
3, 3.0, 3.022 are all interpreted as 3 ms;
3.1, 3.12,3.199 are all interpreted as 3.1 ms; and
0.1, 0.12 are interpreted as 100 s.

`timescale 10 ms/100 s
implies that in the following design all the timescales are specified as multiples of 10 ms with a
precision of 100 s.
Thus
3 and 3.0 are interpreted as 30 ms;
3.022 is interpreted as 30.2 ms;
3.1 is interpreted as 31 ms;
3.12 is interpreted as 31.2 ms;
3.199 is interpreted as 31.9 ms;
0.1 is interpreted as 1 ms and
0.12 is interpreted as 1.2 ms.



Form of specifying timescale: s, ms, us, ns, ps, and fs stand for seconds, milliseconds,
microseconds, picoseconds and femtoseconds, respectively.