Low power and high gain current reuse LNA with modied input matching

and inter-stage inductors

S. Toofan

, A.R. Rahmati, A. Abrishamifar, G. Roientan Lahiji

Electrical Engineering Department, Iran University of Science and Technology, Narmak, Tehran, Iran
a r t i c l e i n f o
Article history:
Received 24 January 2008
Accepted 31 July 2008
Available online 23 September 2008
Keywords:
RF CMOS LNA
Inductive degenerative LNA
Receiver front-end
Current reuse LNA
Inter-stage inductor
Modied architecture
a b s t r a c t
In this paper we present a fully integrated current reuse CMOS LNA (low noise amplier) with modied
input matching circuitry and inductive inter-stage architecture in 0.18mm CMOS technology. To reduce
the large spiral inductors that actually require larger surface area for their fabrication, two parallel
LC circuits are used with two small spiral on-chip inductors. Using cascode conguration equipped by
parallel inter-stage LCs, we achieved lower power consumption with higher power gain. In this
conguration we used two cascoded transistors to have a good output swing suitable for low voltage
technology compared to other current reuse congurations. This conguration provides better input
matching, lower noise gure and more reverse isolation which is vital in LNA design. Complete
analytical simulation of the circuit results in center frequency of 5.5 GHz, with 1.9dB NF, 50 O input
impedance, 1GHz 3dB power bandwidth, 20.5dB power gain (S
21
), high reverse isolation (S
12
)o48dB,
18.5 dB input matching (S
11
) and 21.3dB output matching (S
22
), while dissipating as low power as
2mW at 1.8V power supply.
& 2008 Elsevier Ltd. All rights reserved.
1. Introduction
In the past few years, wireless local area networks (WLAN)
have been deployed all over the world as ofce and home
communication infrastructures, where LNAs are important com-
ponents in these systems [1]. Price and other market require-
ments force RF receivers to be integrated in standard CMOS
technology along with the rest of digital signal processing units [2].
Integrating large amount of circuits for sure requires low power
consumption design techniques; therefore wide attention has
been paid to the low power fully integrated LNA designs.
Besides power consumption, there are many other parameters
of importance that are used as part of the trade-off among the LNA
designs. Some of these parameters are: input impedance match-
ing, noise gure, power gain, stability, linearity and increasing the
frequency of operation [3,4]. In order to increase the frequency of
operation, LNA designers, take advantage of some circuit techni-
ques such as unilateralization and neutralization methods beside
the widely used single-stage cascode topology [5,6].
LNA actually amplies the weak signals coming from the
antenna and duplex lter, and delivers them to the next stage with
minimum amount of added inherent noise. To minimize the
reections from LNA to the antenna and duplex lter, impedance
matching is required [7]. Providing sufcient transconductance
gain with acceptable linearity and power consumption is part of
an LNA design in order to overcome the noise of subsequent
stages. Linearity in LNA is typically measured in terms of IIP3
which is required to be maximized. To impose a suitable trade-
offs among the LNA parameters, we presented a fully integrated
CMOS LNA circuit [8]. In order to decrease the total noise gure
and to increase the sensitivity of receiver, its power gain is
increased by the application of current reuse structure.
Several works have been reported on the current reuse
techniques in LNAs [9,10]. In [9] a current reuse two-stage LNA
topology is proposed, which adopts a series inter-stage resonance
to enhance the gain. But, using a three transistor in cascode form
decreases the output swing which is not suitable for low voltage
technology and introduces additional noise. Ref. [10] reports a
gain controlled differential current reuse LNA for IEEE 802.11a
WLAN application. Despite using a current reuse structure, it has
high power consumption and low power gain compared to other
similar topologies. Furthermore, they use on-chip spiral inductors
that take a large area which is costly and needs to be avoided.
The emphases of this paper are reducing the power consump-
tion and inductors area, improving the power gain of CMOS LNA
while still retaining acceptable noise performance, better input
matching and sufcient linearity. The above improvements have
been achieved by the implication of cascode current reuse
structure with using two parallel LCs instead of inter-stage
inductor and input matching inductor. After discussing the input
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0026-2692/$ - see front matter & 2008 Elsevier Ltd. All rights reserved.
doi:10.1016/j.mejo.2008.07.073

Corresponding author. Tel.: +989125948476; fax: +982177240490.

E-mail address: S_toofan@iust.ac.ir (S. Toofan).
Microelectronics Journal 39 (2008) 15341537
impedance matching techniques, we explain the details of our
design process. The simulation results of the designed LNA and
comparison with other works are presented in detail.
2. Input impedance matching
In Fig. 1 of [3], four distinct methods of matching input
impedances in LNAs were given, which includes adding a resistor
at the input terminal, common gate conguration, a resistive
shunt-series feedback and inductive degeneration common source
LNA. The inductive degeneration technique, depicted in Fig. 1, does
not degrade the ampliers noise performance and it easily
matches the input impedance [3].
From Fig. 1(b), the input impedance of inductive degeneration
CMOS LNA is expressed by [3,11]:
Z
in
R
Lg
R
g
R
nqs

g
m1
L
s
C
gs
sL
g
L
s

1
sC
gs
(1)
where C
gs
is the gatesource capacitance of the transistor. For
matched input impedance, at desired frequency, the real and
imaginary parts of (1) must be equal to R
s
and zero, respectively.
However, the on-chip spiral inductors take large area which is
costly. To alleviate this problem, several ways are presented for
reducing L
g
. One way is to increase the input transistors width W
so as to increase C
gs
. Another way is to connect an additional
capacitor in parallel with gatesource capacitance. Both of these
methods degrade the quality factor of the input stage, which will
in turn degrade LNAs performance. Another method is using a
parallel LC network that is illustrated in Fig. 2.
For ooo
o1
, where o
o1
1=

LC
p
is the resonant frequency of
the parallel LC network, its impedance (Z) can be modeled with a
series RL circuit, then
Z joL
g
R
g
(2)
By a simple calculation we can write [12]:
L
g

L
1 o
2
LC

L
1 o=o
o1

2
(3)
R
g

R
sL
1 o
2
LC
2

R
sL
1 o=o
o1

2
(4)
where for simplicity, the inductor is simply modeled as an ideal
inductor L and a series parasitic resistance R
sL
. Hence, a small
parallel LC circuit can be modeled as a large inductance L
g
[12]. In
this work, we used this method to overcome the use of large
inductors.
3. Designing process
The designed LNA as illustrated in Fig. 3 has cascode current
reuse structure with parallel LC network in inter-stage and input
matching network. The design process can be presented as follows:
The rst step in our design was to calculate the optimumwidth
of the input transistor in order to obtain the best noise perfor-
mance. The input transistor channel width is calculated by [13,14]
W
1
W
optjF
min

3
2oLC
ox
R
s
Q
Lop
(5)
where C
ox
, R
s
, o, Q
Lop
and L are the oxide capacitance, source
resistance, the operating frequency, optimum quality factor of
input circuit, and length of the transistor, respectively; where
Q
Lop
X2.598 [13]. The gate width of the cascode transistor M
2
is
chosen half or similar of the M
1
size. This needs a trade-off in
order to suppress the noise introduced by M
2
and the gain
obtained by load. The value for the total gate to source capacitance
of transistor M
1
, C
gs1
, can be taken as
C
gs1

2
3
W
1
LC
ox
(6)
Transistor M
3
forms a current mirror with M
1
that biases the
whole LNA circuit. In order to minimize the noise and power
consumption, its width must be set to a small fraction of M
1
s. In
this design we assumed W
1
10W
3
.
In order to limit the total power consumption the second
design step is the calculation of supply current or reference
current source. The supply current is
I
Vcc
I
DM1
I
DM3
I
DM2
I
DM3
P
dis
=V
cc
1:1I
ref
(7)
where I
Vcc
, I
DMx
and I
ref
are the supply current, the related
transistor drain current and amount of reference current source,
respectively.
The third step is nding L
g
and L
s
, from Eqs. (8) and (9), where
L
g
represents the imaginary part of the equal impedance of L
g1
C
g1
.
In this step we consider an amount for (R
Lg
+R
g2
+R
nqs2
) and then
repeat this step until the simulation results conrm the well done
input matching. R
b1
and R
b2
have been used for mitigating the
effect of gate-source capacitor of transistor M
3
and as a bias of M
2
,
respectively. Arbitrarily, both are chosen to be 24kO in 0.18mm
technology [13].
o
o

1
L
s
L
g
C
gs1
s
(8)
ARTICLE IN PRESS
s
R
g
L
1
M
s
L
s
R
g
L
g
R
Lg
R
nqs
R
gs
C gs
v
+

m1 gs
g v
2
on
i
s
L
Ls
R
s
v
s
v
Fig. 1. Common LNA input architecture, (b) equivalent circuit of (a).
L
C
L
g R
g
Fig. 2. Parallel LC network and its equivalent circuit for ooo
o1
.
v
s
L
s
V
cc
3
M
R
b1
0.1 I
ref
mA =
R
s
L
g1
M
1
L
g2
M
2
C
1
C
2
3
C
C
d2
L
d2
L
d1
R
b2
C
d1
C
g1
x
y

Fig. 3. Designed and simulated LNA structure.

S. Toofan et al. / Microelectronics Journal 39 (2008) 15341537 1535
R
Lg
R
g2
R
nqs2

g
m1
L
s
C
gs1
50 (9)
In this paper, in order to reduce the area taken by L
g
, we use a
small parallel L
g1
C
g1
as an on-chip spiral inductor described in
previous section.
The fourth step is the design of inter-stage inductors. The value
of L
g2
is calculated to resonate in series with the input capacitance
of M
2
[9]. Fig. 4 shows the small signal equivalent circuit of Fig. 3
between x and y nodes, where L
ed1
, C
gs2
and R
nqs2
are the
equivalent inductance of L
d1
C
d1
, the gatesource capacitance, and
the non-quasi static effect of transistor M
2
, respectively. As was
mentioned before, the amount of R
b2
is larger than input
impedance in gate M
2
. Then from Fig. 4, the current gain can be
expressed as
i
d2
i
d1

g
m2
sC
gs2
sL
ed1
sL
ed1
sL
g2
R
nqs2
1=sC
gs2

(10)
If sL
ed1
provides sufciently high impedance, then
i
d2
i
d1

g
m2
sC
gs2

o
T
o
. (11)
This equation indicates that signicant current gain can be
obtained from the drain of M
1
to that of M
2
, leading to high overall
power gain [12]. So, in our design in order to achieve higher power
gain based on Eq. (11), we take the largest amount for L
ed1
, and
then we design it with a small parallel L
d1
C
d1
on-chip spiral
inductor structure, as mentioned before in order to reduce the
area.
Obviously, because of the Miller Effect, the input matching will
be inuenced by the inter-stage devices that in turn deteriorate
the input matching that already was achieved. Then it may be
necessary to go back to the third step and repeat the design
process again.
At the output, an inductor L
d2
is placed at the drain primarily
for two reasons: First, to resonate with the total drain capacitance
in order to achieve the desired frequency range. Second, to
provide high enough impedance to allow for a good voltage gain.
The largest amount of L
d2
is restricted by the total drain
capacitance. Then the value of L
d2
and C
d2
are chosen by
trading-off between gain and bandwidth of the circuit. Of course,
the minimum amount of C
d2
is dened by the load (e.g. mixer)
and LNA output capacitances.
4. Simulation results
The designed circuitry has been simulated using HSPICE.
Device dimensions and inductors values are given in Table 1.
Fig. 5 shows the power gain (S
21
) and noise gure (NF), and Fig. 6
shows the S
11
and S
22
for 5.5GHz center frequency. Fig. 5 shows
that we achieve a high power gain and good input impedance
matching with small on-chip spiral inductors. As indicated in
Table 2, the NF and power consumption have been reduced, power
gain increased, matching parameters (S
11
, S
22
) are in acceptable
ranges and approximately are equal to the amounts of other works
[1,7,10]. It is concluded that the structure used for LNA not only
satises most of the parameter of importance in LNA but also
allows better trade-off among the LNA dening parameters.
5. Conclusion
In this paper we designed and simulated a fully integrated
CMOS lownoise amplier with on-chip spiral inductors in 0.18mm
ARTICLE IN PRESS
i
d2
y
i
d1
x
L
ed1
g
m2
v
gs2
v
gs2
C
gs2
R
nqs2
R
b2
L
g2
Fig. 4. Small signal equivalent of current reuse part of designed LNA.
Table 1
Aspect ratio of transistors and the value of inductors
Frequency (W/L)
1
(W/L)
2
(W/L)
3
L
g1
L
g2
L
s
L
d1
L
d2
5.5GHz 125m/0.18m 62.5m/0.18m 15m/0.18m 3.9n 6.25n 0.5n 4.4n 4.65n
20
19
18
17
5 5.5
S
2
1

[
d
B
]
Frequency [GHz]
2.6
2.4
2.2
2
1.8
N
o
i
s
e

F
i
g
u
r
e

(
N
F
)

[
G
H
z
]
NF
S
21
Fig. 5. LNA noise gure (NF) and power gain (S
21
).
-8
-10
-12
-14
-16
-18
5 5.5
S
1
1

[
d
B
]
S
2
2

[
d
B
]
Frequency [GHz]
-10
-15
-20
S
22
S
11
Fig. 6. LNA S
11
and S
12
.
Table 2
Simulation results of this proposed LNA and previously published LNAs
LNA This work Ref. [1] Ref. [7]
a
Ref. [10]
f
0
(GHz) 5.5 5.2 5.7 5.7
NF (dB) 1.82.6 3 3.4 3.65
Current (mA) 1.1 3.2 2.2 8
Supply (V) 1.8 1.8 1.8 1.8
IIP3 (dBm) 6.2 5 3.3
S
11
(dB) 18.5 17 14 15.2
S
21
(dB) 20.5 12.4 11.45 14.5
S
12
(dB) o48
S
22
(dB) 21.3 16 17 14
Technology (mm) 0.18 CMOS 0.18 CMOS 0.18 CMOS 0.18 CMOS
a
Measurement results.
S. Toofan et al. / Microelectronics Journal 39 (2008) 15341537 1536
CMOS technology. Simulation results showed increased power
gain with a small inter-stage spiral inductor. Moreover, power
consumption is quite low compared to the other works [1,7,10].
Designed LNA has good noise gure, lower power dissipation,
better input impedance matching and also suitable power gain.
All these became possible by employing a current reuse structure
with modied input matching and inter-stage inductor, which
also allows good trade-off among the LNAs known parameters.
Acknowledgement
The author would like to thank the Iran Telecommunication
Research Center (ITRC) for supporting this work.
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S. Toofan et al. / Microelectronics Journal 39 (2008) 15341537 1537