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A low-voltage low-power CMOS transmitter front-end using current mode

approach for 2.4 GHz wireless communications


Qiuzhen Wan
n
, Chunhua Wang
School of Computer and Communication, Hunan University, Changsha 410082, Hunan, PR China
a r t i c l e i n f o
Article history:
Received 6 August 2010
Received in revised form
25 January 2011
Accepted 27 January 2011
Available online 17 February 2011
Keywords:
CMOS
Up-conversion mixer
Driver amplier
Current mode
High linearity
Low-power
a b s t r a c t
This paper presents a low-voltage low-power transmitter front-end using current mode approach for
2.4 GHz wireless communication applications, which is fabricated in a chartered 0.18 mm CMOS
technology. The direct up-conversion is implemented with a current mode mixer employing a novel
input driver stage, which can signicantly improve the linearity and consume a small amount of DC
current. The driver amplier utilizes a transimpedance amplier as the rst stage and employs an inter-
stage capacitive cross-coupling technique, which enhances the power conversion gain as well as high
linearity. The measured results show that at 2.4 GHz, the transmitter front-end provides 15.5 dB of
power conversion gain, output P1 dB of 3 dBm, and the output-referred third-order intercept point
(OIP3) of 13.8 dBm, while drawing only 6 mA from the transmitter front-end under a supply voltage of
1.2 V. The chip area including the testing pads is only 0.9 mm1.1 mm.
& 2011 Elsevier Ltd. All rights reserved.
1. Introduction
Over the last decade, the rapid growth in the eld of radio-
frequency (RF) and wireless communication applications has led
to considerable effort being expended in the design of high
performance and low cost RF integrated circuits and systems
with the advanced CMOS technologies [1]. The more advanced
CMOS process provides the smaller feature size and the higher
performance for the RF building blocks, while the supply voltage
is required to be reduced accordingly. The lower the supply
voltage, the smaller the voltage headroom is left for designing
circuits. Low voltage headroom would deteriorate the perfor-
mance of the RF building blocks and counteract the advantages
provided by the advanced CMOS technologies if no special
techniques are utilized.
As for voltage mode circuits, the impedance of internal nodes
is large so that the information is mostly carried by the time-
varying voltage signal. This makes the voltage mode circuits
gradually face the problem of insufcient voltage headroom in
the case of low-voltage circuit designs. The papers regarding a
2.4 GHz CMOS voltage mode transmitter and receiver front-end
have been published, such as [25]. However, it is difcult to
realize the RF building blocks in the transmitter and receiver with
lower voltage and lower power consumption. Different circuit
topologies and design techniques therefore need to be explored to
overcome this problem. Unlike voltage mode circuits, current
mode circuits have low impedance at the internal nodes and the
signal information is carried by the time-varying current signal.
Thus, the voltage signal at each node can be small, resulting in
higher linearity and lower power performance. It is well known
that in the design of the RF building blocks, high linearity and low
power dissipation are the key performance parameters. Thus, a
current mode technique can be used to improve the linearity of a
direct-conversion transmitter operating with a low supply voltage
and a low power. Therefore, current-mode circuits have a great
potential in the design of the RF integrated circuits and the
systems in advanced nanometer CMOS technologies [69].
In this paper, a novel 2.4 GHz transmitter front-end using
current mode approach in 0.18 mm CMOS technology has been
proposed. For the high linearity performance, the direct-conver-
sion transmitter is integrated with the current mode up-conver-
sion mixer as well as the transimpedance driver amplier, which
could eliminate an unnecessary current-to-voltage (IV), voltage-
to-current (VI) conversion and reduce the nonlinearity contribu-
tion. The proposed direct-conversion transmitter front-end could
provide the overall power conversion gain of 15.5 dB, which has
the advantages of a high linearity and a low power consumption
under a supply voltage of 1.2 V, at the same time, its die size is
only 0.9 mm1.1 mm including testing pads.
The contents of this paper are as follows. In Section 2, the
specication of the current-mode transmitter is presented and
Contents lists available at ScienceDirect
journal homepage: www.elsevier.com/locate/mejo
Microelectronics Journal
0026-2692/$ - see front matter & 2011 Elsevier Ltd. All rights reserved.
doi:10.1016/j.mejo.2011.01.009
n
Corresponding author. Tel.: +86 13875902717.
E-mail addresses: wanqiuzhen@yahoo.com.cn (Q. Wan),
wch1227164@sina.com (C. Wang).
Microelectronics Journal 42 (2011) 766771
the traditional transmitter architecture is discussed. Section 3
presents the circuit design and implementation of each block in
detail. The experimental results are described in Section 4 to
verify the performances of the proposed current-mode transmit-
ter front-end. Finally, the conclusions of this work are given
in Section 5.
2. Transmitter architecture
In the typical direct-conversion transmitter, a baseband digital
signal is converted to an analog signal by a digital-to-analog
converter (DAC), ltered and amplied by a low pass lter (LPF)
and a variable gain amplier (VGA). This analog baseband signal
is then up-converted to a RF signal by an up-conversion mixer
and amplied by an on-chip driver amplier. Meanwhile a power
amplier (PA), after the driver amplier can deliver high output
power, is used to satisfy the special system requirement. In this
traditional architecture, the up-conversion mixer and driver
amplier are essential building blocks that generate a high power
conversion gain with good linearity. In general, these voltage
mode transmitter front-end circuits require three series
connected transistors stacked between the supply rails, which
make them unsuitable for low voltage operation. Moreover, the
traditional mixer designs convert IF input voltage to current and
then mixing to RF output voltage, and the driver amplier
converts the mixer output voltage into current and then back
into voltage for amplication. Thus, there appear several unne-
cessary VI and IV conversions in the up-conversion mixer and
the driver amplier, which can cause nonlinearity and power
dissipation in the direct-conversion transmitter front-end [10,11].
With the motivation of low-voltage, low-power to fulll the
demand of new technology trends, Fig. 1 shows the block diagram
of the proposed transmitter front-end architecture using current
mode approach for 2.4 GHz wireless communication applications.
Here, the direct-conversion transmitter front-end is based on the
current mirror structure, which enables the VI converters to be
eliminated in the baseband analog circuits and up-conversion
mixer. Then, the amplication is performed by the transimpe-
dence driver amplier to reduce the number of VI conversion
that result in the nonlinearity. By using this structure, the VI
conversion of the up-conversion mixer input can be eliminated,
and the current output of the mixer is directly connected to the
transimpedance driver amplier input. Besides, because the
traditional transmitter system need wide range of gain control,
usually the driver amplier also implements gain control to serve
as a RF variable gain amplier. This paper focuses on the low-
voltage low-power design rather than gain control, hence, no gain
control is implemented in this version of the driver amplier, and
the gain control will be implemented in the next version. The
detailed operational principles of the current mode up-conversion
mixer and the transimpedence driver amplier are described in
the following part.
3. Circuit descriptions
3.1. Current-mode up-conversion mixer
3.1.1. Input current-squaring circuit and its class AB topology
The linearity of the conventional Gilbert-cell mixer is not good
mainly because of the VI converter nonlinearity, which becomes
more serious especially at lower bias current [12]. Because the
current mirror amplier is highly linear regardless of the bias
current, where much better linearity is expected. The gain of
the current mirror amplier can be easily set through appropriate
scaling factor between the current mirror transistors. Therefore,
we replaced VI converter by the current mirror amplier based
on the current-squaring circuit, which is modied from [13], as
shown in Fig. 2(a). The transistors M1AM4A are biased to
operate in saturation region. Supposing that the threshold vol-
tages of M1AM4A are V
th
, the relation between V
GS,M1A
, i
o
and i
IF
can be expressed as
V
GS,M1A

vcc
2

i
IF
kw=lvcc2V
th

1
i
o
N I
B

i
IF
2

i
IF
2
16I
B
!
2
I
B

1
8
k
w
l
vcc2V
th

2
3
where w/l is the channel width to the channel length ratio of the
MOS devices, km
0
C
ox
is the mobility m
0
times the oxide capaci-
tance per unit area C
ox
. The current i
1
is copied by the current
mirror amplier formed by M1A and M3A, and the aspect ratio of
M3A is N times that of M1A. From (2), the current-squaring
function is realized. The transistor M4A acts as a current buffer
and keeps the V
DS
of M3A the same as V
DS
of M1A to prevent from
the channel length modulation. Also, there is freedom to choose
the aspect ratio and bias of M1AM4A. Therefore, by choosing a
proper aspect ratio and bias of M1AM4A, the performance of this
structure can be improved without inserting any additional
circuit.
In general, the drain current I
DS
of a common-source MOS
transistor can be expressed as
I
DS
I
DS:dc
g
m
v
gs

gu
m
2!
v
2
gs

guu
m
3!
v
3
gs
UUU 4
where g
n
m
represents the nth order derivative of transconduc-
tance g
m
with respect to small signal gate-to-source voltage v
gs
.
The unwanted harmonic components inherently affected by the
quadratic characteristic of MOS transistors, lead to leakages of
VGA
DAC
LPF
Current-mode
Up-conversion mixer
Transimpedance
driver amplifier
LO
PA
Fig. 1. The proposed transmitter front-end architecture.
i
IF
M3A
M4A
i
o
M1A
M2A
i
1
VCC
VCC
IF+
M1
M2
M5 M7
M8 M6
M3
M4
IF-
Fig. 2. (a) The proposed current-squaring circuit and (b) its cross-coupled class AB
topology.
Q. Wan, C. Wang / Microelectronics Journal 42 (2011) 766771 767
input signals at the outputs, which usually counteract linearity of
the current mirror amplier. It is well known that the linearity of
a CMOS RF building block can be improved by minimization guu
m
of the circuits transconductance [14,15]. One way to minimize
guu
m
of the current-squaring circuit is using the cross-coupled
class AB topology, which is shown in Fig. 2(b). The circuit has the
advantage that the current owing through M1 and M3 contri-
butes to the output current, thanks to current mirrors MlM5 and
M3M7. This arrangement makes the circuit less sensitive to
linearity degradation due to common-mode signals, since each
output depends on both inputs.
3.1.2. Mixer circuit
The circuit diagram of the proposed CMOS current-mode
up-conversion mixer is shown in Fig. 3. The input current-
squaring circuit as the input stage, which consists of M1M8. As
seen in Fig. 3, the current output of the current-squaring circuit is
capacitive coupled to the mixer core (M9M12), whose function
is to transfer the received incoming signal from current to current
that serves as the biased current of the mixer core. This circuit has
separate bias voltages for the current-squaring circuit and the
mixer core, allowing independent optimization for the perfor-
mance in the two stages. The headroom requirements are also
relaxed in this circuit because the tail current source in the mixer
core does not govern the linearity, and hence can have much
smaller gate-overdrive. The gain of current-squaring circuit is
only determined by the ratio of device sizes and the linearity is
hardly affected by the voltage headroom.
In this design, the mixer core (M9M12) acts as switches to
modulate the output current signals provided by the current-
squaring circuit, which are double balanced topology with the
advantage of rejecting the strong LO signal and the even-order
distortion products. They switch the amplied IF current at a rate
equal to the local oscillators frequency to realize the function of
mixer. The switching action generates an up-converted signal,
which is same as that the IF current is multiplied by a square
wave. The bias voltage at the gate of the transistor M9M12 are
set near to the threshold voltage V
th
under dened the mixer core
of biasing current and output loading impedance in order to
provide a fast switching response. It is undesirable to set the bias
voltage higher or lower than the V
th
. If the bias voltage is lower
than the V
th
, then the turn-on time will increase. If the gate bias
voltage is higher than V
th
, the four switching transistors will
always be on, this will increase the power consumption. The
degeneration inductors (L1 and L2) are used in the mixer to
improve linearity. On-chip capacitors (C1C8) are applied to be
the DC-blocking capacitors to isolate the input or output port
from the dc source. The circuit is biased by means of current
mirrors (not shown in Fig. 3). Vb1 and Vb2 are the bias voltages
with the maximum DC supply voltage at 1.2 V.
Besides, R3 and R4 are the adequate resistors to enhance
the driving capability of the mixer output stage [16]. Due to the
parasitic capacitors at the drains of M9M12, the impedance at
these nodes is reduced. Since the resistors (R3 and R4) make the
high gain difcult to achieve, the peaking inductors (L3 and L4)
are resonated at 2.4 GHz with parasitic capacitances which
prevent the signal loss into the silicon substrate to get the highest
achievable gain. The peaking inductors (L3 and L4) have also an
effect, which can keep the current signal between the transimpe-
dance input stage and the mixer output stage.
3.2. Transimpedance driver amplier
With the key point of high gain, low power consumption and
high linearity, the solution proposed in this paper is the two stage
class AB transimpedance driver amplier. As can be seen in Fig. 4,
the rst stage of the driver amplier is a transimpedance structure
while the second stage is the conventional cascode topology.
By using the transimpedance amplier, the IV conversion of the
mixer output can be eliminated, and the current output of the
VCC
LO-
LO+
M9
M10
M11
M12
L1 L2
L3
C3
C4
R3
L4
Vb2
R4
RF+
RF-
VCC
IF+
IF-
M1
M2
M5
M7
M8
M6
R1 R2
Vb1
M3
M4
C1
C2
C5
C6
C7
C8
Fig. 3. The proposed CMOS current-mode up-conversion mixer.
OUT-
M13
M14
M16
M15
M17 M19
M20 M18
M21
M22
M23
M24
IN+ IN-
L6 L5
C9
C10
C11 C12
C13 C14
OUT+
R5 R6
Vb3
Vb3
VCC
Fig. 4. The proposed transimpedance driver amplier.
Q. Wan, C. Wang / Microelectronics Journal 42 (2011) 766771 768
mixer is directly connected to the transimpedance amplier input.
This reduces the voltage swing, as well as a redundant current
voltagecurrent conversion. Thus signicant advantage is obtained
because it provides high dynamic range, as well as low power
consumption. To relax the design constrains, the transimpedance
stage consists of a CMOS inverter with the self-biasing by a
feedback resistor [17]. Indeed, by stacking both NMOS and PMOS
transistors, the overall equivalent transconductance of the input
stage is increased from g
m
to g
m
+g
mp
without additional power
dissipations for the same biasing current. Furthermore, this con-
guration holds on the transistors in saturation region under a
minimum supply voltage, without design tradeoff.
The second stage amplier, which employs the conventional
cascode topology, is designed for further signal amplication. The
cascode structure is a good choice for better isolation between the
rst and second stage amplier, also the reduction of the Miller effect
onto the rst stage amplier. Another benet is that the RF gain
control can be more easily implemented at this cascode amplier
without impairing the third order distortion cancellation of the driver
amplier [4]. Essentially, the differential cascade structure can not
only reduce the second harmonics, but also increase the maximum
output power with the additional power consumption.
At the same time, the inter-stage capacitive cross-coupling
technique across the two stage driver amplier has been used.
An obvious advantage of the capacitive cross-coupling is that it is
inherently suitable for fully differential operation [18]. The capa-
citive cross-coupling technique has been used for gain enhance-
ment and inter-stage matching in this paper. The capacitive cross-
coupling pair (C9 and C10) acts as two buffer ampliers, which
offer a feedback loop to each NMOS of the differential cascade
structure to boost up the conversion gain in the high frequency. It
compensates the high frequency gain decay of NMOS and further
improves the linearity of the driver amplier.
The two LC tank circuits, established by parallel connection of
on-chip spiral inductors (L5 and L6) and on-chip capacitors (C11
and C12), and resonating at the operation frequency, are used to
improve the available power gain without requiring extra DC
voltage headroom. On-chip capacitors (C13 and C14) are applied
to be the DC-blocking capacitors to isolate the output port from
the dc source. Vb3 is the bias voltage by means of current mirror
at 1.2 V DC supply voltage (not shown in Fig. 4). The source
followers are used as the output driver stage for maximizing the
output power and provide the required output impedance to
drive the 50 O input port of the network analyzer.
Most instances about the design parameters of the transmitter
front-end are summarized in Table 1.
4. Measurement results
The proposed transmitter front-end is fabricated in a chartered
0.18 mm single-poly six-metal CMOS technology. A photomicro-
graph of the fabricated transmitter front-end is shown in Fig. 5. The
die size of the test chip is 0.9 mm1.1 mm including testing pads.
The testing board has been built by directly bonding the die on a
two-layer FR4 substrate. Fig. 6 shows the experimental setup,
which is used to measure the implemented current mode trans-
mitter. C15 and C16 are the off-chip ltering capacitors to lower
the noise induced by the supply voltage. In the measurement
processes, the input IF signal and LO signal are converted from a
single-ended output of the signal generators to a differential signal
by using external passive baluns, another external passive balun is
used to combine the differential output signal to single-ended
signal at the RF output. A single-ended RF output signal is directly
connected to a spectrum analyzer or a network analyzer both of
which have 50 O to measure the output power spectrum and the
output return loss (S22) of the transmitter front-end.
From the supply voltage of 1.2 V, the power consumption of the
transmitter front-end is 7.2 mW (not included the source followers
dissipation of the driver amplier). The gain and power loss caused
by the off-chip baluns and bonding wires have been de-embedded
from the measurement. Fig. 7 illustrates the measured result of the
S22 (RF) return loss, which is below 13 dB from 1.8 to 2.8 GHz,
indicating a good RF output matching condition. The measured
output spectrum of the proposed transmitter front-end at max-
imum gain condition is plotted in Fig. 8. In this measurement, an
input IF signal at 10 MHz of which the signal level is 30 dBm and
the LO signal at 2.39 GHz are applied. The measured LO suppres-
sion is more than 35 dB and all other unwanted harmonics are
30 dB below the desired upper sideband (USB) signal, except for
the lower sideband signal, which is equal to the wanted upper
sideband signal. However, this signal can be removed if I/Q
(in-phase and quadrature) signals are applied.
Fig. 9 shows the measured power conversion gain of the
transmitter versus LO power. The overall power conversion gain
is 15.5 dB at 2.4 GHz when the input LO power is 0 dBm. In the
two-tone measurement, the two-tone signals injected into the
transmitter are at 10 and 10.1 MHz, while the input power level is
swept from 30 to 2 dBm. The relationship between the input
and output power levels for the fundamental tones and third-
order inter-modulation (IM3) products at maximum gain condi-
tion are plotted in Fig. 10. The measurement result shows that the
output P1 dB compression point and OIP3 of the transmitter
front-end approximately equal to 3 and 13.8 dBm, respectively.
From the measurement results, the maximum output power of
the transmitter front-end equal approximately to 4.5 dBm. The
power amplier, if it is necessary, can be integrated to deliver
higher output power to satisfy the special system requirement.
Table 1
Summary of instance parameters.
Inst. Para. Inst. Para. Inst. Para.
M1M4 w/l 1/0.18 mm C1, C2 10 pF C13, C14 5.6 pF
M5M8 w/l 320/0.18 mm C3, C4 3.6 pF R1, R2 307 O
M9M12 w/l 51/0.18 mm C5, C6 4.5 pF R3, R4 305 O
M13M16 w/l 40/0.18 mm C7, C8 2.5 pF R5, R6 5.2 kO
M17M20 w/l 90/0.18 mm C9, C10 0.4 pF L1L4 1.43 nH
M21M24 w/l 120/0.18 mm C11, C12 0.62 pF L5, L6 5.3 nH
Fig. 5. Photomicrograph of the fabricated transmitter front-end.
Q. Wan, C. Wang / Microelectronics Journal 42 (2011) 766771 769
The measurement results meet the post-layout simulation
results quite good. Most of the values are 71 dB deviation
compared with the simulation results. The overall measured
performance of the 2.4 GHz current-mode transmitter front-end
is summarized in Table 2, where comparisons with other published
works are also provided. From Table 2, the proposed current mode
transmitter front-end can achieve a good linearity and a high
conversion gain with low LO power, while at the same time, meets
the requirement of low-voltage and low-power applications.
LO
source
Match
network
Spectrum
alalyzer
Network
alalyzer
VCC VCC
C15 C16
L
bondwire
L
bondwire
IF
source
Fig. 6. Block diagram of the transmitter front-end test setup.
1 2 3
-20
-5
-10
-15
0
4 0
RF Frequency (GHz)
R
F

R
e
t
u
r
n

L
o
s
s

(
d
B
)
Fig. 7. Measured output return loss (S22) of the transmitter front-end.
Fig. 8. Measured output spectrum of the transmitter front-end at 30 dBm
input.
-6 0 3 6
16
14
C
o
n
v
e
r
s
i
o
n

G
a
i
n

(
d
B
)
LO Power (dBm)
10
12
8
Conversion gain (USB)
-3
Fig. 9. Measured power conversion gain versus LO power with RF2.4 GHz.
R
F

O
u
t
p
u
t

P
o
w
e
r

(
d
B
m
)
IF Input Power (dBm)
-34 -24 -14 -4 4
15
0
-30
-15
-45
-60
IM3 (USB)
USB
Fig. 10. Measured OIP3 of the proposed transmitter front-end (LO power: 0 dBm).
Q. Wan, C. Wang / Microelectronics Journal 42 (2011) 766771 770
5. Conclusion
This paper has proposed the analysis and measurement of a
2.4 GHz CMOS direct-conversion transmitter front-end, which is
fabricated in a chartered 0.18 mm CMOS technology. The current
mode up-conversion mixer uses the input current-squaring circuit
of cross-coupled class AB topology as the input stage, which
signicantly improves the linearity performance. Two stage tran-
simpedance driver amplier shares the inter-stage capacitive cross-
coupling technique, which provides high enough gain as well as
high linearity to drive 50 O output loading. The measurement
results show that the transmitter front-end only consumes
7.2 mW under a low supply voltage of 1.2 V, the circuit provides
15.5 dB of overall power conversion gain, output P1 dB of 3 dBm,
and the output-referred third-order intercept point (OIP3) of
13.8 dBm. The excellent results have shown that the proposed
current-mode transmitter front-end is suitable for the applications
of low-voltage low-power RF and wireless communication systems.
Future research will be conducted to design a complete
2.4 GHz CMOS current mode single-sideband transmitter using
the proposed I/Q signals arrangement and integrating it with an
on-chip current mode analog baseband circuits.
Acknowledgement
The authors would like to thank the National Nature Science
Foundation of China for nancially supporting this research under
no. 60776021.
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improvement technique for a differential cascode LNA, IEEE Journal of Solid-
State Circuits 43 (2008) 588599.
Table 2
Performance summary of the proposed transmitter front-end.
Parameters [10] [11] This work
Technology 0.18 mm CMOS 0.18 mm CMOS 0.18 mm CMOS
LO power 3 dBm 2 dBm 0 dBm
Output return loss 23 dB 14 dB o-13 dB
Power conversion gain 11.5 dB 16 dB 15.5 dB
Output P1 dB 3 dBm 2 dBm 3 dBm
OIP3 12 dBm 13.8 dBm
LO suppression 24 dB 30 dB 35 dB
Supply voltage 1.8 V 1.25 V 1.2 V
Die size 0.96 (mm
2
) 0.8 (mm
2
)
a
0.99 (mm
2
)
a
It does not included the off-chip size.
Q. Wan, C. Wang / Microelectronics Journal 42 (2011) 766771 771

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