Advanced VLSI Design

Lecture 7: CMOS Transistor Theory

Shaahin Hessabi
Department of Computer Engineering
Sharif University of Technology
Adapted with modifications from lecture notes from
Rutgers university
Advanced VLSI Design
Slide 2 of 29 Sharif University of Technology
Outline
Introduction
MOS Capacitor
nMOS I-V Characteristics
pMOS I-V Characteristics
Adjustments for non-ideal 2
nd
-order effects
Advanced VLSI Design
Slide 3 of 29 Sharif University of Technology
Introduction
So far, we have treated transistors as ideal switches
An ON transistor passes a finite amount of current
Depends on terminal voltages
Derive current-voltage (I-V) relationships
Transistor gate, source, drain all have capacitance
I = C (V/t) -> t = (C/I) V
Capacitance and current determine speed
Advanced VLSI Design
Slide 4 of 29 Sharif University of Technology
MOS Characteristics
MOS majority carrier device
Carriers: e
--
in nMOS, holes in pMOS
V
t
channel threshold voltage
(cuts off for voltages < V
t
)
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Slide 5 of 29 Sharif University of Technology
nMOS Enhancement Transistor
Moderately doped p type Si substrate
Two heavily doped n
+
regions
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I vs. V Plots
Enhancement and
depletion
transistors
CMOS: uses only
enhancement
transistors
nMOS uses both
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MOSFET Transistors
For given V
ds
& V
gs
, I
ds
controlled by:
Distance between source & drain L
Channel width W
V
t
Gate oxide thickness t
ox
gate oxide
Carrier mobility
Advanced VLSI Design
Slide 8 of 29 Sharif University of Technology
MOS Capacitor
Gate and body form MOS capacitor
Operating modes
Accumulation
Depletion
Inversion
polysilicon gate
(a)
silicon dioxide insulator
p-type body
+
-
V
g
<0
(b)
+
-
0 <V
g
<V
t
depletion region
(c)
+
-
V
g
>V
t
depletion region
inversion region
Advanced VLSI Design
Slide 9 of 29 Sharif University of Technology
Terminal Voltages
Mode of operation depends on V
g
, V
d
, V
s
V
gs
= V
g
V
s
V
gd
= V
g
V
d
V
ds
= V
d
V
s
= V
gs
V
gd
Source and drain are symmetric diffusion terminals
By convention, source is terminal at lower voltage (NMOS)
Hence V
ds
0
nMOS body is grounded. First assume source is 0 too.
Three regions of operation
Cutoff
Linear
Saturation
V
g
V
s
V
d
V
gd
V
gs
V
ds
+
-
+
-
+
-
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Slide 10 of 29 Sharif University of Technology
nMOS Cutoff
No channel
I
ds
= 0
+
-
V
gs
=0
n+ n+
+
-
V
gd
p-type body
b
g
s
d
Advanced VLSI Design
Slide 11 of 29 Sharif University of Technology
nMOS Linear
Channel forms
Current flows from d to s
carriers (e
-
for nMOS)
from s to d
I
ds
increases with V
ds
Similar to linear resistor
At drain end of channel,
only difference between
gate & drain voltages
effective for channel
creation
+
-
V
gs
>V
t
n+ n+
+
-
V
gd
=V
gs
+
-
V
gs
>V
t
n+ n+
+
-
V
gs
>V
gd
>V
t
V
ds
=0
0 <V
ds
<V
gs
-V
t
p-type body
p-type body
b
g
s
d
b
g
s
d
I
ds
Advanced VLSI Design
Slide 12 of 29 Sharif University of Technology
nMOS Saturation
Channel pinches off
I
ds
independent of V
ds
We say current saturates
Similar to current source
+
-
V
gs
>V
t
n+ n+
+
-
V
gd
<V
t
V
ds
>V
gs
-V
t
p-type body
b
g
s
d
I
ds
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Slide 13 of 29 Sharif University of Technology
I-V Characteristics
In Linear region, I
ds
depends on
How much charge is in the channel?
How fast is the charge moving?
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Channel Charge
MOS structure looks like parallel plate capacitor while
operating in inversion
Q
channel
= CV
C = C
g
=
ox
WL/t
ox
= C
ox
WL
Average gate to channel potential:
V = V
gc
V
t
= (V
gs
V
ds
/2) V
t
n+ n+
p-type body
+
V
gd
gate
+ +
source
-
V
gs
-
drain
V
ds
channel
-
V
g
V
s
V
d
C
g
n+ n+
p-type body
W
L
t
ox
SiO
2
gate oxide
(good insulator,
ox
=3.9)
polysilicon
gate
C
ox
=
ox
/ t
ox
V
gc
=(V
gs
+V
gd
)/2 = (V
gs
-V
ds
/2)
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Slide 15 of 29 Sharif University of Technology
Carrier Velocity
Charge is carried by e-
Carrier velocity proportional to lateral E-field
between source and drain
= E called mobility
E = V
ds
/L
Time for carrier to cross channel:
t = L /
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Slide 16 of 29 Sharif University of Technology
nMOS Linear I-V
Now we know
How much charge Q
channel
is in the channel
How much time t each carrier takes to cross
c h a n n e l
ox
2
2
d s
d s
g s t d s
d s
g s t d s
Q
I
t
W
V
C V V V
L
V
V V V

=

=



=


ox
=
W
C
L

Current Vgs-Vt since Vgs-Vt sets the number of carriers in the channel
Current C
ox
1/tox
Current W/L Resistance L/W
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Slide 17 of 29 Sharif University of Technology
nMOS Saturation I-V
If V
gd
< V
t
, channel pinches off near drain
When V
ds
> V
dsat
= V
gs
V
t
Now drain voltage no longer increases current
( )
2
2
2
dsat
ds gs t dsat
gs t
V
I V V V
V V

=


=
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Slide 18 of 29 Sharif University of Technology
nMOS I-V Summary
( )
2
cutoff
linear
saturatio
0
2
2
n
gs t
ds
ds gs t ds ds dsat
gs t ds dsat
V V
V
I V V V V V
V V V V

<

= <

>

Shockley 1
st
order transistor models
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Ideal Quadratic NMOS I-V Curve
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Slide 20 of 29 Sharif University of Technology
Example
Using a 0.6 m process from AMI Semiconductor
t
ox
= 100
= 350 cm
2
/V*s
V
t
= 0.7 V
Plot I
ds
vs. V
ds
V
gs
= 0, 1, 2, 3, 4, 5
Use W/L = 4/2
( )
14
2
8
3.9 8.85 10
350 120 /
100 10
ox
W W W
C A V
L L L

= = =

0 1 2 3 4 5
0
0.5
1
1.5
2
2.5
V
ds
I
d
s

(
m
A
)
V
gs
=5
V
gs
=4
V
gs
=3
V
gs
=2
V
gs
=1
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Slide 21 of 29 Sharif University of Technology
pMOS I-V
All dopings and voltages are
inverted for pMOS
Mobility
p
is determined by
holes
Typically 2-3x lower than that
of electrons
n
Thus pMOS must be wider
to provide same current
In this class, assume:

n
/
p
= 2
Advanced VLSI Design
Slide 22 of 29 Sharif University of Technology
Non-ideal I-V Effects
The saturation current increases
less than quadratically with
increasing V
gs
Caused by 2 effects:
1. velocity saturation: at high lateral
field strengths (V
ds
/L), carrier
velocity ceases to increase linearly
with E.
lower I
ds
than expected at high V
ds
.
2. mobility degradation: at high vertical field strengths (V
gs
/t
ox
), the
carriers scatter more often less current than expected at high
V
ds
.
Advanced VLSI Design
Slide 23 of 29 Sharif University of Technology
Channel length modulation
The saturation current increases slightly with V
ds
.
Reason: higher V
ds
increases the size of the depletion region
around the drain effectively shortens the channel.
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Slide 24 of 29 Sharif University of Technology
Leakage Current
Sources of leakage current in
nominally OFF transistors:
1. Subthreshold conduction: at V
gs
< V
t
the current drops off exponentially,
rather than abruptly becoming zero.
V
t
itself is influenced by V
sb
, called
body effect.
2. J unction leakage: source and drain
diffusions are reverse-biased diodes
with respect to substrate or well.
3. Tunneling through the gate: as the thickness of gate oxide
decreases, electrons tunnel through the gate (I
g
> 0).
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Gate Leakage Current
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Slide 26 of 29 Sharif University of Technology
Velocity Saturation and Mobility Degradation
At high field strengths, drift
velocity rolls off due to carrier
scattering and saturates at
sat
:
= E
lat
/(1+ E
lat
/ E
sat
)

sat
= E
sat
6-10 x 10
6
cm/s for electrons
saturation field: 2 x 10
4
V/cm for
NMOS transistors.
4-8 x 10
6
cm/s for holes.
Saturation current for completely velocity saturated
transistors ( =
sat
): I
ds
= C
ox
W (V
gs
V
t
)
sat
Current is linearly (rather than quadratically) dependent on
voltage.
Advanced VLSI Design
Slide 27 of 29 Sharif University of Technology
Velocity Saturation (contd)
-power law model:
0; V
gs
< V
t
cutoff
I
ds
= I
dsat
V
ds
/V
dsat
; V
ds
< V
dsat
linear
I
dsat
; V
ds
> V
dsat
saturation
Long channel transistors or low V
DD
:
quadratic I-V characteristics in
saturation ( =2).
decreases to 1 for velocity-saturated
transistors.
also takes into account the mobility degradation.
For short channel transistors, the lateral field increases (unless V
DD
decreases) and transistor becomes more velocity saturated.
No performance benefit to raising V
DD
Two transistors in series deliver more than half the current of a single transistor.
PMOS transistors experience less velocity saturation.
Advanced VLSI Design
Slide 28 of 29 Sharif University of Technology
Temperature Dependence
Both mobility and threshold voltage decrease with rising temperature.
decrease (important for ON transistor) lower I
ds
at high T.
V
t
decrease (important for OFF transistor) higher leakage current at
high T.
MOS characteristics degrade with temperature.
Advanced VLSI Design
Slide 29 of 29 Sharif University of Technology
Geometry Dependence
L
eff
= L
drawn
+ X
L
-2L
D
W
eff
= W
drawn
+ X
W
-2W
D
X
L
:manufacturers adjustment (usually negative)
L
D
: lateral diffusion under the gate
A transistor drawn twice as long may have an effective
length that is more than twice as great current is
less than half. Other reasons for this:
V
t
increases for longer transistors less current
Long transistors experience less channel length modulation
less current
For current matching, use the same L and W for all
devices; make current ratios by tying identical
transistors in parallel.