Answer Key for the Model Question October 2009

Subject: VLSI echnolo!y

Subject code: L"02
#A$ A
1. MGS preparation from silica
EGS preparation from MGS
Single crystal silicon growth from EGS
2. Metallization is for interconnection and power rails.
3. Isolation is to avoid electrical contact between different devices in the Is.
!" #$nction isolation% simple& b$t poor performance.
'ielectric isolation% better electrical properties.
(. Gate material m$st cover the channel completely& otherwise ca$ses more parasitic
capacitance effect. Si)gate technology has this feat$re.
*. In M+S str$ct$re parasitic pnp transistor ,horizontal- and npn transistor ,vertical-
ca$ses a low resistance path between .
''
and .
SS
. /his res$lts a short)circ$iting of
device.
0sing trench isolation this problem can perfectly solved.
1. /he dimension of transistors is limited.
/he speed of the device is limited by carrier velocity sat$ration.
/he interconnections are also limited.
2. %Refer teaching material.)
3. 4ess delay sensitive to load
5igh o$tp$t drive c$rrent.
5igh transcond$ctance.
4ow power dissipation compare to "M+S and 6ipolar technologies.
7. Ga8s carriers are aro$nd si9 times faster than Si carriers
Its crystal str$ct$re gives that property.
1:. MES;E/ made $p of Ga8s semicond$ctors and hence faster.
M+S;E/ made $p of Si semicond$ctors so speed is limited to some
threshold.
#A$ &
11. Refer Teaching material (page 5 and 6 of file Module1.doc)
12. 4ithography in I technology is art of ma<ing mas<s for window c$ts which are
$sed to performing vario$s process li<e diff$sion& metallization& o9idation etc.
'ifferent lithography techni=$es%
> !hotolithography
> ;ine line lithography
!hotolithography $ses photons for forming window c$ts& hence poor
resol$tion& b$t cheap.
;ine lithography $ses electron beam& 9)ray and ion beam for forming
window c$ts and res$lts good resol$tion& b$t e9pensive.
,disc$ss this three methods with its resist materials& printing techni=$es
and compare three types-.
13. Step 1% rystal growth ,!)s$bstrate-.
Step 2% ?afer slicing and polishing
Step 3% "@ b$ried layer diff$sion by mas<1.
Step (% " epita9ial layer growth ,ollector-.
Step *% Isolation diff$sion ,! diff$sion- by mas<2.
Step 1% 6ase ,!- diff$sion by mas<3.
Step 2% Emitter ,"@- diff$sion by mas< (.
Step 3% +pen contact windows by mas<*.
Step 7% Metallization for E& 6 and contacts by mas<1.
Step 1:% ?ire band connections to header.
Step 11% Glassivation.
Step 12% Seal the pac<age.
,Draw the necessary structures for each steps)
Imp$rity !rofiles%
1. "@ b$ried profile
2. " epilayer profile
3. ! type base profile
(. "@ emitter diff$sion profile.
,Draw the profiles and explain)
1(. 'iff$sed resistors%
6ase diff$sed resistor) diff$sed d$ring base and moderate resistance.
Emitter diff$sed resistors) diff$sed d$ring emitter diff$sion and
moderate resistance.
Epita9ial resistors% Epilayer resistance and high resistance val$e
!inched resistors%
6ase pinched resistors
!inched epita9ial resistor
Ion implanted resistors
M+S resistors
'iff$sed M+S resistors
!oly Silicon resistors
?ell resistors
1*. ;abrication steps of p)well M+S
1. Si s$bstrate growth
2. " epilayer growth.
3. Si+
2
'eposition.
(. 'eposit ! type ions $sing mas<1 for forming !)well.
*. Si
3
"
(
'eposition on the active areas of !M+S and "M+S transistors by
mas< 2.
1. 'eposit thin Si+
2
layer and poly)Si for gate $sing mas< 3.
2. 'eposit !)ions for drain and so$rce of !M+S in " s$bstrate by mas< (.
3. 'eposit thic< Si+
2
layer for isolation.
7. 'eposit ")ions for drain and so$rce of "M+S in !)well by mas< *.
1:. 'efine contact c$ts $sing mas< 1.
11. Metallization is performed for .
''
& .
SS
& 'rain& So$rce and Gate terminals by
mas< 1.
12. ?ire band connections to header.
13. Glassivation.
1(. Seal the pac<age
(Draw the necessary structures for each step)
'o()*rison
#+,ell -+,ell
" s$bstrate contains ! devices and deep !
type doped area called !)well contains "
devices.
! s$bstrate contains " devices and deep "
type doped area called ")well contains !
devices.
!)well prod$ction is easy ,short period
implantation is eno$gh-.
")well prod$ction is diffic$lt.
Speed of " devices in well is low
comparing to those in s$bstrate.
" devices are in s$bstrate& hence faster.
!erformance difference between ! and "
devices is low.
Increase in performance difference between
! and " devices.
Incompatible with "M+S technology& so
more additional processing steps are
re=$ired.
ompatible with "M+S technology& only
2:A additional processing steps are
re=$ired.
4ess vol$me of prod$ction 5igh vol$me of prod$ction
4atch)$p sensitivity is more. Bed$ced latch)$p sensitivity& beca$se of
high resistivity !)s$bstrate.
ostly 4ow cost
11. Stic< diagram is $sed to convey the information of vario$s layers in Is.
It $ses colo$r code for each layer.
8cts as interface between circ$it designer and fabricator.
(Refer teaching material module for rules for drawing)
12. 'raw the circ$it diagram.
'raw the s$itable stic< diagram $sing colo$r code and give the layer information
of each colo$r.
onvert the stic< diagram into mas< layo$t with design r$les ,C)based-.
(Refer teaching material)
O$
13. 6$s str$ct$res carries data and control information and are lengthy wires within
the Is.
'ifferent types%
!assive 6$s Bail) ;loating rail& hence slow& b$t low power cons$mption.
/his b$s s$ffers from transistor ratio problems.
8ctive 6$s Bail) ?ired "+B connection with a common p$ll)$p
transistor. ;aster than passive type& b$t more power cons$mption. /his b$s also
s$ffers from transistor ratio problems.
!re)charged 6$s) 6ased on the cloc< and two type% "M+S and !M+S
type. /hey are faster and less power cons$mption.
(Refer the teaching material for circuit diagrams)
17. ;abrication steps for Ga8s E)MES;E/ are%
1. Semi)ins$lating Ga8s s$bstrate growth.
2. Si
3
"
(
layer deposition.
3. 'eposit ")ions ,lightly doped- for channel $sing mas< 1.
(. Si
3
"
(
layer deposition.
*. 'eposit ")ions ,heavily doped- for So$rce and 'rain $sing
mas< 2.
1. Si+
2
layer deposition for second layer ins$lation.
2. 8nnealing
3. +pen contact c$ts for 'rain and So$rce and deposit ohmic
contacts ,metal alloy)8$DGeD!t- by mas< 3.
7. +pen windows for metal gate deposition and deposit metal
,metal alloy) /iD!tD8$- by mas< (.
1:. ;irst level metallization is performed of metal contact for
'rain and So$rce $sing mas< *.
11. +pen via c$ts and perform second level metallization for
'rain and So$rce contacts $sing mas< 1.
12. ?ire band connections to header.
13. Glassivation.
1(. Seal the pac<age.
(Draw the necessary structures for each step)
2:.
Sub+(icron 'MOS .*As
4ow power dissipation Medi$m power dissipation
5igh inp$t impedance& so low drive c$rrent
re=$ired
5igh inp$t impedance& so low drive c$rrent
re=$ired
5igh noise margin 4ow noise margin
5igh speed .ery high speed
5igh pac<ing density 5igh pac<ing density
5igh delay sensitivity to load)fan)o$t 5igh delay sensitivity to load as well as
so$rce.
4ow o$tp$t drive c$rrent 4ow o$tp$t drive c$rrent
6idirectional 6idirectional
Integration of photonics and electronics is
not possible
Integration of photonics and electronics is
possible
Ideal switching device Beasonable switching device
Mas< levels 12)11 are re=$ired Mas< levels 1)1: are re=$ired
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