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$UESTION%BAN&
$'( Differentiate )et*een +icro,rocessor and +icrocontroller-
Ans( 1. Microprocessor is a general purpose devise
2. Microcontroller is indented for a specific purpose
3. Memory ,I/O devices etc need to be interfaced with microprocessor
. Microcontroller is having its own memory , I/O etc integrated with it
!. "e can say that microprocessor is a cpu on a chip
#. Microcontroller is a system on a chip
$.( /hat is an instruction 0ueue- E1,lain-
Ans( $his is introduced in %&%# processor.$his 'ueue is in the (I) and is used for
storing the predecoded instructions.$his will overlap the fetching and e*ecution cycle.
$he + ) will ta,e the instructions from the 'ueue for decoding and e*ecution.
$2( /hat is RE! ,refi1- o* it functions for string instructions-
Ans( $his -+. prefi* is used for repeating. $he instruction with -+. prefi* will e*ecute
repeatedly till the count in the c* register will be /ero. $his can be used in with some of
the string handling instructions.
$3( E1,lain the instructions 4i5 LDS 4ii5 !USF 4iii5 TEST 4i65 7LD
Ans(
i0 123 4 load pointer to 23
Move a 32 bit content from the memory given as source to 1#
bit destination register specified and to 23 register.
ii0 .)356 4 push the flag
7fter the e*ecution the content of the flag register will be
pushed to the stac,.$he higher byte to sp81 and lower to
sp82
iii0 $+3$ 4 logical comparison
$his will compare the source and the destination specified.
$he result will be reflected only in the flag registers.

iv0 912 4 this will clear the direction flag.
$8( /hat is stac9- E1,lain the use and o,eration of stac9 and stac9 ,ointer-
Ans( 7 stac, is a portion of the memory used for the temporary storage. 7 stac, is a last
In first Out memory. 7 stac, grows in the decreasing order. 7 stac, will hold the
temporary information:s push and pop are the instructions used for storing and
accessing data from the stac,. 9ontents can be moved as 1# bit only using push and
pop instructions.
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$:( /hat are the flags in ;<;:-
Ans( In %&%# 9arry flag, .arity flag, 7u*iliary carry flag, Aero flag, Overflow flag,
$rap flag, Interrupt flag, 2irection flag, and 3ign flag.
$=( /hat are the 6arious interru,ts in ;<;:- E1,lain(
Ans( Mas,able interrupts, >on8Mas,able interrupts.
i0 7n interrupt that can be turned off by the programmer is ,nown as Mas,able
interrupt.
ii0 7n interrupt which can be never be turned off Bie.disabled0 by the programmer
is ,nown as >on8Mas,able interrupt.
$;( /hich interru,ts are generally used for critical e6ents-
Ans( >on8Mas,able interrupts are used in critical events. 3uch as .ower failure,
+mergency, 3hut off etc.
$>( /hat is the effect of e1ecuting the instruction-
?O" 7@A BSOUR7EC?E?D
/here SOUR7EC?E? e0ual to .<': is a +e+ory location offset relati6e to
the current data seg+ent starting at address 'A<<<
':
Ans( +*ecution of this instruction results in the following4
BB230 & C 2&
1#
0 B910
BB230 & C 2&
1#
C 1
1#
0 B950
In other words, 91 is loaded with the contents held at memory address
17&&&
1#
C2&
1#
C1
1#
D17&21
1#
$'<( The original contents of A@A BLA *ord%siEed +e+ory location SU?A and carry
flag
7F are '.23A ABA <<7DA and <A res,ecti6ely( Descri)e the results of
e1ecuting the follo*ing se0uence of instructionsF
ADD A@A BSU?D
AD7 BLA <8
IN7 /ORD !TR BSU?D
Ans( +*ecuting the first instruction adds the word in the accumulator and the word in the
memory location pointed to by address 3)M. $he result is placed in the
accumulator. $hat is,
B7E0 F B7E0 C B3)M0 D 1235 C &&925 D 13&15
$he carry flag remains reset.
$he second instruction adds to the lower byte of the base register B(10 the
immediate operand !5 and the carry flag, which is &5. $his gives
B(10 F B(10 C imm% C B960 D 7(5 C !5C &5 D (&5
3ince no carry is generated 96 remains reset.
$he last instruction increments the contents of memory location 3)M by one. $hat
is,
B3)M0 F B3)M0 C 15 D &&925 C 15 D&&9+5
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$''( The .Gs co+,le+ent signed data contents of AL e0ual %' and the contents of
7L are
%.( /hat result is ,roduced in A@ )y e1ecuting the follo*ing instructionsF
i5 ?UL 7L ii5 I?UL 7L
Ans( 7s binary data, the contents of 71 and 91 are
B710 D 81 Bas 2:s complement0 D 11111111
2
D 665
B910 D 82 Bas 2:s complement0 D 1111111&
2
D 6+5
+*ecuting the M)1 instruction gives
B7E0 D 11111111
2
G 1111111&
2
D 111111&1&&&&&&1&
2
D 62&25
$he second instruction multiplies the two numbers as signed numbers to generate
the signed result. $hat is,
B7E0 D 815 G 825
D 25 D &&&25
$'.( E1,lain different ty,es of registers in ;<;: +icro,rocessor arch(
Ans( Most of the registers contain data/instruction offsets within # @( memory
segment. $here are four different # @( segments for instructions, stac,, data and e*tra
data. $o specify where in 1 M( of processor memory these segments are located the
processor uses four segment registers4
7ode seg+ent B930 is a 1#8bit register containing address of # @( segment with
processor instructions. $he processor uses 93 segment for all accesses to instructions
referenced by instruction pointer BI.0 register. 93 register cannot be changed directly.
$he 93 register is automatically updated during far Hump, far call and far return
instructions.
Stac9 seg+ent B330 is a 1#8bit register containing address of #@( segment with
program stac,. (y default, the processor assumes that all data referenced by the stac,
pointer B3.0 and base pointer B(.0 registers is located in the stac, segment. 33 register
can be changed directly using .O. instruction.
Data seg+ent B230 is a 1#8bit register containing address of #@( segment with
program data. (y default, the processor assumes that all data referenced by general
registers B7E, (E, 9E, 2E0 and inde* register B3I, 2I0 is located in the data segment.
23 register can be changed directly using .O. and 123 instructions.
E1tra seg+ent B+30 is a 1#8bit register containing address of #@( segment, usually
with program data. (y default, the processor assumes that the 2I register references the
+3 segment in string manipulation instructions. +3 register can be changed directly using
.O. and 1+3 instructions.
It is possible to change default segments used by general and inde* registers by prefi*ing
instructions with a 93, 33, 23 or +3 prefi*.
7ll general registers of the %&%# microprocessor can be used for arithmetic and logic
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operations. $he general registers are4
Accu+ulator register consists of 2 %8bit registers 71 and 75, which can be combined
together and used as a 1#8bit register 7E. 71 in this case contains the low8order byte of
the word, and 75 contains the high8order byte. 7ccumulator can be used for I/O
operations and string manipulation.
Base register consists of 2 %8bit registers (1 and (5, which can be combined together
and used as a 1#8bit register (E. (1 in this case contains the low8order byte of the word,
and (5 contains the high8order byte. (E register usually contains a data pointer used for
based, based inde*ed or register indirect addressing.
7ount register consists of 2 %8bit registers 91 and 95, which can be combined together
and used as a 1#8bit register 9E. "hen combined, 91 register contains the low8order
byte of the word, and 95 contains the high8order byte. 9ount register can be used as a
counter in string manipulation and shift/rotate instructions.
Data register consists of 2 %8bit registers 21 and 25, which can be combined together
and used as a 1#8bit register 2E. "hen combined, 21 register contains the low8order
byte of the word, and 25 contains the high8order byte. 2ata register can be used as a port
number in I/O operations. In integer 328bit multiply and divide instruction the 2E
register contains high8order word of the initial or resulting number.
$he following registers are both general and inde* registers4
Stac9 !ointer B3.0 is a 1#8bit register pointing to program stac,.
Base !ointer B(.0 is a 1#8bit register pointing to data in stac, segment. (. register is
usually used for based, based inde*ed or register indirect addressing.
Source Inde1 B3I0 is a 1#8bit register. 3I is used for inde*ed, based inde*ed and register
indirect addressing, as well as a source data address in string manipulation instructions.
Destination Inde1 B2I0 is a 1#8bit register. 2I is used for inde*ed, based inde*ed and
register indirect addressing, as well as a destination data address in string manipulation
instructions.
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Introduction to Ad6anced ,rocessors
$'( E1,lain the ;<';: +icro,rocessor e6olution(
Ans( $he %&1%# microprocessor was developed by Intel in 1I%2. It is an improved %&%#
with several common support functions built in4 cloc, generator, system controller,
interrupt controller, 2M7 controller, and timer/counter. It also added % new instructions
and e*ecutes instructions faster than the %&%#. 7s with the %&%#, it has a 1#8bit e*ternal
bus and is also available as the %&1%%, with an %8bit e*ternal data bus. $he initial cloc,
rate of the %&1%# and %&1%% was # M5/. In 1I%J Intel announced the second generation
of the %&1%# family4 the %&91%#/91%%. $he %&1%# was redesigned as a static, stand8alone
module ,nown as the %&91%# Modular 9ore and is pin compatible with the %&1%#
family, while adding an enhanced feature set. $he high8performance 95MO3 III process
allowed the %&91%# to run at twice the cloc, rate of the >MO3 %&1%#, while consuming
less than one8fourth the power.
In 1II1 the %&91%# Modular 9ore family was again e*tended with the introduction of the
%&91%#E1. $he %&91%#E1/91%%E1 is a higher performance, lower power replacement
for the %&91%#/91%%
$.( Dra* the internal architecture of ;<';:(
Ans(
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$2( /hat are the features of ;<';:-
Ans( $he various enhancement features of %&1%#/%% processors are 4
9loc, ?enerator
.rogrammable Interrupt 9ontroller
$imers
.rogrammable 2M7 )nit
.rogrammable 9hip 3election )nit
.ower 3ave/.ower 2own 6eature
-efresh 9ontrol )nit

$3( Dra* the ti+ing diagra+ of ;<';:(
Ans(


>ote, the only difference in %&1%#/%% vs. %&%#/%% is in the generation of 71+ which
is asserted one8half cloc, cycle earlier
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$8( Dra* the internal architecture of ;<.;:(
Ans(

$:( /hat are the features of ;<.;:-
Ans( %&2%# have following features4
1. independent units B%&%# has only two units0
2. 28bit 7ddress bus in
3. (us )nit generates all data, address and I/O signals.
.refetcher flushes the prefetched data, if I) finds a branch instruction.
. 7ddress )nit B7)0 off8loads address generation, translation and chec,ing from
().units B
!. Instruction )nit off8loads +) by performing the instruction decoding.
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$=( Dra* the interfacing diagra+ of ;<.;:(
Ans(
ly two units0
$;( E1,lain the e6olution of ;<.;:(
Ans( $he %&2%# was introduced by Intel on 6ebruary 1, 1I%2. 7s the %&1%#/%&1%% 9.)s
were not really significant to personal computing, the %&2%# was IntelKs ne*t step
processor for micro computers.
Intel added four more address lines to the %&%#/%&1%# design. $he %&%#, %&%%, %&1%#,
and %&1%% all contained 2& address lines, giving these processors one megabyte of
addressibility B2L2& D 1M(0. $he %&2%#, with its 2 address lines, gives 1# megabytes of
addressibility B2L2 D 1# M(0.
$he most substantial difference between the %&2%# and the %&%#/%&%% is the addition of a
protected mode. In protected mode, segment registers became pointers into a table of
memory descriptors rather than being a direct part of the address. 7mong other things,
protected mode allows safe e*ecution of multiple programs at once by protecting each
program in memory. 2O3 normally operates in real mode, in which segment registers act
Hust as they do in the %&%#/%&%%. .rotected mode is used by Microsoft "indows, I(MKs
O3/2 and )>IE. B6or an introduction to protected mode please refer to this source0
$he %&2%# is a much more powerful 9.) than the %&%#, offering 38# times the
performance of it. $he # M5/ %&2%# is the 9.) of the I(M 7$ B7dvanced $echnology0,
which also introduced a 1#8bit motherboard and 1#8bit e*pansion bus to the .9 world.
$he I(M 7$ was introduced in 1I%! 8 three years after introduction of the %&2%#.
"ith the %&2%#, the first MchipsetsM were introduced. $he computer chipset is a set of
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chips that replaced do/ens of other peripheral chips while maintaining identical
functionality. 9hips and $echnologies became one of the first popular chipset companies.
Intel second8sourced the %&2%# to ensure an ade'uate supply of chips to the computer
industry. 7M2, I(M, and 5arris were ,nown to produce %&2%# chips as O+M productsN
while 3iemens, 6uHitsu, and @ruger either cloned it or was also second8sources. (etween
these various manufacturers, the %&2%# was offered in speeds ranging from # M5/ to 2!
M5/4
Intel4#812.!M5/
3iemens4%81#M5/
7M24%82&M5/
5arris41&82!M5/
$he %&2%# was typically made in 3 pac,age versions, each with #% contacts4 a .?78,
91998and a .1998pac,age.
$>( Is there any instruction added to ;<.;: instruction set- If yesA +ention(
Ans( ;es, in %&2%# few instruction is added with %&1%# instruction set.
$hey are written below4 7-.1 8 7dHust -.1 6ield of 3egment 3elector
91$3 8 9lear $as,83witched 6lag in 9-O
17- 8 1oad 7ccess -ights (yte
1?2$/1I2$ 8 1oad ?lobal/Interrupt 2escriptor $able
-egister
112$ 8 1oad 1ocal 2escriptor $able -egister
1M3" 8 1oad Machine 3tatus "ord
1O72711 8 1oad 7ll -egisters
131 8 1oad 3egment 1imit
1$- 8 1oad $as, -egister
3?2$ 8 3tore ?lobal 2escriptor $able -egister
3I2$ 8 3tore Interrupt 2escriptor $able -egister
312$ 8 3tore 1ocal 2escriptor $able -egister
3M3" 8 3tore Machine 3tatus "ord
3$- 8 3tore $as, -egister
=+--/=+-" 8 =erify a 3egment for -eading or
"riting
$'<( /hat are the features of ;<2;:-
Ans( 6eatures of %&3%# are given below4
2J!,&&& transistors
Intel:s first practical 328bit microprocessor
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328bit data bus and memory address
?( of memory
Memory management unit
Multitas,ing
$''( /hat are the features of !entiu+-
Ans( 6eatures of .entium4
.! architecture / %&!%#
Introductory version4 #&M5/ and ##M5/, 11&MI.3 / 1&&M5/, 1!&MI.3
1#@( of cache si/e B%@( I9, %@( 290
?( of memory system, #8bit data bus
+*ecutes up to two instructions at a time BIf they don:t conflictO0
$'.( /rite do*n the addressing +odes of ;<2;: *ith e1a+,les(
Ans( 7ddressing modes of %&3%#4
-egister addressing4 MO= +9E, +2E
Immediate addressing4 MO= +(E, 123!#J%5
2irect addressing4 MO= 9E, 1I3$
-egister indirect addressing4 MO= 71, P+9EQ
(ase8plus8inde* addressing4 MO= P+7EC+(EQ, 91
-egister relative addressing4 MO= 7E, P+9ECQ
(ase relative8plus8inde* addressing4 MO= +7E, 7--7; P+(EC+9EQ
3caled8inde* addressing4 MO= +2E, P+7ECG+(EQ
$'2( Dra* the internal architecture of ;<2;:(
Ans(
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$'3( /hat are the co+,arisons )et*een ;<;:A ;<.;:A ;<2;:A !entiu+-
7ns.
;<;: ;<.;: ;<2;: !entiu+
Introduced J% %2 %! I!
7loc9 S,eed !<1& M5/ #812M5/ 1#833M5/ 1!&82&& M5/
Bus *idth 1# bits 1# bits 32 bits # bits
No(of transistor 2I&&& 13&&& 2J!&&& !.! million
Addressa)le
?e+ory
1 M( 1# megabytes gigabytes # gigabytes
"irtual +e+ory R 1 gigabyte # terabytes # terabytes
$'3( Dra* the functional )loc9 diagra+ of !entiu+ ,ro(
Ans(
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.-+.7-+2 (; < =7>++$ 3I>?5, .7-=++> @)M7-