Philips Semiconductors Product Specification

PowerMOS transistor BUK556-60H

Logic level FET
GENERAL DESCRIPTION QUICK REFERENCE DATA
N-channel enhancement mode logic SYMBOL PARAMETER MAX. UNIT
level field-effect power transistor in a
plastic envelope. V
DS
Drain-source voltage 60 V
The device is intended for use in I
D
Drain current (DC) 60 A
automotive and general purpose P
tot
Total power dissipation 150 W
switching applications. T
j
Junction temperature 175 C
R
DS(ON)
Drain-source on-state 22 m
resistance; V
GS
= 5 V
PINNING - TO220AB PIN CONFIGURATION SYMBOL
PIN DESCRIPTION
1 gate
2 drain
3 source
tab drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DS
Drain-source voltage - - 60 V
V
DGR
Drain-gate voltage R
GS
= 20 k - 60 V
V
GS
Gate-source voltage - - 15 V
I
D
Drain current (DC) T
mb
= 25 C - 60 A
I
D
Drain current (DC) T
mb
= 100 C - 44 A
I
DM
Drain current (pulse peak T
mb
= 25 C - 240 A
value)
P
tot
Total power dissipation T
mb
= 25 C - 150 W
T
stg
Storage temperature - - 55 175 C
T
j
Junction Temperature - - 175 C
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
R
th j-mb
From junction to mounting base - - 1.0 K/W
R
th j-a
From junction to ambient - 60 - K/W
1 2 3
tab
d
g
s
October 1993 1 Rev 1.000
Philips Semiconductors Product Specification
PowerMOS transistor BUK556-60H
Logic level FET
STATIC CHARACTERISTICS
T
j
= 25 C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
(BR)DSS
Drain-source breakdown V
GS
= 0 V; I
D
= 0.25 mA 60 - - V
voltage
V
GS(TO)
Gate threshold voltage V
DS
= V
GS
; I
D
= 1 mA 1.0 1.5 2.0 V
I
DSS
Zero gate voltage drain current V
DS
= 60 V; V
GS
= 0 V; - 1 10 A
I
DSS
Zero gate voltage drain current V
DS
= 60 V; V
GS
= 0 V; T
j
= 125 C - 0.1 1.0 mA
I
GSS
Gate source leakage current V
GS
= 15 V; V
DS
= 0 V - 10 100 nA
R
DS(ON)
Drain-source on-state V
GS
= 5 V; I
D
= 25 A - 18 22 m
resistance
DYNAMIC CHARACTERISTICS
T
j
= 25 C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
g
fs
Forward transconductance V
DS
= 25 V; I
D
= 25 A 17 30 - S
C
iss
Input capacitance V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz - 2200 2800 pF
C
oss
Output capacitance - 700 1000 pF
C
rss
Feedback capacitance - 280 400 pF
t
d on
Turn-on delay time V
DD
= 30 V; I
D
= 3 A; - 40 50 ns
t
r
Turn-on rise time V
GS
= 5 V; R
GS
= 50 ; - 150 250 ns
t
d off
Turn-off delay time R
gen
= 50 - 350 450 ns
t
f
Turn-off fall time - 190 250 ns
L
d
internal drain inductance Measured from contact screw on - 5 - nH
tab to centre of die
L
d
internal drain inductance Measured from drain lead 6 mm - 5 - nH
from package to centre of die
L
s
internal source inductance Measured from source lead 6 mm - 12.5 - nH
from package to source bond pad
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= 25 C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
I
DR
Continuous reverse drain - - - 60 A
current
I
DRM
Pulsed reverse drain current - - - 240 A
V
SD
Diode forward voltage I
F
= 50 A; V
GS
= 0 V - 1.1 2.0 V
t
rr
Reverse recovery time I
F
= 50 A; -dI
F
/dt = 100 A/s; - 80 - ns
Q
rr
Reverse recovery charge V
GS
= -10 V; V
R
= 30 V - 0.4 - C
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
W
DSS
Drain-source non-repetitive I
D
= 50 A; V
DD
25 V; - - 150 mJ
unclamped inductive turn-off V
GS
= 5 V; R
GS
= 50 ; T
mb
= 25 C
energy
October 1993 2 Rev 1.000
Philips Semiconductors Product Specification
PowerMOS transistor BUK556-60H
Logic level FET
Fig.1. Normalised power dissipation.
PD% = 100P
D
/P
D 25 C
= f(T
mb
)
Fig.2. Normalised continuous drain current.
ID% = 100I
D
/I
D 25 C
= f(T
mb
); conditions: V
GS
10 V
Fig.3. Safe operating area. T
mb
= 25 C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Fig.4. Transient thermal impedance.
Z
th j-mb
= f(t); parameter D = t
p
/T
Fig.5. Typical output characteristics, T
j
= 25 C.
I
D
= f(V
DS
); parameter V
GS
Fig.6. Typical on-state resistance, T
j
= 25 C.
R
DS(ON)
= f(I
D
); parameter V
GS
0 20 40 60 80 100 120 140 160 180
Tmb / C
PD% Normalised Power Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
1E-05 1E-03 1E-01 1E+01
t / s
Zth j-mb / (K/W)
10
1
0.1
0.01
0.001
0
0.5
0.2
0.1
0.05
0.02
BUKx56-lv
D =
D =
tp
tp
T
T
P
t
D
0 20 40 60 80 100 120 140 160 180
Tmb / C
ID / IDmax % Normalised Current Derating
120
100
80
60
40
20
0
0 2 4 6 8 10 12
VDS / V
ID / A BUK5y6-60A
150
100
50
0
2.5
3
3.5
4
4.5
5
6
7 10
8
VGS / V =
1 100
VDS / V
ID / A
1000
100
10
1
BUK556-60H
10
tp = 10 us
100 us
1 ms
10 ms
100 ms
DC
R
D
S
(
O
N
)
=
V
D
S
/ ID
0 20 40 60 80 100 120 140
ID / A
RDS(ON) / Ohm BUK5y6-60A
0.1
0.08
0.06
0.04
0.02
0
6
3 3.5 4 4.5 5
7
VGS / V = 10
October 1993 3 Rev 1.000
Philips Semiconductors Product Specification
PowerMOS transistor BUK556-60H
Logic level FET
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
) ; conditions: V
DS
= 25 V; parameter T
j
Fig.8. Typical transconductance, T
j
= 25 C.
g
fs
= f(I
D
); conditions: V
DS
= 15 V
Fig.9. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 C
= f(T
j
); I
D
= 25 A; V
GS
= 5 V
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 C; V
DS
= V
GS
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
0 2 4 6 8 10
VGS / V
ID / A BUK5y6-60A
150
100
50
0
Tj / C = 25
150
-60 -20 20 60 100 140 180
Tj / C
VGS(TO) / V
2
1
0
max.
typ.
min.
0 20 40 60 80 100
ID / A
gfs / S BUK5y6-60A
40
35
30
25
20
15
10
5
0
0 0.4 0.8 1.2 1.6 2 2.4
VGS / V
ID / A
1E-01
1E-02
1E-03
1E-04
1E-05
1E-06
SUB-THRESHOLD CONDUCTION
2 % typ 98 %
-60 -20 20 60 100 140 180
Tj / C
Normalised RDS(ON) = f(Tj)
2.0
1.5
1.0
0.5
0
a
0 20 40
VDS / V
C / pF
Ciss
Coss
Crss
10
100
1000
10000
BUK5y6-60A
October 1993 4 Rev 1.000
Philips Semiconductors Product Specification
PowerMOS transistor BUK556-60H
Logic level FET
Fig.13. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
); conditions: I
D
= 50 A; parameter V
DS
Fig.14. Typical reverse diode current.
I
F
= f(V
SDS
); conditions: V
GS
= 0 V; parameter T
j
Fig.15. Normalised avalanche energy rating.
W
DSS
% = f(T
mb
); conditions: I
D
= 50 A
Fig.16. Avalanche energy test circuit.
0 20 40 60 80
QG / nC
VGS / V BUK5y6-60A
10
9
8
7
6
5
4
3
2
1
0
VDS / V =12
48
20 40 60 80 100 120 140 160 180
Tmb / C
120
110
100
90
80
70
60
50
40
30
20
10
0
WDSS%
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
VSDS / V
IF / A BUK5y6-60A
200
150
100
50
0
Tj / C = 25
150
L
T.U.T.
VDD
RGS
R 01
VDS
-ID/100
+
-
shunt
VGS
0
W
DSS
= 0.5 LI
D
2
BV
DSS
/(BV
DSS
V
DD
)
October 1993 5 Rev 1.000
Philips Semiconductors Product Specification
PowerMOS transistor BUK556-60H
Logic level FET
MECHANICAL DATA
Dimensions in mm
Net Mass: 2 g
Fig.17. TO220AB; pin 2 connected to mounting base.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Refer to mounting instructions for TO220 envelopes.
3. Epoxy meets UL94 V0 at 1/8".
10,3
max
3,7
2,8
3,0
3,0 max
not tinned
1,3
max
(2x)
1 2 3
2,4
0,6
4,5
max
5,9
min
15,8
max
1,3
2,54 2,54
0,9 max (3x)
13,5
min
October 1993 6 Rev 1.000
Philips Semiconductors Product Specification
PowerMOS transistor BUK556-60H
Logic level FET
DEFINITIONS
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1996
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
October 1993 7 Rev 1.000
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