UNIT 5

Serial Data Transmission Vs Parallel Data Transmission

Serial Data Transmission Formats can be classified as
Asynchronous Data Transmission:
In Asynchronous Mode Serial data communication different clock sources are used for
Transmitter and Receiver.In this mode data is Transmitted with Start and Stop bits.Transmission
begins with Start bit,followed by data bit and Stop bit.For Error Checking Purpose Parity bit may
also be included just before Stop bit.


2. Synchronous Data Transmission: In Synchronous Mode Serial data communication
Transmitter and Receiver are Synchronised.It Uses as a Common Clock Signal to Synchronize
receiver and Transmitter.





Serial Transmission modes can be classified as
1. Simplex
2. Half Duplex
3. Full Duplex

1) Simplex mode
Data is transmitted only in one direction over a single communication channel. For example, the
processor may transmit data for a CRT display unit in this mode.
Eg: Computer to Printer.

2) Half Duplex mode
In this mode, data transmission may take place in either direction, but at a time data may be
transmitted only in one direction. A computer may communicate with a terminal in this mode. It
is not possible to transmit data from the computer to the terminal and terminal to computer
simultaneously.
Eg: Walkie Talkie.

3)Full Duplex Mode:
In this mode data transfer in both directions is possible Simultaneously.
Eg:Telephone lines.





Need for 8251:
To implement Serial Communication in Microprocessor based System we need basically two
Devices
1)Parallel to Serial Converter 2)Serial to Parallel Converter.
To Transmit 8 bit parallel data it is necessary to convert 8 bit parallel data into 8 bit Serial
data.This Canbe done by using Parallel to Serial Converter. Similarly at the reception these
Serial bits must be converted into 8 bit parallel data.
The Devices which are designed for this Purpose are
1)USART(Universal Synchronous Asynchronous Receiver Transmitter)
2)UART(Univeral Asynchronous Receiver Transmitter)

USART-8251(Universal Synchronous Asynchronous Receiver Transmitter)
The 8251 is a USART (Universal Synchronous Asynchronous Receiver Transmitter) for serial
data communication.

INTEL introduced a 28-pin DIP chip called the programmable communication interface.
This 8251 receives parallel data from the CPU and transmits serial data after conversion.
Similarly it also receives serial data from outside devices and transmits parallel data into the
CPU after conversion.

Block diagram of 8251
The Block diagram of 8251 is shown below .The USART chip consists of four important
sections .They are
1) Data Bus Buffer
2) Read / Write Control Logic section
3) Transmitter Section
4) Receiver Section
5) Modem Control Section


.
1)Data Bus Buffer:-
This is a Tri-state,Bi directional,8 bit buffer is used to interface 8251 to System data bus.
It consists of three registers, one 8-bit data register, one 16-bit control word register and one 8-bit
status word register.
2)Read/Write Control Logic section :
The Read/Write control logic accepts signals from RD, WR, CLK, C/D, CS and RESET pins of the
system and generates the necessary signals for controlling the device operation.
The active low signals RD, WR, CS and C/D (Low) are used for read/write operations with these
three registers.
When C/D bar is high, the control register is selected for writing control word or reading status
word. When C/D bar is low, the data buffer is selected for read/write operation.
When the reset is high, it forces 8251A into the idle mode. The clock input is necessary for
8251A for communication with CPU and this clock does not control either the serial transmission
or the reception rate.
3) Transmitter section:
The transmitter section accepts parallel data from CPU and converts them into serial data.
This section is double buffered, i.e., it has a buffer register to hold an 8-bit parallel data and
another register called output register to convert the parallel data into serial bits.
When output register is empty, the data is transferred from buffer to output register. Now the
processor can again load another data in buffer register. If buffer register is empty, then TxRDY
is goes to high. If output register is empty then TxEMPTY goes to high.
The clock signal, TxC (low) controls the rate at which the bits are transmitted by the USART. The
clock frequency can be 1, 16 or 64 times the baud rate.
4) Receiver Section:
The receiver section accepts serial data and convert them into parallel data
This receiver section is also double buffered with two registers. i.e., it has an input register to
receive serial data and convert to parallel, and a buffer register to hold the parallel data.
When the RxD line goes low, the control logic assumes it as a START bit, waits for half a bit time
and samples the line again. If the line is still low, then the input register accepts the following
bits, forms a character and loads it into the buffer register. The CPU reads the parallel data from
the buffer register. When the input register loads a parallel data to buffer register, the RxRDY
line goes high.
The clock signal RxC (low) controls the rate at which bits are received by the USART.
During asynchronous mode, the signal SYNDET/BRKDET will indicate the break in the data
transmission. During synchronous mode, the signal SYNDET/BRKDET will indicate the reception
of synchronous character.
5)MODEM Control Section:
The MODEM control unit allows to interface a MODEM to 8251A and to establish data
communication through MODEM over telephone lines.
This unit takes care of handshake signals for MODEM interface.
The Modem sends certain hand shake signals for proper communication between two devices.
The DTR and RTS are the are the hand shake signals sent out by the 8251 to Modem and they
are activated by using command instruction register.
The DSR and CTS are the hand shake signals sent by the Modem to 8251.
Pin Diagram of 8251
The 8251 is a 28 pin DIP chip which works at 5 volts DC. The Pin diagram of 8251 is shown below.

D0 D7 : This is an 8-bit data bus used to read or write status, command word or data from or to
the 8251A.
C / D : (Control Word/Data): This input pin, together with RD and WR inputs,informs the
8251A that the word on the data bus is either a data or control word/status information.
If this pin is 1, control / status is on the bus,
If the pin is 0, data is on the bus.
RD : A low on this input allows the CPU to read data or Status Bytes from 8251.
WR : A low on this input allows the CPU to write data or Command word to the 8251.


CLK : This input is used to generate internal device timings and is normally connected to clock
generator output. This input frequency should be at least 30 times greater than the receiver or
transmitter data bit transfer rate.
RESET : A high on this input forces the 8251A into an idle state. The device will remain idle till
this input signal again goes low and a new set of control word is written into it.
CS: A low on this input allows communication between CPU and 8251.

Receiver Signals:-
RXC (Receiver Clock Input) : This receiver clock input pin controls the rate at which the
character is to be received.
RXD (Receive Data Input) : This input pin of 8251A receives a composite stream of the data to
be received by 8251 A.
RXRDY (Receiver Ready Output) : This output indicates that the 8251A contains a character
to be read by the CPU.

Transmitter Signals:-
TXE- Transmitter Empty: The TXE signal can be used to indicate the end of a transmission
mode.
TXD (Transmitted Data Output) : This output pin carries serial stream of the transmitted data
bits along with other information like start bit, stop bits and parity bit, etc.
TXRDY - Transmitter Ready : This output signal indicates to the CPU that the internal circuit
of the transmitter is ready to accept a new character for transmission from the CPU.


Modem Control Signals:-
DSR (Data Set Ready) : This input Signal is normally used to test modem Conditions Such as
Data Set Ready.
DTR (Data Terminal Ready) : This output Signal is used to indicate that the device is ready to
accept data.
RTS - Request to Send Data : This output signal is used to begin transmission.

























Operating Modes of 8251
1. Asynchronous mode
2. Synchronous mode
1. Asynchronous mode
Asynchronous Mode (Transmission)
When a data character is sent to 8251A by the CPU, it adds start bits prior to the serial data bits,
followed by optional parity bit and stop bits using the asynchronous mode instruction control
word format. This sequence is then transmitted using TXD output pin on the falling edge of
TXC.
Asynchronous Mode (Receive)
A falling edge on RXD input line marks a start bit. The receiver requires only one stop bit to
mark end of the data bit string, regardless of the stop bit programmed at the transmitting end.
The 8-bit character is then loaded into the into parallel I/O buffer of 8251. RXRDY pin is raised
high to indicate to the CPU that a character is ready for it. If the previous character has not been
read by the CPU, the new character replaces it, and the overrun flag is set indicating that the
previous character is lost.




Fig : Mode Instruction Format Asynchronous Mode




Fig. Asynchronous Mode Transmit and Receive Formats






2) Synchronous mode
Synchronous Mode (Transmission)
The TXD output is high until the CPU sends a character to 8251 which usually is a SYNC
character. When CTS line goes low, the first character is serially transmitted out. Characters are
shifted out on the falling edge of TXC .Data is shifted out at the same rate as TXC , over TXD
output line. If the CPU buffer becomes empty, the SYNC character or characters are inserted in
the data stream over TXD output.
Synchronous Mode (Receiver)
In this mode, the character synchronization can be achieved internally or externally. The data on
RXD pin is sampled on rising edge of the RXC. The content of the receiver buffer is compared
with the first SYNC character at every edge until it matches. If 8251 is programmed for two
SYNC characters, the subsequent received character is also checked. When the characters match,
the hunting stops.
The SYNDET pin set high and is reset automatically by a status read operation. In the external
SYNC mode, the synchronization is achieved by applying a high level on the SYNDET input pin
that forces 8251 out of HUNT mode. The high level can be removed after one RXC cycle. The
parity and overrun error both are checked in the same way as in asynchronous mode.


Fig. Synchronous Mode Instruction Format



Synchronous mode Transmit and Receive data format

Fig. 8.6 Data Formats of Synchronous Mode









Command Instruction Definition
The command instruction controls the actual operations of the selected format like enable
transmit/receive, error reset and modem control. A reset operation returns 8251 back to mode
instruction format.

Fig. 8.7 Command Instruction Format
Status Read Definition
This definition is used by the CPU to read the status of the active 8251 to confirm if any error
condition or other conditions like the requirement of processor service has been detected during
the operation.

Fig. Status Read Instruction Format

RS 232 Serial Communication Standards
In serial I/O, data can be transmitted as either current or voltage. When data is transmitted as
voltage, the commonly used standard is known as RS-232C. RS-232 standard proposes a
maximum of 25 signals for the bus used for serial data transfer.In practice, the first 9-signals are
sufficient for most of the serial data transmission scheme. Hence, the RS-232C bus signals are
transmitted on a D-type 9-pin connector.When all the 25 signals are used, then RS-232C serial
bus is terminated on a 25-pin connector.

Commonly used voltage levels are, +12V (Logic high) and -12V (Logic low)
The RS-232C signal levels are not compatible with TTL logic levels.
For interfacing TTL devices, level converters or RS-232C line drivers are employed.
The popularly used level converters are :
1. MC 1488 - TTL to RS-232C level converter.
2. MC 1489 RS-232C to TTL level converter.

TTL to RS-232C Conversion RS-232C to TTL signal conversion
IEEE-488It is a short-range digital communications bus specification. It was created in the late
1960s for use with automated test equipment, and is still in use for that purpose. IEEE-488 is
commonly called GPIB (General Purpose Interface Bus)..


IEEE-488

Pin out

Female IEEE-488 connector