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5. How to Create a Pulse Width Modulation ( Pwm ) in a
erilog Module to !un a Motor " #er$o
How to Create a Pulse Width Modulation ( Pwm ) in a
Verilog Module to Run a Motor / Servo
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) PWM (an also 'e used to (ontrol light intensit&
) pulse width modulation is one wa& to (ontrol the rotation or
position o* an ele(tri( motor or ser$o.
+sing erilog H,L- . will show how eas& it is to use (ounters in
order to (reate a pwm. Ha$e a /uestion0 1et an answer *rom
online te(h support now2
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How to Ma3e a Pulse Width Modulator
4utorial *or erilog H,L
hings !ou"ll #eed
5ilin6 .#7
8P1)
#er$o " motor
$nstru%tions
1.
o 1
#o how does a pwm wor30
Ha$ing a periodi( re(tangular signal- we (hange the
dut& (&(le ( modulate ) to 'e smaller or 'igger and
there*ore (ontrol our de$i(e.
Wh& use a PWM0
.t is a simple digital to analog (on$ersion te(hni/ue
that does not re/uire an ),C.
o 2
93- so lets thin3 what inputs- outputs- registers and
(ounters we will need and whi(h design we want to
(reate.
. want to use the eight swit(hes on the #partan 8P1)
'oard to (ontrol how m& motor " ser$o mo$es or how
*ast or slow . want it to mo$e.
.nputs: (lo(3- ; swit(hes
9utputs: pwm
!egisters: pwm
Counters: 1< 'it (ounter ( will e6plain wh& 1< 'its
later)
o #ponsored Lin3s
#er$o Motor = Controller
Leading #upplier o* #er$o Motor = Controller-
+L- C#) = C7 Compliant
www.amte(hele(troni(s.(om
o 3
>now what is the (lo(3 speed o* &our 8P1) and what
period &ou would li3e to use.
. ha$e a #partan 8P1) 'oard with a 5?MH@ (lo(3. .
would li3e to re*resh the signal e$er& 1 millise(ond (t).
We appl& the *ollowing (al(ulation to *ind the
wa$e*orm period (p)
p A t B 8P1) (lo(3
.n m& (ase:
p A .??1 se(onds B 5?MH@ A 5????
>nowing m& p is important in order to (al(ulate m&
step dela& (sd):
sd A p " 25< A 1C5
Wh& did . use 25<0 . will 'e using ; swit(hes to
(ontrol m& ser$o " motor- so 2D; A 25<.
o 4
8inall& we want to use our (ounter as our dut& (&(le.
4o (al(ulate how man& 'its (ompose our (ounter we
use:
log2(sd) A how man& 'its is our (ounter
While the (ounter is less than sd ( step dela&)
multiplied '& the swit(hes $alue ( whi(h (an range
*rom ? to 255)- this is our dut& (&(le.
&eatures
H,L sour(e (ode o* a PWM generator (omponent
Con*igura'le dut& (&(le resolution
Con*igura'le num'er o* outputs"phases
Con*igura'le PWM *re/uen(&
Modulation around the (enter o* the pulse
PWM in$erse outputs
$ntrodu%tion
4his details a pulse width modulation (PWM) generator
(omponent *or use in CPL,s and 8P1)s- written in H,L.
4he (omponent outputs PWM signals 'ased on the dut& (&(le
set '& user logi(. 4he (enter o* ea(h pulse o((urs at the PWM
*re/uen(&- and the pulse width $aries around the (enter. .* set to
multiple phases- the (omponent generates one PWM signal *or
ea(h phase- e$enl& spa(ed. 8or e6ample- when set to three
phases- it generates three PWM outputs 12?E outFo*Fphase with
one another. 4he (omponent was designed with Guartus ..-
$ersion 12.1 and tested with Model#imF)ltera 1?.1'. !esour(e
re/uirements depend on the implementation. 8igure 1 illustrates
a t&pi(al e6ample o* the PWM generator integrated into a
s&stem.
&igure '( 76ample .mplementation
heor) o* Operation
4he s&stem (lo(3 di$ided '& the PWM *re/uen(& e/uals the
num'er o* s&stem (lo(3 pulses in one PWM period. Counters
de*ine this PWM period *or ea(h phase. 4here is one (ounter
*or ea(h PWM phase- with their $alues o**set '& the phase.
7a(h (ounter in(rements on ea(h s&stem (lo(3 and (lears on(e it
rea(hes the end o* its period.
4he dut& (&(le determines the points during the period when the
PWM signalHs rising and *alling edges o((ur. 8igure 2
illustrates the 'asi( (on(ept used to determine these positions.
4he signalHs *alling edge happens at I dut& (&(le- and its rising
edge happens at the end o* the period minus I dut& (&(le. 9n(e
the (ounter rea(hes ea(h o* these positions- the PWM signal is
toggled as appropriate. #in(e a hal* dut& (&(le (an ne$er e6(eed
a hal* period- the *alling edge alwa&s o((urs 'e*ore the rising
edge.
&igure +( Wa$e*orm o* a Pulse .nFPhase with the PWM Period
Con*igura,le Parameters
4he PWM generator is (on*igured using *our 17J7!.C
parameters- set in the 7J4.4K. 4a'le 1 lists the parameters.
4he PWM generator does not re/uire a spe(i*i( input (lo(3- so
long as the user sets the sys_clk parameter to the (lo(3
*re/uen(& pro$ided. 4he parameter pwm_freq (orresponds to
the PWM *re/uen(&. 4he bits_resolution determines the
resolution o* the pulse width. 8or e6ample- a $alue o* ;
pro$ides ; 'its o* resolution. 4here*ore- the pulse widthHs
resolution is 2
;
or 25<- so in this (ase- the *inest possi'le pulse
width adLustment is the period (i.e. 1"pwm_freq) di$ided '&
25<. 4he parameter phases sets the num'er o* outputs and their
relation to one another. 4he num'er o* PWM outputs is phases-
and these outputs are 3<?E"phases outFo*Fphase with one
another.
a,le '( 1eneri( Parameters
-eneri%
.ata
)pe
.es%ription
s&sM(l3 integer #&stem (lo(3 *re/uen(& in H@.
pwmM*re/ integer 8re/uen(& o* PWM in H@.
'itsMresolution integer
4he num'er o* 'its o* resolution setting
the dut& (&(le.
phases integer
4he num'er o* output PWMs and
phases.
#in(e the PWM period is de*ined in s&stem (lo(3s as
sys_clk"pwm_freq- this ratio also a**e(ts the dut& (&(le
resolution. ) dut& (&(le resolution is not a(hie$a'le i* it
e6(eeds the num'er o* s&stem (lo(3s in the PWMHs period.
#imilarl&- the a(hie$ed dut& (&(le is su'Le(t to single 'it
rounding errors i* the period is not an integer multiple o* the
resolution.
Port .es%riptions
4a'le 2 des(ri'es the PWM generatorHs ports.
a,le +( Port ,es(riptions
Port
Widt
h
Mod
e
.ata )pe
$nter*a%
e
.es%ription
(l3 1 in standard logi(
user
logi(
#&stem
(lo(3.
resetMn 1 in standard logi(
user
logi(
)s&n(hrono
us a(ti$e
low reset.
ena 1 in standard logi(
user
logi(
?: PWM
(ontinues
outputting
(urrent dut&
(&(le.
1: lat(hes in
the new dut&
(&(le and
immediatel&
adLusts
PWM
outputs the
new $alue.
dut& MB in
standardMlogi(M$e(
tor
user
logi(
Jew dut&
(&(le.
pwmMout JD out standardMlogi(M$e(
tor
load 9utput
PWM
signals. 4he
PWM
modulates
around the
(enter o* the
the pulse.
Port
Widt
h
Mod
e
.ata )pe
$nter*a%
e
.es%ription
4he phases
are e$enl&
spa(ed o$er
the period.
pwmMnMo
ut
JD out
standardMlogi(M$e(
tor
load
.n$erse o*
the PWM
outputs.
Jotes
B M is the dut& (&(leNs spe(i*ied resolution in 'its- set '& the
bits_resolution generi(.
D J is the spe(i*ied num'er o* outputs (and phases)- set '& the
phases generi(.
Controlling the .ut) C)%le
+ser logi( (an (ontrol the dut& (&(le '& lat(hing in new dut&
(&(le $alues on the duty port. 4he PWM generator lat(hes in
$alues on this port on all s&stem (lo(3s when the ena port is set
to O1H. 8igure 3 shows a Model#im simulation (hanging the
dut& (&(le.
&igure /( #imulation o* Changing the ,ut& C&(le
Reset
4he reset_n input port must ha$e a logi( high *or the PWM
generator (omponent to operate. ) low logi( le$el on this port
as&n(hronousl& resets the (omponent. ,uring reset- the
(omponent (lears the period (ounters and sets 'oth the PWM
outputs and PWM in$erse outputs to O?H.
Con%lusion
4his PWM generator is a programma'le logi( (omponent that
produ(es PWM and PWM in$erse outputs. 4he s&stem (lo(3-
PWM *re/uen(&- dut& (&(le resolution- and num'er o* phases
are (on*igura'le. )n inter*a(e to user logi( (ontrols the PWM
dut& (&(le.
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