PREFACE

Subject Name : DIGITAL ELECTRONICS

Subject Code : EC6302
Staff Name

: MR.T.BHARATHRAMAN

Designation

: AP / ECE

Prepared by

Approved by

MRK Institute of Technology

(Approved by AICTE & Affiliated to Anna University)
Kattumannarkoil - 608 301.

LESSON PLAN
Subject Code : EC6302
Subject Name: Digital Electronics
Faculty Name: Mr.T.Bharathraman
Branch
: B.E.-Electronics & Communication
Year /SEM : II / III
Aim:

No. of Hours : Theory - 45

Total

- 45

To enable the student learn the basic methods for the design of digital circuits and provide the
fundamental concepts used in the design of digital systems .

Objectives:
To introduce basic postulates of Boolean algebra and shows the correlation between
Boolean expressions
To introduce the methods for simplifying Boolean expressions
To outline the formal procedures for the analysis and design of combinational circuits
and sequential circuits
To introduce the concept of memories and programmable logic devices.
To illustrate the concept of synchronous and asynchronous sequential circuits
Unit Unit Description
No.
1.
2.

Minimization Techniques
and Logic Gates

Starting
Date

Finishing
Date

No. of Hours

Test Plan.
Periodical
Test I

Combinational circuits

Sequential circuits

Memory devices

Synchronous and
Asynchronous sequential
circuits

Periodical
Test II

Model Exam

Periodical
Test III

TEXT BOOKS
1. M. Morris Mano, Digital Design, 3rd Edition, Prentice Hall of India Pvt. Ltd., 2003 / Pearson
Education (Singapore) Pvt. Ltd., New Delhi, 2003.
2. S. Salivahanan and S. Arivazhagan, Digital Circuits and Design, 3rd Edition., Vikas Publishing
House Pvt. Ltd, New Delhi, 2006
REFERENCES
1. John F.Wakerly, Digital Design, Fourth Edition, Pearson/PHI, 2006
2. John.M Yarbrough, Digital Logic Applications and Design, Thomson Learning, 2002.
3. Charles H.Roth. Fundamentals of Logic Design, Thomson Learning, 2003.
4. Donald P.Leach and Albert Paul Malvino, Digital Principles and Applications, 6 Edition, TMH,
2003.
5. William H. Gothmann, Digital Electronics, 2nd Edition, PHI, 1982.
6. Thomas L. Floyd, Digital Fundamentals, 8th Edition, Pearson Education Inc, NewDelhi, 2003
7. Donald D.Givone, Digital Principles and Design, TMH, 2003.
th

UNIT I- MINIMIZATION TECHNIQUES AND LOGIC GATES

Sl.
No

Description

Reference
Books

Estimated
hours

Mode of
teaching*

Boolean postulates and laws De-Morgans TheoremPrinciple of Duality - Boolean expression

BBP

Minimization of Boolean expressions - Minterm

Maxterm.

BBP

Sum of Products (SOP) Product of Sums (POS)

Karnaugh map Minimization Dont care conditions.

BBP

BBP

BBP

BBP

Digital
Principles
and Design,
TMH,
2003.
Donald
D.Givone,

Quine-McCluskey method of minimization.

Logic Gates: AND, OR, NOT, NAND, NOR.

ExclusiveOR and ExclusiveNOR Implementations

of Logic Functions using gates.

NANDNOR implementations

Multilevel gate implementations

BBP

Multi output gate implementations

BBP

TTL and CMOS Logic and their characteristics

Tristate gates.

BBP

8
9

TOTAL

UNIT II- COMBINATIONAL CIRCUITS

Sl.
No

Description

Design procedure Half adder Full Adder Half

subtractor Full subtractor.

Parallel binary adder, parallel binary Subtractor

Fast Adder.

Carry Look Ahead adder Serial Adder/Subtractor.

BCD adder Binary Multiplier Multiplier Binary

Divider.

Multiplexer/ Demultiplexer decoder encoder.

Parity checker parity generators.

Code converters - Magnitude Comparator.

Reference
Books

John.M
Yarbrough,
Digital
Logic
Applications
and Design,
Thomson
Learning,
2002

TOTAL

UNIT III- SEQUENTIAL CIRCUITS

Estimated
hours

Mode of
teaching*

BBP

BBP

BBP

BBP

BBP

BBP

BBP
9

Sl.
No

Description

Reference
Books

Estimated
hours

Mode of
teaching*

Latches, Flip-flops - SR, JK, D, T, and Master

BBP

Slave Characteristic table and equationApplication

table Edge triggering Level Triggering.

BBP

Realization of one flip flop using other flip flops

serial adder/subtractor.

BBP

Asynchronous Ripple or serial counter

Asynchronous Up/Down counter - Synchronous
counters

BBP

BBP

BBP

Circuit implementation - Modulon counter, Registers

shift registers- Universal shift registers Shift
register counters

BBP

Ring counter Shift counters - Sequence generators

BBP

Synchronous Up/Down counters Programmable

counters.

Design of Synchronous counters: state diagram- State

table State minimizationState assignment Excitation table and maps.

Charles
H.Roth.
Fundament
als of Logic
Design,
Thomson
Learning,
2003.

TOTAL

UNIT IV- MEMORY DEVICES

Sl.

Reference

Estimated

Mode of

No

Description

Books

hours

teaching*

Classification of memories ROM - ROM

organization - PROM EPROM

BBP

EEPROM EAPROM, RAM RAM organization

BBP

Write operation Read operation Memory cycle

BBP

Timing wave forms Memory decoding memory

expansion Static RAM Cell- Bipolar RAM cell

BBP

MOSFET RAM cell Dynamic RAM cell

Programmable Logic Devices

BBP

Programmable Logic Array (PLA) - Programmable

Array Logic (PAL) Field Programmable Gate
Arrays (FPGA).

BBP

BBP

John
F.Wakerly,
Digital
Design,
Fourth
Edition,
Pearson/P
HI, 2006

Implementation of combinational logic circuits using

ROM, PLA, PAL.

TOTAL

UNIT V- SYNCHRONOUS AND ASYNCHRONOUS SEQUENTIAL CIRCUITS

Sl.
No

Reference
Books

Description

Estimated
hours

Mode of
teaching*

Synchronous Sequential Circuits: General Model.

BBP

Classification Design Use of Algorithmic State

Machine Analysis of Synchronous Sequential
Circuits.

BBP

BBP

BBP

William H.
Gothmann,
Digital
Electronics,
2nd Edition,
PHI, 1982

Asynchronous Sequential Circuits: Design of

fundamental mode and pulse mode circuits.

Incompletely specified State Machines Problems in

Asynchronous Circuits.

Design of Hazard Free Switching circuits.

BBP

Design of Combinational and Sequential circuits

using VERILOG.

BBP

TOTAL

Sl.No

Unit

No of Hours
as per
syllabus

No of Hours as per
Lesson plan

Deviation

Remarks

NIL

II

NIL

III

IV

SUBJECT STAFF

HOD

Sufficient
class hours
are allocated
for teaching.
Sufficient
class hours
are allocated
for teaching.

NIL

Sufficient
class hours
are allocated
for teaching.

NIL

Sufficient
class hours
are allocated
for teaching.

NIL

Sufficient
class hours
are allocated
for teaching.

PRINCIPAL