Flow DW

Encounter
Design Flow Guide

and Tutorial
Product Version 3.2
September 2003
2003 Cadence Design Systems, Inc. All rights reserved.
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August 29, 2003
Encounter Design Flow Guide and Tutorial
September 2003 3 Product Version 3.2
About This Manual. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Online Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
BuildGates/Physically Knowledgeable Synthesis Commands . . . . . . . . . . . . . . . . . . . 7
Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Conventions Used in This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Design Flow Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Flow Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Tcl Script Examples and Linking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2
Logical Synthesis and Scan Insertion. . . . . . . . . . . . . . . . . . . . . . . . . . 19
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Tcl Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3
Silicon Virtual Prototyping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Contents
Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Tcl Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4
Hierarchical Floorplan Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Tcl Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5
Block Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Tcl Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Timing Closure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6
Top-Level Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Tcl Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Timing Closure Strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
7
Chip Assembly and Sign-Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Tcl Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
8
Chip Finishing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Tcl Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
9
Sub Flows: PKS Physical Optimization, Timing/SI Closure . 71
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
PKS Physical Optimization Sub Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Steps: PKS Physical Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Timing/SI Closure Sub Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Steps: Timing Analysis/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
A
Terminology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
B
List of Tcl Script Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
C
Tcl Scripts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Logical Synthesis and Scan Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Silicon Virtual Prototyping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Hierarchical Floorplanning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Block Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Top-Level Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Chip Assembly / Sign-Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Chip Finishing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Miscellaneous Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
CTS File Script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
D
Timing Closure Strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Preplacement Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Floorplanning/Initial Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Routability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Path Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Useful Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Critical Path Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Example Approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
About This Manual
This manual can be used in two ways:
Basic Flow GuideShows a design flow that highlights the capabilities of the
Encounter product. It describes the tasks needed to complete a hierarchical
design, starting from a gate-level netlist and ending with a file in GDSII stream
mask data format using hierarchy and manual budgeting.
TutorialAnnotated Tcl scripts link directly from the flow steps, providing a tutorial-like
resource for learning the Encounter tool.
Online Use
This manual is designed to be used online (HTML). Text and graphic hyperlinks provide direct
access to relevant information in the Encounter User Guide and Encounter Text
Command Reference. Links to the user guide are from the flow steps; links to the command
reference are from the Tcl scripts.
BuildGates/Physically Knowledgeable Synthesis Commands
In addition to the Encounter commands, Appendix D, Timing Closure Strategies, contains
BuildGates

and Cadence
Physically Knowledgeable Synthesis (BG/PKS) commands.

These commands can usually be distinguished from Encounter commands by the use of the
underscore character (for example, do_optimize). These commands are hyperlinked to the
Command Reference for BuildGates Synthesis and Cadence PKS.
Audience
This manual is written for experienced designers of digital integrated circuits. Such designers
must be familiar with design planning, placement and routing, block implementation, chip
assembly, and design verification. Designers must also have a solid understanding of UNIX
and Tcl/Tk programming.
About This Manual
Chapter Summary
This manual is organized into the following chapters and appendixes:
Chapter 1, Introduction
Introduction to the document.
Chapter 2, Logical Synthesis and Scan Insertion
Synthesize the design and insert scan chains. Can be performed with BuildGates/PKS
or Design Compiler.
Chapter 3, Silicon Virtual Prototyping
Determine the feasibility of the netlist, floorplan, and constraints.
Chapter 4, Hierarchical Floorplan Generation
Defines the top-level floorplan and blocks within that floorplan that you implement
separately.
Chapter 5, Block Implementation
Creates physical implementations of the blocks you defined when you generated the
hierarchical floorplan.
Chapter 6, Top-Level Implementation
Run placement and in-place optimization, and route the design at the top-level you
defined in hierarchical floorplanning.
Chapter 7, Chip Assembly and Sign-Off
Flatten the design and perform final analysis.
Chapter 8, Chip Finishing
Create physical layouts of the data you have created, perform final verification, and
prepare the design for tapeout.
Chapter 9, Sub Flows: PKS Physical Optimization, Timing/SI Closure
Description of sub flows.
Appendix A, Terminology
Terms used in the Encounter flow.
Appendix B, List of Tcl Script Examples
About This Manual
List of all Tcl script examples.
Appendix C, Tcl Scripts
Tcl script examples relating to flow procedures.
Appendix D, Timing Closure Strategies
Possible solutions for timing closure issues.
Conventions Used in This Manual
This section describes the typographic and syntax conventions used in this manual.
text Indicates text that you must type exactly as shown. For
example:
analyze_connectivity -analyze all
text Indicates information for which you must substitute a name
or value.
In the following example, you must substitute the name of
a specific file for configfile:
wroute filename configfile
text Indicates the following:
Text found in the graphical user interface (GUI),
including form names, button labels, and field names
Terms that are new to the manual, are the subject of
discussion, or need special emphasis
Titles of manuals
[ ] Indicates optional arguments.
In the following example, you can specify none, one, or
both of the bracketed arguments:
command [-arg1] [arg2 value]
About This Manual
[ | ] Indicates an optional choice from a mutually exclusive list.
In the following example, you can specify any of the
arguments or none of the arguments, but you cannot
specify more than one:
command [arg1 | arg2 | arg3 | arg4]
{ | } Indicates a required choice from a mutually exclusive list.
In the following example, you must specify one, and only
one, of the arguments:
command {arg1 | arg2 | arg3}
{ } Indicates curly braces that must be entered with the
command syntax.
In the following example, you must type the curly braces:
command arg1 {x y}
... Indicates that you can repeat the previous argument.
.
.
.
Indicates an omission in an example of computer output or
input.
Command Subcommand Indicates a command sequence, which shows the order in
which you choose commands and subcommands from the
GUI menu.
In the following example, you choose Floorplan from the
menu, then Power Planning from the submenu, and then
Add Rings from the displayed list:
Floorplan Power Planning Add Rings
This sequence opens the Add Rings form.
About This Manual
Related Documents
For more information about the Encounter family and other related products and tools,
consult the following Cadence documents. You can access these and other documents with
the CDSDoc online documentation system.
Encounter User Guide
Encounter Text Command Reference
Encounter Known Problems and Solutions
Whats New in Encounter
NanoRoute Ultra Reference
PKS User Guide
Command Reference for BuildGates Synthesis and Cadence PKS
The following books are helpful references.
IEEE 1364 Verilog HDL LRM
TCL Reference, Tcl and the Tk Toolkit, John K. Ousterhout, Addison-Wesley
Publishing Company
For a complete list of documents provided with this release, see the CDSDoc library.
Training
In addition to this documentation, courses on the Encounter family of products are available
from Education Services at Cadence.
About This Manual
1
Introduction
This chapter provides an overview of the main flow procedures and also lists the assumptions
you should be aware of before you start this flow.
Overview on page 14
Design Flow Procedures on page 15
Flow Assumptions on page 17
Tcl Script Examples and Linking on page 18
Introduction
Overview
The Encounter platform is a hierarchical physical implementation environment leveraging
the capabilities of First Encounter for floorplanning, feasibility analysis, placement, and clock
tree insertion along with the power of NanoRoute for SI aware routing; CeltIC for SI
analysis; VoltageStorm for IR drop analysis; PKS for logic restructuring and complex
optimizations; and Fire & Ice QX for sign-ff quality extraction.
The Encounter product is comprised of the following tools:
First EncounterVirtual prototyping, feasibility analysis, placement, clock tree
insertion, GDSII generation
NanoRouteFast, high-capacity, signal integrity (SI) and timing-aware routing
CeltICSign-off quality SI analysis
PKSComplex optimizations which require logic restructuring
The following tools interface with Encounter. They require separate licenses.
Fire & Ice QXSign-off quality parasitic extraction
VoltageStormIR drop analysis
Design Entry
Logic Synthesis and
Scan Insertion
(BuildGates)
Hierarchical Virtual Prototyping
and Physical Implementation
Environment
(Encounter)
Chip Finishing
(VCE)
RTL Design Data
Initial Constraints
Optimized Netlist
Mapped Constraints
Final Netlist
Routed Database
Introduction
Design Flow Procedures
The Encounter design flow from RTL to GDSII consists of the following procedures. Each
procedure contains a series of flow steps.
Logical Synthesis and Scan InsertionSynthesize the design and insert scan chains.
Can be performed with Cadence BuildGates/PKS or Synopsys Design Compiler.
For more information, see Chapter 2, Logical Synthesis and Scan Insertion.
Virtual PrototypingDetermine the feasibility of the netlist, floorplan, and constraints.
For more information, see Chapter 3, Silicon Virtual Prototyping.
Hierarchical Floorplan GenerationDefine the top-level floorplan and blocks within that
floorplan that you implement separately.
For more information, see Chapter 4, Hierarchical Floorplan Generation.
Hierarchical Floorplan Generation
Silicon Virtual Prototyping
Top-Level Implementation
Chip Assembly and Sign-Off
Chip Finishing
Logical Synthesis and Scan Insertion
Detailed Block Implementation
Design Entry
Introduction
Block ImplementationCreates physical implementations of the blocks you defined
when you generated the hierarchical floorplan.
For more information, see Chapter 5, Block Implementation.
Top-Level ImplementationRun placement and in-place optimization, and route the
design at the top-level you defined in hierarchical floorplanning.
For more information, see Chapter 6, Top-Level Implementation.
Chip Assembly and Sign-OffFlatten the design and perform final analysis.
For more information, see Chapter 7, Chip Assembly and Sign-Off
Chip FinishingCreate physical layouts of the data you have created, perform final
verification, and prepare the design for tapeout.
For more information, see Chapter 8, Chip Finishing.
TerminologyAppendix of terms used in the flow.
For more information, see Appendix A, Terminology.
Tcl ScriptsTcl scripts relating to flow procedures.
For more information, see Appendix C, Tcl Scripts.
List of Tcl Script ExamplesList of all Tcl script examples.
For more information, see Appendix B, List of Tcl Script Examples.
Timing Closure StrategiesSolutions for timing issues related to the flow.
For more information, see Appendix D, Timing Closure Strategies.
Introduction
Flow Assumptions
1. The following library formats are used:
Timing LibrariesTLF
Timing ConstraintsSDC (Synopsys Design Constraints)
Standard Cell and Macro Library DescriptionsLEF 5.5 unless otherwise indicated
(for example, the Fire & Ice QX interface in Tcl scripts). The cdump format is no
longer required and has been replaced by an all LEF-based flow.
Design Floorplan descriptionsFloorplan file and DEF 5.5 unless otherwise
indicated (for example, the Fire & Ice QX interface in Tcl scripts).
2. The flow assumes that both Fire & Ice QX and VoltageStorm are available for sign-off
quality extraction and IR/EM analysis.
3. The flow as depicted uses channel-based routing only. No over-the-block routing is
shown although the tool can support both abutted-block and feedthrough-based
methodologies.
4. The clocking methodology is based on clock trees. Other methodologies can be
supported with slight modifications to the flow.
Introduction
Tcl Script Examples and Linking
The Tcl script examples in this guide are designed to be used as a tutorial-like resource for
learning the Encounter tool (see Appendix C, Tcl Scripts). The scripts map (link) directly
from the flow steps and are annotated with information and links to the commands in the
Encounter Text Command Reference.
Important
The Tcl scripts are for instructional purposes only. They contain links to the
Encounter Text Command Reference, where more information on using the
Encounter tool is available. These scripts are for reference only and are not meant
to be run standalone.
2
This chapter describes the logical synthesis and scan insertion flow.
Overview on page 20
Flow on page 21
Steps on page 22
Additional Information on page 23
Overview
This flow can be performed with Cadence BuildGates/PKS or Synopsys Design Compiler.
The BG/PKS flow is documented here.
This flow begins with Cadence RTL Compiler (RC) to optimize and map the netlist.
Subsequent passes through this flow can make use of custom wireload models or even
floorplan data if PKS is used for preplacement optimization.
Inputs
RTL design data
Timing constraints
Outputs
Optimized netlist
Mapped constraints
Flow
JTAG/ BIST Generation on page 22
JTAG/BIST Generation
BG/PKS
Third Party
Hierarchical Physi cal Impl ementation
Go to Silicon Virtual Prototyping on page 25
RTL Constraints
Netlist Mapped
Constraints
Floorplan Custom
WLM
Design-For-Test Configuration
Scan Insertion
Preplacement Optimization
Scan DEF Generation*
Netlist Generation
Constraint Generation
1
3
4
5
6
8
7
2
Virtual Prototyping
Hierarchical Floorplanning
Block Implementation
Chip Assembly / Sign-Off
Chip Finishing
Logic Synthesis
Optimize and Map Netlist
RC
* Scan DEF Note
Optmize/Map Netlist
Steps
Important
These steps require the use of the BuildGates/Physically Knowledgeable Synthesis
(BG/PKS) synthesis tool. The detailed flow for logical synthesis and scan insertion
is described in the BG/PKS documentation (see the PKS User Guide).
1. Optimize and Map Netlist
Use RTL Compiler (RC) to optimize and map the netlist. RTL Compiler is a next-
generation synthesis solution for multi-million gate chip design.
2. DFT Configuration
Test synthesis is performed prior to and during optimization. All flip-flops that pass the
DFT rule checks are mapped to their scan-equivalent flops for creation of the scan chain
configuration during optimization.
3. Scan Insertion
When the top-level scan chains are created by scan insertion, the tool will generate a
scan order file (SOF). This file lists the top-level scan chains and depicts how the scan
flops are connected along each of the chains.
4. Preplacement Optimization
Preplacement optimization runs and controls various optimization processes before
place-and-route to produce a desired netlist. Subsequent passes can make use of
custom wireload models or floorplan data if PKS is used for preplacement optimization.
5. Scan DEF Generation
The Scan DEF file (scanDEF) is a sub-section of the Cadence-developed DEF file format
(text based) used to describe the scan chain configuration (architecture) and the set of
reorderable scan chains present in the scan-mapped netlist.
6. JTAG/ BIST Generation
JTAG/BIST generation is performed with third party tools.
7. Netlist Generation
A Verilog netlist is generated.
8. Constraint Generation
The synthesis constraints are applied to the resulting netlist.
Additional Information
Tcl Scripts
See Logical Synthesis and Scan Insertion on page 87.
3
This chapter describes the Silicon Virtual Prototyping flow.
Overview on page 26
Flow on page 27
Steps on page 28
Overview
Silicon Virtual Protyping is used to determine the feasibility of the netlist, floorplan, and
constraints. The design is placed, buffered, routed, extracted, and timed. Clock trees can be
optionally inserted and scan chains can be reordered. Candidate floorplans with fences along
with the timing and clock constraints are carried forward to the Hierarchical Floorplanning
Generation Flow procedure.
Inputs
Netlist
Timing and clock constraints
Additional inputs such as the scan DEF, pad placement information, and vendor floorplan
information are design, flow and vendor specific.
Outputs
Prototype floorplan with fences
Timing and clock constraints
Flow
VP:
JTAG Placement
I/O, P/G Placement | Flip Chip
CTE Timing Analysis*
(no net loading)
Amoeba Placement***
Scan Chain Reordering
Power Planning
(rings and stripes)
IPO
Generate Floorplan File
T-Route / Extract / TA
Power Analysis
From Logical Synthesis and Scan Insertion on page 19
To Hierarchical Floorplan Generation on page 35
Timing/Clk
Constraints
Floorplan
w/Fences
Vendor
Floorplan
I/O
Placement
Netlist*
1
2
3
5
7
9
10
11
8
12
13
14
15
Specify/Refine Floorplan
- Module guides
- Fences (shaping/sizing)
- Blockages (place/routing)
- Assign block locations
- Power plan
Clock Tree Synthesis
6
Timing Issues
Power Issues
Timing Issues
Routability or
Timing Issues
Timing/Clk
Constraints
* Empty modules treated
as blackboxes
** Place top-level modules
and blackboxes (used in
all-block designs)
Clock Issues
VP:
VP:
VP
VP:
VP:
VP:
VP:
Tcl
Tcl
Tcl
Tcl
Tcl
Tcl
Tcl
Tcl
VP:
VP:
VP:
VP:
Tcl
Tcl
Tcl
VP:
VP:
Tcl
Tcl
Tcl
VP
VP
VP
Tcl
Tcl
Tcl
VP
Tcl
Virtual Prototyping
Chip Finishing
Logic Synthesis
*** Depending on design
size, may use FP mode or
clusteringPlace for
increased capacity
Block Placement**
(top modules and blackboxes)
4
Steps
To create a virtual prototype, complete the following steps:
1. Run timing analysis.
Analyze timing with the CTE (Common Timing Engine) using no net loading to determine
whether the initial design meets timing requirements.
User Guide: See Timing: Timing Analysis.
Tcl Script: VP: CTE Timing Analysis (no net loading) on page 88.
2. Place I/O pads, and power and ground pads.
During this step you have the option of reading a file that contains preplaced pad
coordinates or ordering information. With a fixed die size, absolute coordinates can be
used to determine the design size. Power and ground pads must be included in the I/O
file. They are a prerequisite for creating the power plan and determining the amount of
power available to the design.
User Guide: See Place.
Tcl Script: VP: Load Floorplan (Place I/Os) on page 89.
Note: To use the flip chip methodology for placing bumps, see the Flip Chip chapter in
the Encounter User Guide. Flip chip and area I/O are used synonymously in the
Encounter documentation.
3. Place JTAG cells.
Specify and place JTAG cells to be near the I/O cells. These structures stay in place
when you run automatic tools.
Tcl Script: VP: JTAG Placement on page 89.
4. Place blocks.
Place top-level modules and blackboxes.
Note: This step is used in an all-block designs.
5. Specify and refine the floorplan.
Tcl Script: VP: Critical Block Placement on page 90.
Add, delete, or modify the following:
Module guides
Define the initial placement guides for key modules. Guides tell the placer to place
a specific modules cells near the guides location. Alternatively, fences can be used.
User Guide: See Floorplan: Basic Floorplanning.
Tcl Script: VP: Generate Floorplan Guides on page 94.
Fences (shaping/sizing)
Refine the shape and size of fences to align the fences manually, using relative
placement to preserve relationships between fences and keep fenced areas in
specific locations. Correct the aspect ratio and size of the fenced areas.
Alternatively, you can run the automatic block placer.
The goal of this step is to make sure that when blocks are committed later in the
process, you can successfully implement the blocks individually, and the design as
a whole.
User Guide: See Partition.
Tcl Script: VP: Floorplan Refinement with Fences on page 97.
Blockages (place/routing)
Add placement or routing blockages to clear routing channels in congested areas.
For example, if there is heavy congestion around the corner of a block, add a
placement blockage or density screen to relieve the congestion in that area.
Tcl Script: VP: Add Blockages if Necessary on page 95.
Assign block locations
Adjust block placement either manually or via block refinement. You can use the
automatic floorplanning capability to adjust the core size and generate module or
hard macro locations.
Tcl Script: VP: Critical Block Placement on page 90.
Power plan
Define the power rings and power stripes. The power plan can be saved to a file
once a satisfactory initial structure has been obtained. Typically, you do this step
only if you use a predefined power structure in the design. If necessary for the
design, define multiple supply voltage domains (MSV).
User Guide: See Floorplan: Power Planning.
Tcl Scripts:
VP: MSV Definition on page 90
VP: Initial Power Planning on page 91
6. Run Amoeba placement.
Use the Amoeba placer to place cells in the flat design. The placer places cells according
to module guide and fence constraints. Depending on the design size, use floorplan
mode or clustering for increased capacity.
Tcl Script: VP: Amoeba Placement on page 93.
7. Reorder scan chains.
Refine the initial scan chain order based on Amoeba placement results. Although
changes made at this step are not used after you finish the initial floorplan, this step is
still recommended in order to reduce wire length so that a more accurate analysis of
congestion can be done.
Tcl Script: VP: Scan Reorder on page 93.
8. Do power planning.
Comment: Where did the scan chian reorder come from? Defining the power plan
doesn't necessitate a re-placement. Let's review Kevin's scripts to see if
they match the flow as specified. We may have to adjust one or the other.
Define the power rings and power stripes. Refine the initial scan chain order based on
the most recent Amoeba placement results.
Tcl Script: VP: Generate Floorplan Guides on page 94.
9. Run trial routing, extract parasitics, and analyze timing.
Comment: Trial Route
Route the design using the trial router. If the congestion is acceptable, extract
parasitics. If congestion is unacceptable, adjust module guides, re-place critical
blocks and cells, or refine I/O and power and ground pads, as necessary. Examine
the congestion map and congestion report to identify congested areas. After
examining the congestion map, either create a placement blockage or a placement
density screen.
User Guide: See Route: Trial Route.
Tcl Scripts:
VP: TrialRoute on page 95
VP: Add Blockages if Necessary on page 95
Extract parasitic resistance and capacitance (RC) values to calculate delays based
on the wire lengths determined by trial routing.
User Guide: See Timing: RC Extraction.
Tcl Script: VP: Extract Parasitics on page 96.
Analyze timing to find timing violations. At this stage, timing might have violations
however, useful information can still be obtained, such as the magnitude of errors or
which net paths are failing. If the floorplan seems reasonable, run in-place
optimization(IPO). Analyze timing again after IPO to determine how to alter the
floorplan.
Tcl Script: VP: Timing Analysis on page 96.
10. Define clock tree constraints and synthesize the clock tree.
Define clock tree constraints such as insertion delay and slew limits.
User Guide: See Clock.
Synthesize the clock tree. Analyze the clock tree reports to determine if constraints
have been met. As before, netlist changes are not passed forward. The clock tree is
generated to determine area and timing issues with the current floorplan.
Tcl Scripts:
VP: Clock Tree Synthesis on page 98
MI: CTS File on page 177
Route the design using the trial router.
Tcl Script: VP: Trial Route/Extract on page 99.
Perform parasitic extraction to determine net RCs.
Tcl Script: VP: Trial Route/Extract on page 99.
Analyze timing to determine whether the initial design meets timing requirements. If
it does not, then re-place the module guides.
Tcl Script: VP: Timing Analysis on page 99.
12. Run in-place optimization (IPO).
Run IPO, which adds buffer cells, resizes gates and fixes design rule violations. Although
netlist changes made at this stage are not kept, IPO is necessary to assess potential
timing issues with the current floorplan.
User Guide: See Timing: Optimization.
Tcl Script: VP: IPO on page 99.
Route the design using the trial router.
Perform parasitic extraction to determine net RCs.
Tcl Script: VP: Extract/Timing Analysis on page 100.
Analyze timing to determine whether the initial design meets timing requirements.
Tcl Script: VP: Extract/Timing Analysis on page 100.
If timing issues remain after several floorplan iterations, you might need to change
the logical netlist. If no satisfactory floorplans can be found, it may be necessary to
alter the RTL of the design.
14. Analyze power.
Do the complete flat power analysis using native mode. Note that the power plan will be
refined in the next procedure.
User Guide: See Route: SRoute and Power.
Tcl Script: VP: Power Analysis on page 100.
15. Generate floorplan.
Generate and save the floorplan file to pass to Hierarchical Floorplan Generation on
page 35.
User Guide: See Floorplan; Basic Floorplanning.
Tcl Script: VP: Save Floorplan on page 101.
Tcl Scripts
See Silicon Virtual Prototyping on page 88.
4
This chapter describes how to create a hierarchical floorplan.
Overview on page 36
Flow on page 37
Steps on page 38
Overview
This chapter describes how to create a hierarchical floorplan from a flat floorplan based on
the fenced modules. Blocks are generated that are implemented separately, and a top-level
floorplan is created that contains physical and timing block abstractions.
Inputs
Initial netlist
Clock and timing constraints
Fenced floorplan
Outputs
Block abstracts
Block timing models
Top-level netlist
Top-level block placement
Timing constraints for the top level
Block netlist
Block floorplan and placement information
Block budgeted constraints
Boundary voltages
Flow
1
2
3
4
5
6
8
9
7
IPO
Generate LEF Abstracts
GenerateTLF/STAMP
Optimize Pins
Timing Budget
Save Partitions
Commit Partitions
Push Down
Top-Level
Netlist
Floorplan/
Placement
Block LEF(s) Block TLFs
or Stamps
Block Netlist Budgeted
Constraints
Top-Level
Impl ementation
Block Impl ementati on
Amoeba Placement
Power Routing
Power Analysis
Power
Problems
Timing
Problems
Timing
Problems
Congestion
or
Floorplan/
Placement
Boundary
Voltages
Silicon Virtual Protyping
To Block Implementation on page 43
From Silicon Virtual Prototyping on page 25
Initial
Netlist
Clk/Timing
Constraints
Floorplan
w/Fences
Define Physical Partition
To Top-Level Implementation on page 51
HF:
HF:
HF:
HF:
HF:
HF:
HF:
HF:
Tcl
Tcl
Tcl
Tcl
Tcl
Tcl
Tcl
Tcl
HF: Tcl
FR: Tcl
Virtual Prototyping
Chip Finishing
Logic Synthesis
T-Route* / Extract / TA
*Use honorPartitions option
Steps
To create a hierarchical floorplan, complete the following steps:
1. Define the physical partitions.
Change fences to partitions and cut partitions for rectilinear partitions. Place the JTAG
cells.
Tcl Scripts:
HF: Specifify Physical Partitions on page 103
HF: Place JTAG on page 103
Run timing-driven Amoeba placement based on the partitions you defined.
Tcl Script: HF: Amoeba Place on page 103.
Route signals based on partitions and examine the congestion map.
If congestion is acceptable, extract parasitics.
If congestion is unacceptable, refine the floorplan.
Tcl Script: HF: Trial Route/Extract/Timing Analysis on page 104.
Extract parasitic RC values to calculate delays based on the wire lengths
determined by trial routing. Do extraction in detailed mode for budgeting.
Analyze timing to determine whether the floorplan based on the partitions you chose
meets timing constraints.
If timing constraints are not met, go back and refine the floorplan.
If timing constraints are met and congestion is acceptable, commit the
partitions.
4. Run in-place optimization (IPO).
In order to create the best budgets for the blocks, the design is run through IPO to
optimize the timing. The -neverAddPort IPO option should be used to avoid changes to
the block port lists (no new module ports).
User Guide: See Timing: IPO.
Tcl Script: HF: IPO (no new module ports) on page 104.
The design is routed using the -honorPartitions option, then extracted and timed
again.
User Guide: See Route: Trial Route, Timing: RC Extraction, and Timing: Timing
Analysis.
Tcl Script: FR: Trial Route/Extract/Timing Analysis on page 105.
6. Route power.
Route the power then do a power analysis (next step).
User Guide: See SRoute.
Tcl Script: HF: Power Route on page 105.
7. Analyze power.
Power analysis must be done prior to partitioning so that power budgets can be created
for the partitions.
User Guide: See Power.
Tcl Script: HF: Power Analysis on page 106.
8. Commit partitions.
Make a final decision on the partitions to implement as separate blocks. The tool
automatically does the following:
Optimizes pins
For each block, the pin optimization places pins along the edges of the block. The
pin optimizer uses trial routing to determine pin placement.
Creates the timing budget
The tool distributes timing delays, assigning arrival and departure times to each
partition port based on an analysis of the logic inside the partition, the logic it
connects to externally, and the top-level timing constraints for the design.
Pushes power into blocks
The tool pushes stripes and rings down into the blocks. The blocks inherit the power
structure from the top-level floorplan.
Tcl Script: HF: Commit Partitions on page 107.
9. Save partitions.
When the partitions are saved, a directory for each block is created and its netlist,
floorplan, and budgeted constraints are saved in the directory. The cell placements within
the partitions can optionally be saved as well.
A directory is also created for the partitioned top level and the top-level netlist, floorplan,
and updated constraints are saved into it. In addition, a simple timing model and physical
abstract to represent each block is stored in the top-level directory.
Tcl Script: HF: Save Partitions on page 107.
Tcl Scripts
See Hierarchical Floorplanning on page 102.
5
This chapter describes block implementation.
Overview on page 44
Flow on page 45
Steps on page 46
Overview
This chapter describes the creation of the physical implementations of the blocks defined
when the hierarchical floorplan was generated.
Inputs
Block netlist
Budgeted constraints
Floorplan and placement information
Outputs
Verilog netlist
DEF file
LEF File
GDSII file
TLF model
OpenAccess (OA) Database
Power model
Noise model
Flow
BI:
BI:
BI:
BI: Tcl
BI:
BI:
Tcl
BI:
Tcl
Tcl
BI: Amoeba Placement (TD) 1
2
3
4
5
6
8
9
7
10
12
13
14
15
16
17
18
Reorder Scan Chains
IPO (High Effort)
Congestion Optimization
6
IPO (High Effort)
Extraction (FE)
1
Power Grid Analysis
4
Clock Slew (post CTS)
5
Noise Model Creation
2
LEF, DEF, GDS,
OA, Netlist, SPEF
Timing Model Creation
From Hierarchical Floorplan Generation on page 35
GDSII
Timing
Model
OA DB
Block
Netlist
Budgeted
Constraint
Floorplan
Placement
Slew Balancing
6
IPO (pre CTS)
5
Equivalence Check
19
20
Power
Model
LEF
Abstract
Noise
Model
SPEF
DEF Netlist
To Chip Assembly and Sign-Off on page 59
To Top-Level Implementation on page 51
6 SI Prevention
1 QX*
2 CeltIC
3 NanoRoute
4 VoltageStorm*
7 SI Analysis/Repair
5 Optional Steps
Timing/SI Closure Sub Flow
2,7
BI:
BI:
BI:
BI: Tcl
Tcl
Tcl
Tcl
Tcl
Virtual Prototyping
Chip Finishing
Logic Synthesis
TD Routing w/SI Prevention
3,6
11
Di ffi cult
Timing
Tcl
BI: Tcl
BI: Tcl
Tcl
Tcl
BI: Tcl
BI: Tcl
BI: Tcl
BI: Tcl
*License required
PKS Physical Optimization Sub Flow
5
Steps
To implement the blocks you defined when you created a hierarchical floorplan, complete the
following steps:
Read in the blocks netlist, floorplan, and constraints. Check the timing then place the
block using timing-driven Amoeba placement.
Tcl Scripts:
BI: Load Data on page 108
BI: Check Timing on page 109
BI: Detailed Placement on page 110
2. Reorder scan chains.
Reorder the scan chains to relieve routing congestion.
Tcl Script: BI: Reorder Scan Chains on page 110.
3. Run trial routing, extract parasitics, and do timing analysis.
The block is routed, extracted with an extended capacitance table, and timing is
analyzed. For blocks with very difficult timing, it may be necessary to run PKS (physical
synthesis) to optimize and restructure the netlist. See the PKS Physical Optimization Sub
Flow on page 73 for more information.
Analysis.
Tcl Script: BI: Trial Route/Extract/Timing Analysis on page 110.
For additional information on timing closure, see Appendix D, Timing Closure
Strategies.
4. Run in-place optimization.
Run a high-effort IPO.
User Guide: See Timing: Optimization
Tcl Script: BI: Timing Optimization (IPO) on page 111.
5. Run congestion optimization.
Run crosstalk prevention with congestion optimization.
6. Balance slews.
Run crosstalk prevention with slew balancing.
7. Run high-effort in-place optimization (IPO).
8. Synthesize clock trees.
After the logic is optimized, clock trees are created using CTS.
User Guide: See Clock
Tcl Script: BI: Clock Tree Synthesis on page 114.
The block is trial routed, extracted, and the timing is again analyzed, this time with
propagated clocks.
Analysis.
Tcl Script: BI: Fix Setup/Hold (IPO High Effort) on page 116.
11. Do a clock skew.
Do a post clock tree synthesis clock skew analysis.
User Guide: See Clock.
Tcl Script: BI: Fix Setup/Hold (IPO High Effort) on page 116.
The block is trial routed, extracted, and the timing is again analyzed, this time with
propagated clocks.
Analysis.
13. Do routing with SI prevention.
Timing Driven (TD) detailed routing and Signal Integrity (SI) prevention are done using
NanoRoute. NanoRoute is integrated natively into the Encounter executable and runs off
of the same in-memory data structures as Encounter.
Tcl Script: BI: Routing w/SI Prevention on page 120.
14. Run extraction.
Extract the design using detailed extraction.
Tcl Script: BI: Extraction on page 122.
15. Go to the Timing/Signal Integrity Closure Sub Flow.
Important
At this point, timing should be met before proceeding to the Timing/SI Closure sub
flow. See Timing/SI Closure Sub Flow on page 75.
16. Run power grid analysis.
Assuming that the netlist is clean, a power grid analysis is performed by Encounter and
then IR drop analysis is done via VoltageStorm. At this point, the block is essentially
complete and the rest of the steps involve creating various representations of the block
to use during top-level implementation and chip assembly.
Tcl Script: BI: Power Rail Analysis (VoltageStorm) on page 132.
17. Create noise model.
An Echo noise model for the block can be created by running CeltIC from within
Encounter in standalone mode.
Tcl Script: BI: Create Noise Model on page 134.
18. Output LEF, DEF, GDS/OA, netlist, SPEF.
A GDSII representation of the block can be generated directly from Encounter. In
addition, an OpenAccess database (OA DB) can be created for the block. The
OpenAccess database can be read by DFII during chip assembly in place of the GDSII.
A block power model consisting of a power grid model and a power consumption value
can be created to represent the block during top-level power analysis.
Tcl Script: BI: Generate DEF, GDSII, Netlist, OA DB on page 135.
19. Create timing model.
In order to create a characterized TLF blackbox timing model of the block, PKS must be
run with the blocks netlist and SPEF parasitics. The TLF created during partitioning in
the Hierarchical Floorplan Generation was only a simple one-dimensional representation
of the block and contained no load or slew dependent timing information.
Tcl Script: BI: Final Xtalk and Timing Analysis on page 131.
Once all the block models are created, proceed to the Top-Level Implementation on
page 51.
20. Do equivalence check.
Use the the Verplex
tool to perform an equivalence check.

Tcl Scripts
See Block Implementation on page 108.
Timing Closure
For additional information on timing closure, see Appendix D, Timing Closure Strategies.
6
This chapter describes the Top-Level Implementation flow.
Overview on page 52
Flow on page 53
Steps on page 54
Overview
The top-level netlist, floorplan, timing constraints and LEFs, TLFs, power and noise models
for the implemented blocks are read in. The top-level is placed and implementation steps are
performed.
Information on performing timing closure is provided in Appendix D, Timing Closure
Strategies. This appendix includes examples which use BG/PKS commands.
Inputs
Top-level netlist
Floorplan and hard block placements
Top-level constraints
Outputs
Top-level GDSII
Top-level netlist
Top-level SPEF
Top-level DEF
Flow
TI:
TI:
TI:
TI:
TI:
TI:
TI: Tcl
Tcl
Tcl
Tcl
Tcl
Tcl 1
2
3
4
5
6
8
9
7
10
Amoeba Placement (TD)
Scan Chain ReOrdering
Repeater Insertion
Congestion Optimization
6
TD Routing w/SI Prevention
3
Slew Balancing
6
Difficult
Timi ng
From Block Implementation on page 43
From Hierarchical Floorplan Generation on page 35
Go to Chip Assembly and Sign-Off on page 59
Top-Level
Netlist
LEF
Abstracts
Timing
Models
Power
Models
Noise
Models
15
16
17
11
12
13
14
IPO (High Effort)
Extraction (FE)
1
Hier Power Grid Analysis
4
GDS, OA, DEF,
Netlist, SPEF
Equivalence Check
5
**
18
19
20
IPO (High Effort)
GDSII
OA DB
SPEF
DEF Netlist
Constraints Floorplan
6 SI Prevention
1 QX*
2 CeltIC
3 NanoRoute
4 VoltageStorm*
*License required
7 SI Analysis/Repair
5 Optional Steps
TI:
Import Block Model Data
TI:
TI: Tcl
Tcl
Virtual Prototyping
Chip Finishing
Logic Synthesis
5
2,7
IPO (pre CTS)
5
Clock Slew (post CTS)
5
TI:
TI:
TI:
TI:
TI:
TI: Tcl
TI: Tcl
Tcl
Tcl
Tcl
Tcl
Tcl
TI:
Tcl
TI:
Tcl
TI:
Tcl
TI:
Tcl
Steps
To implement the top-level design, complete the following steps:
1. Import the block model data.
Import the block data from the block implementation procedure. Update the configuration
file to point to the timing models and LEFs created for the blocks during implementation,
since the TLF models created buring block implementation are more accurate than the
one-dimensional models created when saving partitions.
Check the timing before running Amoeba placement.
Tcl Scripts:
TI: Load Data on page 137
TI: Check Timing on page 139
Run timing-driven Amoeba placement to place cells, leaving block placement fixed.
Tcl Script: TI: Detailed Placement on page 140.
3. Do scan chain reordering.
The top level is placed scan chains are reordered to relieve routing congestion.
Tcl Script: TI: Reorder Scan Chains on page 140.
4. Do trial routing, extraction, and timing analysis.
The top level is routed, extracted (using Encounter), and the timing is analyzed pre-IPO.
If timing is very tight, it may be necessary to run PKS to optimize timing and restructure
the netlist. See the PKS Physical Optimization Sub Flow on page 73 for more
information.
Tcl Scripts:
TI: Trial Route/Extract/Timing Analysis on page 141
TI: Physical Synthesis on page 141
For additional information on timing closure, see Appendix D, Timing Closure
Strategies.
5. Do in-place optimization.
Tcl Script: TI: Timing Optimization (IPO) on page 141.
6. Insert repeaters.
Repeaters are inserted after crosstalk prevention has been implemented.
7. Do congestion optimization.
Optimize for congestion.
8. Balance slews.
Balance slews then do a high-effort trial routing.
9. Do in-place optimization.
Do an IPO before doing a clock tree synthesis.
Tcl Script: TI: Timing Optimization (IPO) on page 141 .
10. Do clock tree synthesis.
Do a clock tree synthesis post IPO.
Tcl Script: TI: Clock Tree Synthesis on page 145.
The top level is routed, extracted (using Encounter), and the timing is analyzed (post
Clock Tree) . As before, if timing is a problem, it may be necessary to run PKS to optimize
timing and restructure the netlist. See the PKS Physical Optimization Sub Flow on
page 73 for more information.
Tcl Scripts:
TI: Trial Route/Extract/Timing Analysis on page 145
Run high effort IPO with restructuring to fix setup and hold violations.
Tcl Script: TI: Fix Setup/Hold (IPO High Effort) on page 146.
13. Do clock skew.
Do a useful clock skew post CTS.
Tcl Script: TI: Fix Setup/Hold (IPO High Effort) on page 146.
The top level is once again routed, extracted (using Encounter), and the timing is
analyzed (post Clock Tree). As before, if timing is a problem, it may be necessary to run
PKS to optimize timing and restructure the netlist. See the PKS Physical Optimization
Sub Flow on page 73 for more information.
15. Do routing with SI prevention.
Use NanoRoute to do timing-driven routing with signal integrity prevention.
Tcl Script: TI: Routing w/SI Prevention on page 151.
16. Run extraction.
Extract the design using detailed extraction.
Tcl Script: TI: Extraction on page 153.
17. Go to the Timing/Signal Integrity Closure sub flow.
Important
At this point, timing should be met before proceeding to the Timing/SI Closure sub
flow. See Timing/SI Closure Sub Flow on page 75.
18. Do a hierarchical power grid analysis.
A power analysis is performed by Encounter and then IR drop analysis is done via
VoltageStorm.
Tcl Script: TI: Power Rail Analysis (VoltageStorm) on page 163.
Note: VoltageStorm requires an additional license.
19. Output the top-level GDS and/or OA, DEF, netlist, and SPEF.
A GDSII representation can be generated directly from Encounter. In addition, an
OpenAccess (OA) database can be created. The OA database can be read by DFII
during chip assembly in place of the GDSII.
Tcl Script: TI: Generate DEF, GDSII, Netlist, OA DB on page 166.
20. Run an equivalence check.
Use the the Verplex
tool to perform an equivalence check.

Tcl Scripts
See Top-Level Implementation on page 137.
Timing Closure Strategies
The following information relating to step 4 in this flow procedure is provided. The examples
use BG/PKS commands in addition to Encounter commands.
See Appendix D, Timing Closure Strategies.
7
This chapter describes chip assembly and sign-off.
Overview on page 60
Flow on page 61
Steps on page 62
Overview
The Chip Assembly and Sign-Off process consists of bringing the detailed information for the
top level and all of the blocks together for full chip extraction, power, timing, and crosstalk
analysis. Once the sign-off extraction has completed, full-chip power, timing, and crosstalk
can be checked. If the methodology calls for dynamic simulation in the sign-off process, an
SDF file can be produced for NC-Verilog.
Note: Flattening the design is not required. A flat sign-off is needed only if the hierarchical
results from the Top-Level mplementation procedure are suspected of having inaccuracies.
These inaccuracies could be due to not taking into account the coupling capacitance between
over-the-block routes and inside-the-block routes.
Inputs
Top-level DEF
Block-level DEF
Top-level netlist
Timing constraints
Block netlist
Full-chip DEF
Outputs
Netlist
OpenAccess Database
Top-Level GDSII
Block GDSII
SDF for Verilog (optional)
Flow
Stitching SPEF
or Flat SPEF
Full-Chip Timing Analysis
Full-Chip SI Analysis
Top-Level
DEF
Go to Chip Finishing on page 65
Block
DEFs
Top-Level
SPEF
Block
SPEFs
Top-Level
OA
Full-Chip
SPEF
Block
OAs
Block
GDSII
Top-Level
GDSII
Flatten (unpartition)
Full-Chip Power Grid Analysis
Full-Chip Extraction
Full-Chip
SDF
Full-Chip Timing Simulation
From Top-Level Implementation on page 51
From Block Implementation on page 43
1
2
3
5
6
7
4
8
Optional
CA: Tcl
Virtual Prototyping
Chip Finishing
Logic Synthesis
Top-Level
Netlist
Block
Netlist
Timing
Constraints
CA:
CA:
CA:
CA:
CA:
CA:
Tcl
Tcl
Tcl
Tcl
Tcl
Tcl
Steps
To assemble the chip and do sign-off, complete the following steps:
1. Flatten the design.
Flatten the design by merging the top-level and block-level DEF files.
Tcl Script: CA: Flatten Design on page 169.
2. Do full-chip power grid analysis.
Use VoltageStorm to perform a power analysis.
Tcl Script: CA: Flat Power Analysis on page 171.
3. Extract full-chip parasitics (optional).
Use the Fire & Ice QX extractor to do a flat extraction to derive all parasitics including
potential undetected coupling between over-the-block routes and inside-the-block
routes.
Note: QX does not support LEF/DEF 5.4 or 5.5.
Comment: Check with Mohammad and Kevin B.
Tcl Script: CA: Extraction on page 170.
4. Create stitching SPEF or flat SPEF.
Either a 64-bit full chip parasitic extraction can be performed on the flattened design, or
the SPEFs from the top level and the blocks can be stitched together for 64-bit timing
and SI analysis.
5. Run full-chip timing analysis.
Use CTE to perform static timing analysis. Use SignalStorm to calculate sign-off delays.
Either a full chip extraction can be performed on the flattened design or the SPEFs from
the top level and the blocks can be stitched together for Timing and SI analysis.
Tcl Script: CA: Flat Timing Analysis on page 173.
6. Do full-chip signal integrity analysis.
Read (into Encounter) the SPEF file generated by the extractor, the top-level netlist, the
timing constraints file, and the netlists for all the blocks. Use CeltIC to do a full-chip SI
analysis.
User Guide: See SI.
Tcl Script: CA: Flat Xtalk Analysis on page 173.
7. Generate full-chip SDF (optional).
If the methodology calls for dynamic simulation in the signoff process, an SDF file can
be produced to feed NC-Verilog.
8. Full-chip timing simulation (optional).
Do a full-chip timing simulation.
Tcl Script: CA: Flat Timing Analysis on page 173.
Tcl Scripts
See Chip Assembly / Sign-Off on page 168.
8
Chip Finishing
This chapter describes the Chip Finishing flow.
Overview on page 66
Flow on page 67
Steps on page 68
Chip Finishing
Overview
This chapter describes how to obtain physical layouts from the data you have created and
perform final verification.
Inputs
Top-Level GDSII and Block-Level GDSII
Top-Level OA DB and Block-Level OA DB
Full Chip OA DB
Outputs
Masks
Chip Finishing
Flow
Import Std Cell GDSII
1
Layout Finishing / Editing
1
Run Physical Verification
2
Errors? Yes
RTM
GDS
Import Top &
Block GDSII
No
From Chip Assembly and Sign-Off on page 59
Import Top &
Block OA DB
1
2
3
Virtual Prototyping
Chip Finishing
Logic Synthesis
1 NanoRoute
2 Assura
3 First Encounter
Restore OA Design
3
Verify/Extract/TA
3
OA DB
* Modified OA DB can be
read back into Encounter
Modified*
Non-connectivity modifying edits
Chip Finishing
Steps
To finish the chip, complete the following steps:
1. Import the GDSII layouts for the standard cells used in the design into a DFII database,
or import the OA DB(s) or GDSII files for the Top/Block, or import the whole chip (OA DB).
Import the GDSII file you created during top-level implementation. The GDSII for the
standard cells, and either the Top Level and Block GDSII files or the Full Chip OA DB are
assembled in the DFII environment in order to complete the steps necessary to mask out
the chip.
2. Run layout finishing.
Layout finishing steps include adding scribe lines, adding fiducials, adding alignment
marks, adding test fixtures, and so forth. Edits made that dont change the designs
logical connectivity (that is, wire edits and cell movement) can be fed back into Encounter
via OA DB (modified flow on left).
3. Run physical verification.
Once the layout finishing steps are complete, a rigorous Physical Verification is
performed using Assura (in DFII) to look for any design rule violations that may be
present in the design. If any are found, they can be corrected and the layout finishing
steps may need to be redone. Once the design passes error free, then masks can be
generated and the chip fabricated.
Chip Finishing
Tcl Scripts
See Chip Finishing on page 176.
Chip Finishing
9
Sub Flows: PKS Physical Optimization,
Timing/SI Closure
This chapter describes the PKS Physical Optimization and Timing/SI Closure sub flows.
Overview on page 72
PKS Physical Optimization Sub Flow on page 73
Steps: PKS Physical Optimization on page 74
Timing/SI Closure Sub Flow on page 75
Steps: Timing Analysis/SI on page 76
Sub Flows: PKS Physical Optimization, Timing/SI Closure
Overview
This chapter describes two sub-flows which branch from the Block Level Implementation and
Top-Level Implementation flows:
PKS Physical Optimization Sub Flow on page 73
Timing/SI Closure Sub Flow on page 75
Create Path Groups 1
2
3
4
5
7
8
6
9
Pre-Clock Optimization
Useful Skew Optimization
TD Global Route
IPO
TD Global Route
IPO
Fix Setup/Hold
Placement Netlist Constraints
Standalone
PKS
From Block or Top-Level Implementation
FE/PKS Interface
Full PKS
Optimization
Capabilities
To Block or Top-Level Implementation
Placed
DEF
Optimized
Netlist
SPEF
Virtual Prototyping
Chip Finishing
Logic Synthesis
Steps: PKS Physical Optimization
You can use either Encounter or PKS to perform PKS Physical Optimization. The Encounter
flow is described here.
Tcl scripts:
BI: Physical Synthesis on page 111
1. Create the path groups.
Path groups are recommended to isolate specific areas of the design. This helps to
assist in uncovering areas that are prone to closure issues and allows the optimizer to
close timing on the rest of the design.
2. Do a pre-clock optimization.
3. Synthesize the clock tree.
Synthesize the clock tree then analyze the clock tree reports to determine if constraints
have been met.
4. Run a useful skew optimization.
5. Do timing-driven global routing.
6. Do in-place optimization (IPO).
7. Redo global routing.
Run timing-driven global routing again.
8. Redo in-place optimization (IPO).
9. Fix setup/hold times.
TA (Setup/Hold) 1
2
3
4
5
7
6
8
9
10
11
12
13
14
IPO (Setup Violations)
IPO (Hold Violations)
SI Aware ECO Route
2
SI Analysis
3
Fix Crosstalk
Add Filler Cells
Fill Notches
Verify Metal Density
Verify Geom/Conn/Antenna
Extraction
1
Add Metal Fill
SI Analysis
3
TA (Setup/Hold)
From Block or Top-Level Implementation
1 QX
2 NanoRoute
To Block or Top-Level Implementation
Extracted Design (metal fill assumed)
3 CeltIC
Virtual Prototyping
Chip Finishing
Logic Synthesis
Steps: Timing Analysis/SI
Tcl scripts:
BI: Timing/SI Closure Sub Flow on page 128
TI: Timing/SI Closure Flow on page 159
1. Do a timing analysis and fix setup/hold times.
2. Run in-place optimization and fix setup violations.
3. Run in-place optimization and fix hold violations.
4. Do a signal integrity-aware ECO route using NanoRoute.
5. Do a signal integrity analysis.
6. Fix crosstallk.
7. Add filler cells.
8. Add metal fill.
9. Fill notches.
10. Verify metal density.
11. Verify geometry, connectivity, and antenna.
12. Extract the design using Fire & Ice QX. Assume metal fill for the extraction.
13. Do a signal integrity-aware ECO route using NanoRoute.
14. Do a timing analysis and fix setup/hold times.
A
Terminology
This appendix provides an alphabetical listing and description of terminology used in the
Encounter flow.
Table A-1 Encounter Flow Terminology
Term Description
BG/PKS BuildGates and Physically Knowledgeable Synthesis. Integrated
synthesis tools from Cadence.
CTE Common Timing Engine (static timing report mode). Two report
mode are available: CTE and FE. See Timing: Timing Analysis in
the Encounter User Guide.
DEF Data Exchange Format.
Extraction See Parasitics.
Fence A fence in an extension of the module guide concept, with
stronger restrictions on placement. The placer must place the
modules entire design hierarchy within the fence. Cells and sub-
block cells originally placed outside the module guide are placed
inside the modules fence. Cells and sub-block cells from other
modules are not allowed within a modules fence.
Fire & Ice QX Sign-off quality parasitic extraction tool. A separate license is
required for this tool.
First Encounter First Encounter product by Cadence.
JTAG Scan test cells (Joint Test Action Group).
GDSII/GDS Graphical Design System II. The name of the file format is
Stream, but it is commonly referred to as GDSII.
Terminology
IR drop Generic term used to describe the reduction in voltage that
occurs on power supply networks (VDD) or the increase in volt-
age (also known as ground bounce) that occurs on ground net-
works (VSS)..
LEF Library Exchange Format.
.lib Synopsys Liberty Timing Library Format.
Module Guide A module guide represents a logical module structure in the
imported netlist. The purpose of module guides is to constrain
module placement in the floorplan. Module guides constrain the
placer to place the module and sub-module cells in the vicinity of
the module guide. Not all cells or sub-module cells must be
placed within a module guide. The placer allows cells from
different modules to be placed within the module guide, and for
module guides to overlap.
MSV Multiple Supply Voltages. Sometimes referred to as MSMV
(multiple supply multiple voltages).
Nanoroute Integrated routing tool for nanometer designs.
OpenAccess OpenAccess Database format.
Parasitics Refers to capacitance in a circuit and methods of extracting the
capacitance from the physical circuit design. See Fire & Ice QX.
Partition When a fenced module is designated as a partition, it is treated
as a hierarchical sub-block in the design. Committing and saving
partitions does the following:
Assigns pins to the sub-blocks based on trial routing
Creates timing budgets
Creates physical and timing budgets
Pushes the top-level power plan and the floorplan
objects into the modules
PKS Physically Knowledgeable Synthesis.
P/G Power and ground.
SDC Synopsys Design Constraints.
Term Description
Terminology
SDF Standard Delay Format.
(SoC) Encounter Combination of First Encounter with other products.
SPEF Standard Parasitic Exchange Format.
TLF Timing Library Format.
VoltageStorm IR drop analysis tool. A separate license is required for this tool.
(C) WLM (Custom) Wireload Model.
Term Description
Terminology
B
List of Tcl Script Examples
This appendix contains the Tcl script examples grouped by procedure. The following
abbreviations are used for the procedures.
Example B-1 VP: CTE Timing Analysis (no net loading) 88
Example B-2 VP: Load Floorplan (Place I/Os) 89
Example B-3 VP: JTAG Placement 89
Example B-4 VP: Critical Block Placement 90
Example B-5 VP: Auto Floorplan Generation 90
Example B-6 VP: MSV Definition 90
Example B-7 VP: Initial Power Planning 91
Example B-8 VP: Amoeba Placement 93
Example B-9 VP: Scan Reorder 93
Example B-10 VP: Generate Floorplan Guides 94
Example B-11 VP: TrialRoute 95
Example B-12 VP: Add Blockages if Necessary 95
Example B-13 VP: Extract Parasitics 96
Example B-14 VP: Timing Analysis 96
Example B-15 VP: Block Placement Adjustment 96
Example B-16 VP: Floorplan Refinement with Fences 97
Logical Synthesis and Scan Insertion no scripts
Silicon Virtual Prototyping VP
Floorplan Refinement FR
Hierarchical Floorplanning HF
Block Implementation BI
Top-Level Implementation TI
Chip Assembly / Sign-Off CA
Chip Finishing no scripts
Example B-17 VP: Trial Route/Extract 97
Example B-19 VP: Clock Tree Synthesis 98
Example B-20 VP: Trial Route/Extract 99
Example B-22 VP: IPO 99
Example B-23 VP: Extract/Timing Analysis 100
Example B-24 VP: Power Analysis 100
Example B-25 VP: Save Floorplan 101
Example B-26 HF: Load Floorplan from Virtual Prototyping 102
Example B-27 HF: Specifify Physical Partitions 103
Example B-28 HF: Place JTAG 103
Example B-29 HF: Amoeba Place 103
Example B-30 HF: Trial Route/Extract/Timing Analysis 104
Example B-31 HF: IPO (no new module ports) 104
Example B-32 FR: Trial Route/Extract/Timing Analysis 105
Example B-33 HF: Power Route 105
Example B-34 HF: Power Analysis 106
Example B-35 HF: Commit Partitions 107
Example B-36 HF: Save Partitions 107
Example B-37 BI: Load Data 108
Example B-38 BI: Check Timing 109
Example B-39 BI: Detailed Placement 110
Example B-40 BI: Reorder Scan Chains 110
Example B-41 BI: Trial Route/Extract/Timing Analysis 110
Example B-42 BI: Physical Synthesis 111
Example B-43 BI: Timing Optimization (IPO) 111
Example B-44 BI: Clock Tree Synthesis 114
Example B-45 BI: Trial Route/Extract/Timing Analysis 115
Example B-47 BI: Fix Setup/Hold (IPO High Effort) 116
Example B-49 BI: Add Filler Cells 119
Example B-50 BI: Routing w/SI Prevention 120
Example B-51 BI: Insert Metal Fill 121
Example B-52 BI: Verify Connectivity, Geometry and Process Antenna 122
Example B-53 BI: Extraction 122
Example B-54 BI: Post-Route Optimization Sub Flow 122
Example B-55 BI: Timing/SI Closure Sub Flow 128
Example B-56 BI: Insert Metal Fill 130
Example B-57 BI: Verify Connectivity, Geometry and Process Antenna 130
Example B-58 BI: Extraction 130
Example B-59 BI: Final Xtalk and Timing Analysis 131
Example B-60 BI: Power Rail Analysis (VoltageStorm) 132
Example B-61 BI: Create Noise Model 134
Example B-62 BI: Generate DEF, GDSII, Netlist, OA DB 135
Example B-63 TI: Load Data 137
Example B-64 TI: Check Timing 139
Example B-65 TI: Detailed Placement 140
Example B-66 TI: Reorder Scan Chains 140
Example B-67 TI: Trial Route/Extract/Timing Analysis 141
Example B-68 TI: Physical Synthesis 141
Example B-69 TI: Timing Optimization (IPO) 141
Example B-70 TI: Clock Tree Synthesis 145
Example B-71 TI: Trial Route/Extract/Timing Analysis 145
Example B-73 TI: Fix Setup/Hold (IPO High Effort) 146
Example B-75 TI: Add Filler Cells 149
Example B-76 TI: Routing w/CCAR 150
Example B-77 TI: Routing w/SI Prevention 151
Example B-78 TI: Insert Metal Fill 152
Example B-79 TI: Verify Connectivity, Geometry and Process Antenna 153
Example B-80 TI: Extraction 153
Example B-81 TI: Post Route Optimization Flow 153
Example B-82 TI: Timing/SI Closure Flow 159
Example B-83 TI: Insert Metal Fill 161
Example B-84 TI: Verify Connectivity, Geometry and Process Antenna 161
Example B-85 TI: Extraction 161
Example B-86 TI: Final Xtalk and Timing Analysis 162
Example B-87 TI: Power Rail Analysis (VoltageStorm) 163
Example B-88 TI: Generate DEF, GDSII, Netlist, OA DB 166
Example B-89 CA: Flatten Design 169
Example B-90 CA: Extraction 170
Example B-91 CA: Flat Power Analysis 171
Example B-92 CA: Flat Xtalk Analysis 173
Example B-93 CA: Flat Timing Analysis 173
Example B-94 CA: Create OA DB 174
Example B-95 MI: CTS File 177
C
Tcl Scripts
This appendix contains Tcl script examples.
Important
to be run standalone. Additional licenses are required to run some commands.
Overview on page 86
Logical Synthesis and Scan Insertion on page 87
Silicon Virtual Prototyping on page 88
Hierarchical Floorplanning on page 102
Block Implementation on page 108
Top-Level Implementation on page 137
Chip Assembly / Sign-Off on page 168
Chip Finishing on page 176
Miscellaneous Scripts on page 177
Tcl Scripts
Overview
These Tcl scripts are for instructional purposes only. They contain links to the Encounter
Text Command Reference, where more information on using the Encounter tool is
available. These scripts are for reference only and are not meant to be run standalone.
Additional licenses are required to run some commands.
The Tcl script examples use the following abbreviations. A complete list of all Tcl script
examples can be found in Appendix B, List of Tcl Script Examples.
Note: Not all flow steps are scripted.
Logical Synthesis and Scan Insertion on page 87 no scripts
Silicon Virtual Prototyping on page 88 VP
Hierarchical Floorplanning on page 102 HF
Block Implementation on page 108 BI
Top-Level Implementation on page 137 TI
Chip Assembly / Sign-Off on page 168 CA
Chip Finishing on page 176 no scripts
Miscellaneous Scripts on page 177 MI
Tcl Scripts
No Tcl scripts are available for this flow procedure. See Flow on page 21 for the Logical
Synthesis and Scan Insertion flow.
Tcl Scripts
Important
Following is the Virtual Prototyping Tcl script example. See Flow on page 27 for the Virtual
Prototyping flow.
#########################################################
# FLOW SECTION = Silicon Virtual Prototyping
#########################################################
puts "###"
puts "### Set up design specific variables and define user procedures"
puts "###"
source $env(ROOTDIR)/scripts/init.tcl
puts "###"
puts "### Set CTE Mode Reporting"
puts "### To set FE mode comment out or use setFeReport"
puts "###"
setCteReport
puts "###"
puts "### Load Config"
puts "###"
loadConfig ${data}/dtmf_chip.conf
puts "###"puts "### Set Operating Conditions for Min and Max Libraries"
puts "###"
setOpCond -min fast -max slow -minLibrary fast -maxLibrary slow
#########################################################
Example C-1 VP: CTE Timing Analysis (no net loading)
#########################################################
See Flow on page 27 for the Virtual Prototyping flow.
puts "###"
puts "### Zero Net Loading STA"
Tcl Scripts
puts "### No parasitics present, so timing is not constrained by interconnect delay"
puts "###"
setAnalysisMode -setup -async -skew -autoDetectClockTree -sequentialConstProp
reportAnalysisMode
buildTimingGraph -ignoreNetLoad
checkTA -verbose > dtmf_chip_check.rpt
reportTA -format {hpin arc cell delay arrival slew load} -late -max_points 100
-net -summary > dtmf_chip.summary
-net > dtmf_chip.slack
#########################################################
Example C-2 VP: Load Floorplan (Place I/Os)
#########################################################
puts "###"
puts "### Floorplan Init"
puts "###"
floorPlan -d 1488 1488 80 80 80 80
setFlipping f
setDrawMode fplan
puts "###"
puts "### Add IO Fillers"
puts "###"
foreach ioFiller {PFEED50 PFEED35 PFEED20 PFEED10 PFEED5 PFEED2 PFEED1} {
addIoFiller -cell $ioFiller -prefix PAD_
}
puts "###"
puts "### Fill any remaining gaps, overlap allowed"
puts "###"
addIoFiller -cell PFEED01 -prefix PAD_ -fillAnyGap
#########################################################
Example C-3 VP: JTAG Placement
#########################################################
Tcl Scripts
puts "###"
puts "### Place Jtag cells"
puts "###"
#specifyJtag -inst DTMF_INST/TDSP_CORE_INST/PORT_BUS_MACH_INST/i_983
#placeJtag -nrRowLeft 5 -nrRowRight 5 -nrRowTop 5 -nrRowBottom 5
#########################################################
Example C-4 VP: Critical Block Placement
#########################################################
placeInstance "DTMF_INST/PLLCLK_INST" 852.124 706.0870 R0
placeInstance "DTMF_INST/RAM_128x16_TEST_INST/RAM_128x16_INST"
577.8390 1002.5780 R0
placeInstance "DTMF_INST/RAM_256x16_TEST_INST/RAM_256x16_INST"
573.5780 315.003 R180
placeInstance "DTMF_INST/ROM_512x16_0_INST" 803.5890 504.7530 R180
#########################################################
Example C-5 VP: Auto Floorplan Generation
#########################################################
addHaloToBlock 30 30 30 30 -allBlock
cutCoreRow
#markPreplacedBlock 0
#markWeightedNet 0
#getNetWeight 0
#blockPlace -effort m -fixedDie 858.0 858.0 -solutionCount 3 -halo 30.0
-minAR 0.5 -maxAR 2.0 -solFilePrefix autofp
#########################################################
Example C-6 VP: MSV Definition
#########################################################
Tcl Scripts
puts "###"
puts "### Define Multiple-Supplies Voltages (MSV) "
puts "###"
deletePowerDomain
createPowerDomain Analog -timinglibs pllclk -minGaps 0.0 0.0 0.0 0.0 -rsExts 0.0
0.0 0.0 0.0
modifyPowerDomainMember Analog -instances DTMF_INST/PLLCLK_INST
-power (AVDD:VDD) -ground (AVSS:VSS)
modifyPowerDomainMember Analog -instances IOPADS_INST/Pavss0
modifyPowerDomainMember Analog -instances IOPADS_INST/Pavdd0
modifyPowerDomainAttr Analog -box 833.69 687.56 1023.75 1001.15
createPowerDomainCut 938.756 1009.417 1048.258 897.125
#########################################################
Example C-7 VP: Initial Power Planning
#########################################################
puts "###"
puts "### create core ring"
puts "###"
addRing -spacing_bottom 1.5 -width_left 10 -width_bottom 10 -width_top 10
-spacing_top 1.5 -layer_bottom Metal5 -center 1 -width_right 10 -jog_distance 0.33
-offset_bottom 20 -layer_top Metal5 -threshold 0.33 -offset_left 0.33
-spacing_right 1.5 -spacing_left 1.5 -offset_right 20 -offset_top 20
-layer_right Metal6 -nets {VDD VSS} -layer_left Metal6
puts "###"
puts "### create block ring"
puts "###"
deselectAll
selectInst "DTMF_INST/PLLCLK_INST"
addRing -spacing_bottom 1.5 -width_left 2 -width_bottom 2 -width_top 2
-spacing_top 1.5 -layer_bottom Metal3 -width_right 2 -around selected
-jog_distance 0.33 -offset_bottom 1.0 -layer_top Metal3 -threshold 0.33
-offset_left 0.33 -spacing_right 1.5 -spacing_left 1.5 -type block_rings
-offset_right 0.33 -offset_top 1.0 -layer_right Metal2 -nets {VDD VSS}
-layer_left Metal2
deselectAll
Tcl Scripts
puts "###"
puts "### create_stripe"
puts "###"
addStripe -xleft_offset 50 -xright_offset 50 -merge_stripes_value 0.33 \
-width 5.0 -nets {VDD VSS} -set_to_set_distance 200 -layer Metal6 \
-spacing 1.0
puts "###"
puts "### IO Power Pad Hookup with new 3.1 incremental routing ability"
puts "###"
sroute -noStripes -noCorePins -noPadRings -noBlockPins -jogControl {
preferWithChanges differentLayer } -area { 96.1 1296.9075 480.943 916.936 } -nets
{ VSS VDD }
sroute -noStripes -noCorePins -noPadRings -noBlockPins -jogControl {
preferWithChanges differentLayer } -area { 127.7645 536.9645 471.2 159.429 } -nets
{ VSS VDD }
sroute -noStripes -noCorePins -noPadRings -preserveExistingRoutes -noBlockPins -
jogControl { preferWithChanges differentLayer } -nets { VSS VDD }
puts "###"
puts "### Connect Analog Pads to PLLCLK"
puts "###"
editResetUndo
uiSetTool addWire
setEdit -snap_to_pin 1
setEdit -snap_align_to Center
setEdit -nets {AVDD AVSS}
setEdit -layer_horizontal M3
setEdit -layer_vertical M4
setEdit -force_special 1
setEdit -width_horizontal 5.00
setEdit -width_vertical 5.00
setEdit -spacing_horizontal 1.60
setEdit -spacing_vertical 0.28
editAddRoute 1015.347 708.126
editCommitRoute 1017.957 887.254
Tcl Scripts
# setEdit -width_horizontal 29.29
setEdit -layer_horizontal M5
setEdit -nets AVDD
setEdit -nets AVSS
uiSetTool select
puts "###"
puts "### Trim excess power wire"
puts "###"
deselectAll
editSelect -shapes STRIPE
editTrim
deselectAll
#########################################################
Example C-8 VP: Amoeba Placement
#########################################################
puts "###"
puts "### Initial Placement "
puts "### - Use clusteringPlace for increased capacity"
puts "###"
amoebaPlace -fp -ignoreScan
checkPlace
setDrawMode place
#########################################################
Example C-9 VP: Scan Reorder
#########################################################
Tcl Scripts
puts "###"
puts "### Specify scan groups "
puts "###"
set scan_in {{IOPADS_INST/Pscanin1ip/C} {IOPADS_INST/Pscanin2ip/C}}
set scan_out {{IOPADS_INST/Pscanout1op/I} {IOPADS_INST/Pscanout2op/I}}
set n 0
while { $n < [llength $scan_in] } {
specifyScanChain dtmf_chip_chain_$n -start [lindex $scan_in $n]
-stop [lindex scan_out $n]
incr n
}
scanTrace
scanReorder
puts "###"
puts "### Report Scan using DEF out..."
puts "###"
defOut -scanChain dtmf_chip_scan_reorder.def
#########################################################
Example C-10 VP: Generate Floorplan Guides
#########################################################
puts "###"
puts "### Dissolve top hierarchy"
puts "###"
deselectAll
selectModule "DTMF_INST"
Rda_Ungroup
deselectAll
puts "###"
puts "### Generate floorplan guide"
puts "###"
generateGuide -noShrink
createGuide DTMF_INST/TDSP_CORE_INST 316.1200 622.4400 757.9600 1171.8000
createGuide DTMF_INST/RESULTS_CONV_INST 320.0000 325.0000 788.7600 577.0800
setDrawMode fplan
Tcl Scripts
puts "###"
puts "### Re-Placement based on Guides"
puts "###"
amoebaPlace -fp -ignoreScan -timingDriven
checkPlace
setDrawMode place
puts "###"
puts "### Reorder scan chains"
puts "###"
scanReorder
puts "###"
puts "###"
#########################################################
Example C-11 VP: TrialRoute
#########################################################
puts "###"
puts "### Trial Route using fast Prototyping Mode"
puts "###"
trialRoute -floorplanMode
#########################################################
Example C-12 VP: Add Blockages if Necessary
#########################################################
puts "###"
puts "### dump congestion map"
puts "###"
dumpCongestArea congestionmap.txt
puts "###"
puts "### After examining congestion map create either nothing, a placement"
puts "### blockage or a placement density screen. We'll assume nothing.
puts "### If a scrren or blockage is added, need to re-do placement."
puts "###"
# createObstruct - cmd to create placement obstruction
Tcl Scripts
# createDensityArea - cmd to create placement density screen
#########################################################
Example C-13 VP: Extract Parasitics
#########################################################
puts "###"
puts "### Extract RC"
puts "###"
setExtractRCMode -default -assumeMetFill
extractRC
#########################################################
Example C-14 VP: Timing Analysis
#########################################################
puts "###"
puts "### Timing Analysis"
puts "###"
setAnalysisMode -setup -async -skew -autoDetectClockTree
buildTimingGraph
#########################################################
Example C-15 VP: Block Placement Adjustment
#########################################################
puts "###"
puts "### Adjust Blocks if necessary"
puts "###"
Tcl Scripts
#########################################################
Example C-16 VP: Floorplan Refinement with Fences
#########################################################
puts "###"
puts "### Partition assignment & fencing shaping/resizing"
puts "###"
createFence DTMF_INST/TDSP_CORE_INST 316.1200 622.4400 757.9600 1171.8000
createFence DTMF_INST/RESULTS_CONV_INST 320.0000 325.0000 788.7600 577.0800
setDrawMode fplan
puts "###"
puts "### Power Plan Refinement"
puts "###"
# create_ring
# create_stripe
puts "###"
puts "### Re-Placement based on Fences"
puts "###"
amoebaPlace -fp -ignoreScan -timingDriven
checkPlace
setDrawMode place
puts "###"
puts "### Reorder scan chains"
puts "###"
scanReorder
puts "###"
puts "###"
#########################################################
Example C-17 VP: Trial Route/Extract
#########################################################
Tcl Scripts
puts "###"
puts "### Trial Route"
puts "###"
trialRoute -floorplanMode
extractRC
#########################################################
#########################################################
puts "###"
puts "###"
buildTimingGraph
#########################################################
Example C-19 VP: Clock Tree Synthesis
#########################################################
puts "###"
puts "### Can automatically generate a CTS clock specification file"
puts "### using createClockTreeSpec"
puts "###"
# createClockTreeSpec -output ${block}.ctstch -bufFootprint buf -invFootprint inv
puts "###"
puts "### Clock Tree Synthesis"
puts "###"
set ctsFileName ${data}/dtmf_chip.cts
specifyClockTree -clkfile $ctsFileName
checkUnique
ckSynthesis -rguide dtmf_chip.rguide -report dtmf_chip.ctsrpt
saveClockNets -output dtmf_chip.ctsntf
Tcl Scripts
displayClockTree -skew
clearClockDisplay
#########################################################
Example C-20 VP: Trial Route/Extract
#########################################################
puts "###"
puts "### Trial Route/Extract "
puts "###"
trialRoute -lowEffort -guide dtmf_chip.rguide
extractRC
reportClockTree -postRoute -localSkew -report dtmf_chip_post_troute_local.ctsrpt
reportClockTree -postRoute -report dtmf_chip_post_troute.ctsrpt
#########################################################
#########################################################
puts "###"
puts "###"
buildTimingGraph
#########################################################
Example C-22 VP: IPO
#########################################################
Tcl Scripts
puts "###"
puts "### Run IPO to check if based on the Fence placement, timing is not met"
puts "###"
setIPOMode -mediumEffort -fixDRC -addPortAsNeeded -incrTrialRoute
initECO ipo.txt
fixSetupViolation
endECO
#########################################################
Example C-23 VP: Extract/Timing Analysis
#########################################################
extractRC
buildTimingGraph
#########################################################
Example C-24 VP: Power Analysis
#########################################################
puts "###"
puts "### Setup Power Analysis Libraries + Slews to use"
puts "### Default libs are same as current timing libs"
puts "###"
setPowerAnalysisLibrary max
getPowerAnalysisLibrary
puts "###"
puts "### Default Power Analysis Slew is best (ie fastest) slew"
puts "### Faster slew results in higher power consumption"
puts "###"
# setPowerAnalysisSlew worst
getPowerAnalysisSlew
puts "###"
puts "### Power Analysis using Native FE mode for VDD net"
puts "###"
clearPadLocDisplay
Tcl Scripts
autoFetchDCSources VDD
savePadLocation -file dtmf_chip_autofetch_VDD.pp
displayPadLoc -file dtmf_chip_autofetch_VDD.pp
setDrawMode place
updatePower -postCTS -toggleFile ${data}/dtmf_chip.tg -irDropAnalysis average
-pad dtmf_chip_autofetch_VDD.pp -mode floorplan VDD
displayIRDrop VDD -threshold 0.002
clearPowerAnalysisDisplay
puts "###"
puts "### Power Analysis using Native FE mode for VSS net"
puts "###"
clearPadLocDisplay
autoFetchDCSources VSSsavePadLocation -file dtmf_chip_autofetch_VSS.pp
displayPadLoc -file dtmf_chip_autofetch_VSS.pp
setDrawMode place
updatePower -postCTS -toggleFile ${data}/dtmf_chip.tg -irDropAnalysis average
-pad dtmf_chip_autofetch_VSS.pp -mode floorplan VSS
displayIRDrop VSS -threshold 0.002
clearPadLocDisplay
clearPACreatedPGRails
#########################################################
Example C-25 VP: Save Floorplan
#########################################################
puts "###"
puts "### Save Floorplan file to pass to FP refinement stage"
puts "###"
saveFPlan dtmf_chip_floorplan_refine.fp
saveDesign floorplan_refine
exit
Tcl Scripts
Important
Following is the Hierarchical Floorplanning Tcl script example. See Flow on page 37 for the
Hierarchical Floorplanning flow.
#########################################################
# FLOW SECTION = Hierarchical Floorplan Generation
#########################################################
puts "###"
puts "###"
puts "###"
puts "###"
setCteReport
puts "###"
puts "###"
loadConfig ${data}/dtmf_chip.conf
puts "###"
puts "### Set Operating Conditions for Min and Max Libraries"
puts "###"
#########################################################
Example C-26 HF: Load Floorplan from Virtual Prototyping
#########################################################
See Flow on page 37 for the Hierarchical Floorplanning flow.
Tcl Scripts
puts "###"
puts "### Load the floorplan file from the initial Floorplanning stage"
puts "###"
loadFPlan dtmf_chip_floorplan_refine.fp
#########################################################
Example C-27 HF: Specifify Physical Partitions
#########################################################
puts "###"
puts "### Specify Physical partition "
puts "###"
setDrawMode fplan
deleteAllPartitions
createPartition tdsp_core DTMF_INST/TDSP_CORE_INST 560 560 0 0
createPartition results_conv DTMF_INST/RESULTS_CONV_INST 560 560 0 0
puts "###"
puts "### Cut Partition - for rectilinear partitions"
puts "###"
createPtnCut 557.4800 980.2800 756.8400 1171.8000
createPtnCut 553.5600 315.0000 783.7200 526.6800
#########################################################
Example C-28 HF: Place JTAG
#########################################################
puts "###"
puts "### Place Jtag cells"
puts "###"
#specifyJtag -inst DTMF_INST/TDSP_CORE_INST/PORT_BUS_MACH_INST/i_983
#placeJtag -nrRowLeft 5 -nrRowRight 5 -nrRowTop 5 -nrRowBottom 5
#########################################################
Example C-29 HF: Amoeba Place
#########################################################
Tcl Scripts
puts "###"
puts "### Placement using improved partition handling"
puts "###"
partitionPlace
checkPlace
setDrawMode place
#########################################################
Example C-30 HF: Trial Route/Extract/Timing Analysis
#########################################################
puts "###"
puts "### Trial Route "
puts "###"
trialRoute -highEffort -handlePartitionComplex -useM1
puts "###"
puts "### RC Extraction"
puts "###"
setExtractRCMode -detail -assumeMetFill
extractRC
puts "###"
puts "###"
buildTimingGraph
#########################################################
Example C-31 HF: IPO (no new module ports)
#########################################################
puts "###"
puts "### IPO Setup. Change file: ipo.txt"
puts "###"
Tcl Scripts
setIPOMode -highEffort -fixDrc -neverAddPort -honorFence -incrTrialRoute
-restruct -topomap -handlePartition
initECO ipo.txt
puts "###"
puts "### Fixing Setup Violations"
puts "###"
fixSetupViolation
endECO
cleanupECO
#########################################################
Example C-32 FR: Trial Route/Extract/Timing Analysis
#########################################################
puts "###"
puts "### Trial Route "
puts "###"
trialRoute -highEffort -handlePartitionComplex -useM1
puts "###"
puts "### RC Extraction. Do extraction in detailed mode for budgeting"
puts "###"
extractRC
rcOut -spef dtmf_chip.spef
puts "###"
puts "###"
buildTimingGraph
#########################################################
Example C-33 HF: Power Route
#########################################################
Tcl Scripts
puts "###"
puts "### Complete Power Routing"
puts "###"
sroute -nets {VSS VDD}
#########################################################
Example C-34 HF: Power Analysis
#########################################################
puts "###"
puts "###"
puts "###"
puts "###"
puts "###"
puts "### Power Analysis using Native FE mode for VDD net"
puts "###"
clearPadLocDisplay
setDrawMode place
updatePower -preCTS -toggleFile ${data}/dtmf_chip.tg -irDropAnalysis average
-pad dtmf_chip_autofetch_VDD.pp -mode layout VDD
displayIRDrop VDD -threshold 0.002
puts "###"
puts "### Power Analysis using Native FE mode for VSS net"
puts "###"
clearPadLocDisplay
autoFetchDCSources VSS
Tcl Scripts
savePadLocation -file dtmf_chip_autofetch_VSS.pp
setDrawMode place
updatePower -preCTS -toggleFile ${data}/dtmf_chip.tg -irDropAnalysis average
-pad dtmf_chip_autofetch_VSS.pp -mode layout VSS
displayIRDrop VSS -threshold 0.002
clearPadLocDisplay
saveDesign pre_partition
#########################################################
Example C-35 HF: Commit Partitions
#########################################################
puts "###"
puts "### Commit Partition"
puts "###"
commitPartition -pinsOffPG -noTrialIPO -timingShell -max -noConstantModel -verify
checkPinAssignment
#########################################################
Example C-36 HF: Save Partitions
#########################################################
puts "###"
puts "### Save Partition"
puts "### Note: Power budgets are generated *_VDD.pp + *_VSS.pp"
puts "###"
savePartition -savePlacement -def -pks -pt -dir PARTITION
puts "###"
puts "### Create an OA design lib"
puts "###"
catch {exec rm -rf oa_dtmf_chip}
exec echo "DEFINE tsmc18 ${library}/oa/tsmc18" > cds.lib
oaLibCreate oa_dtmf_chip tsmc18
exit
Tcl Scripts
Important
Following is the Block Implementation Tcl script example. See Flow on page 45 for the Block
Implementation flow.
#########################################################
# FLOW SECTION = Block Implementation
#########################################################
puts "###"
puts "###"
puts "###"
puts "###"
setCteReport
Example C-37 BI: Load Data
#########################################################
# Before executing script, set block variable to the name of the block
#########################################################
See Flow on page 45 for the Block Implementation flow.
set block [user_get_name]
puts "###"
puts "###"
loadConfig ${block}.conf
# KPnS 3.2: savePartition is not saving the min max .lib entries correctly
Tcl Scripts
set {rda_Input(ui_timelib,max)} \
"$ROOTDIR/library/synopsys/stdcell/slow.lib \
$ROOTDIR/library/synopsys/memory/ram_128x16A_slow_syn.lib \
$ROOTDIR/library/synopsys/memory/rom_512x16A_slow_syn.lib \
$ROOTDIR/library/synopsys/analog/pllclk_slow.lib \
$ROOTDIR/library/synopsys/iopads/tpz973gwc-lite.lib"
set {rda_Input(ui_timelib,min)} \
"$ROOTDIR/library/synopsys/stdcell/fast.lib \
$ROOTDIR/library/synopsys/memory/ram_128x16A_fast_syn.lib \
$ROOTDIR/library/synopsys/memory/rom_512x16A_fast_syn.lib \
$ROOTDIR/library/synopsys/analog/pllclk_fast.lib \
$ROOTDIR/library/synopsys/iopads/tpz973gbc-lite.lib"
commitConfig
defIn ./${block}.def
puts "###"
puts "###"
#########################################################
Example C-38 BI: Check Timing
#########################################################
puts "###"
puts "###"
setAnalysisMode -setup -async -skew -noClockTree -sequentialConstProp
reportAnalysisMode
checkTA -verbose > ${block}_check.rpt
-net -summary > ${block}.summary
-net > ${block}.slack
Tcl Scripts
#########################################################
Example C-39 BI: Detailed Placement
#########################################################
amoebaPlace -slow -ignoreScan -timingdriven
checkPlace
setDrawMode place
#########################################################
Example C-40 BI: Reorder Scan Chains
#########################################################
puts "###"
puts "###"
set scan_in {BG_scan_in BG_scan_in_2}
set scan_out {BG_scan_out BG_scan_out_2}
set n 0
specifyScanChain ${block}_chain_$n -start [lindex $scan_in $n]
-stop [lindex $scan_out $n]
incr n
}
scanTrace
scanReorder
puts "###"
puts "###"
defOut -scanChain ${block}_scan.def
#########################################################
Example C-41 BI: Trial Route/Extract/Timing Analysis
#########################################################
Tcl Scripts
puts "###"
puts "###"
trialRoute -highEffort
puts "###"
puts "###"
extractRC
puts "###"
puts "### Timing Analysis - preIPO"
puts "###"
buildTimingGraph
#########################################################
Example C-42 BI: Physical Synthesis
#########################################################
See Flow on page 45 for the Block Implementation flow or see PKS Physical Optimization
Sub Flow on page 73.
## For difficult timing blocks, can run Physical Synthesis
## using PKS
# runPhySyn
#########################################################
Example C-43 BI: Timing Optimization (IPO)
#########################################################
puts "###"
puts "###"
setIPOMode -highEffort -fixDrc -addPortAsNeeded -incrTrialRoute -restruct
-topomap -boolean -moveInst -fixFanoutLoad
initECO ipo.txt
Tcl Scripts
puts "###"
puts "### XTalk Prevention: congOpt"
puts "###"
congOpt
extractRC
buildTimingGraph
reportIPOSlacks -outfile ${block}.slack
reportIPOViolation -plusNonViolating -num 50 -outfile ${block}.tarpt
puts "###"
puts "### XTalk Prevention: balanceSlew"
puts "###"
balanceSlew
extractRC
buildTimingGraph
puts "###"
puts "###"
# Sufficient to use default extraction for IPO
extractRC
fixSetupViolation
# Reset back to detailed extraction
extractRC
extractRC
buildTimingGraph
puts "###"
puts "### Skew Clock Opt"
puts "###"
Tcl Scripts
setAnalysisMode -usefulSkew
buildTimingGraph
# KPnS 3.2: Remove previously created files
file delete scheduling_file.cts latency_file.sdc
skewClock
extractRC
buildTimingGraph
puts "###"
puts "### optCritPath fixes new critical paths due to new clock latencies"
puts "###"
optCritPath
extractRC
buildTimingGraph
puts "###"
puts "### Reclaim Area"
puts "###"
downsizeFAR -checkNextStage -nrDownIter 4 -checkTargetSlack -checkDriverFanin
extractRC
buildTimingGraph
puts "###"
puts "### DRC Fixing"
puts "###"
if {[isDRVClean -maxTran -maxCap -maxFanout] != 1} {
puts "###"
puts "### Fixing DRC Violations"
puts "###"
fixDRCViolation -maxTran -maxCap -maxFanout
}
puts "###"
puts "### Optimize Leakage Power by downsizing non-critical gates"
puts "### Does not affect timing or DRVs"
puts "###"
getReport reportLeakagePower > leakage_power_pre_opt.rpt
Tcl Scripts
optLeakagePower
getReport reportLeakagePower > leakage_power_post_opt.rpt
extractRC
buildTimingGraph
endECO
cleanupECO
puts "###"
puts "### Check for remaining DRV Violations"
puts "###"
reportTranViolation -outfile ${block}_tran.rpt
reportCapViolation -outfile ${block}_cap.rpt
reportFanoutViolation -outfile ${block}_fanout.rpt
puts "###"
puts "### Timing Analysis - post IPO, pre-Clock Tree "
puts "###"
extractRC
buildTimingGraph
# KPnS 3.2: reportTA does not take useful skew latencies into account
# reportTA -format {hpin arc cell delay arrival slew load} \
# -late -max_points 100 -net -summary > ${block}.summary
# -late -max_points 100 -net > ${block}.slack
#########################################################
Example C-44 BI: Clock Tree Synthesis
#########################################################
puts "###"
puts "###"
Tcl Scripts
puts "###"
puts "### Load Constraints including Clock Skew Latencies"
puts "###"
if { [getSchedulingFile] != {} } {
specifyClockTree -clkfile [getSchedulingFile]
}
specifyClockTree -clkfile $data/${block}.cts
checkUnique
puts "###"
puts "###"
ckSynthesis -rguide ${block}.rguide -report ${block}.ctsrpt
-macromodel ${block}.ctsmdl -fix_added_buffers
# Useful Skew Mode not required after CTS, real clock tree present
setAnalysisMode -noUsefulSkew
saveClockNets -output ${block}.ctsntf
displayClockTree -skew -gcts -allLevel
clearClockDisplay
#########################################################
Example C-45 BI: Trial Route/Extract/Timing Analysis
#########################################################
puts "###"
puts "###"
trialRoute -highEffort -guide ${block}.rguide
extractRC
reportClockTree -postRoute -localSkew -report ${block}_post_troute_local.ctsrpt
reportClockTree -postRoute -report ${block}_post_troute.ctsrpt
puts "###"
puts "### Timing Analysis - post Clock Tree"
puts "###"
setAnalysisMode -clockTree
buildTimingGraph
Tcl Scripts
saveDesign preIpo.enc
#########################################################
#########################################################
## using PKS
# runPhySyn
#########################################################
Example C-47 BI: Fix Setup/Hold (IPO High Effort)
#########################################################
puts "###"
puts "###"
initECO ipo.txt
puts "###"
puts "### Useful Skew IPO"
puts "###"
skewClock
extractRC
buildTimingGraph
puts "###"
puts "### optCritPath"
puts "###"
optCritPath
extractRC
buildTimingGraph
Tcl Scripts
# if timing is not met can iterate with skewClock
# puts "###"
# puts "### Useful Skew IPO"
# puts "###"
# skewClock
# extractRC
# buildTimingGraph
# reportIPOSlacks -outfile ${block}.slack
# reportIPOViolation -plusNonViolating -num 50 -outfile ${block}.tarpt
puts "###"
puts "###"
}
endECO
cleanupECO
puts "###"
puts "###"
puts "###"
puts "### Timing Analysis - post Clock Tree + IPO"
puts "###"
extractRC
buildTimingGraph
puts "###"
puts "### Report Critical Terms that Hold Fixing should not change"
puts "###"
reportCritTerm -outfile critical_terms.rpt
Tcl Scripts
puts "###"
puts "### Begin Hold Fixing"
puts "###"
puts "###"
puts "### Timing Analysis - Hold Analysis"
puts "###"
setAnalysisMode -hold
reportAnalysisMode
buildTimingGraph
reportTA -format {hpin arc cell delay arrival slew load} -early -max_points 100
puts "###"
puts "### IPO for Hold Violations"
puts "###"
extractRC
initECO ipo.txt
fixHoldViolation -excTermFile critical_terms.rpt
endECO
cleanupECO


puts "###"
puts "### Timing Analysis - post Hold IPO"
puts "###"
extractRC
buildTimingGraph
Tcl Scripts
#########################################################
#########################################################
## using PKS
# runPhySyn
puts "###"
puts "### End of Hold Fixing Flow"
puts "###"
puts "###"
puts "### Return to setup analysis"
puts "###"
setAnalysisMode -setup
reportAnalysisMode
#########################################################
Example C-49 BI: Add Filler Cells
#########################################################
# addEndCap -prefix endcap -preCap ENDCAP -postCap ENDCAP
# addWellTap -cell WELLTAP -prefix wtap_odd -maxGap 100 -skipRow 1
# addWellTap -cell WELLTAP -prefix wtap_even -maxGap 100 -skipRow 1 \
# -startRowNum 2 -inRowOffset 50
addFiller -cell FILL64 -prefix FILL -fillBoundary
# Need to connect power for all newly added cells
user_connect_power
Tcl Scripts
saveDesign preRoute.enc
#########################################################
Example C-50 BI: Routing w/SI Prevention
#########################################################
puts "###"
puts "### NanoRoute Options"
puts "###"
set critNet {@clock}
setAttribute -net $critNet -weight 100
# setAttribute -net $critNet -preferred_extra_space 2
setAttribute -net $critNet -avoid_detour true
setAttribute -net $critNet -bottom_preferred_routing_layer 4
setAttribute -net $critNet -top_preferred_routing_layer 5
# KPnS 3.2: Second NRoute doesn't rip up shield vias
# setAttribute -net $critNet -shield_net VSS
setAttribute -net $critNet -shield_net none
setNanoRouteMode -quiet drouteFixAntenna true
setNanoRouteMode -quiet routeInsertAntennaDiode false
setNanoRouteMode -quiet routeAntennaCellName default
setNanoRouteMode -quiet routeWithTimingDriven true
setNanoRouteMode -quiet routeWithTimingOpt false
setNanoRouteMode -quiet optimizeBi false
setNanoRouteMode -quiet optimizeGs false
setNanoRouteMode -quiet optimizeFixSetupTime true
setNanoRouteMode -quiet optimizeTargetSetupSlack 0.000000
setNanoRouteMode -quiet optimizeFixMaxCap false
setNanoRouteMode -quiet optimizeFixHoldTime false
setNanoRouteMode -quiet optimizeTargetHoldSlack 0.000000
setNanoRouteMode -quiet optimizeFixMaxTran false
setNanoRouteMode -quiet optimizeDontUseCellFile default
setNanoRouteMode -quiet routeWithSiDriven true
setNanoRouteMode -quiet routeSiEffort normal
setNanoRouteMode -quiet siNoiseCTotalThreshold 0.050000
setNanoRouteMode -quiet siNoiseCouplingCapThreshold 0.005000
setNanoRouteMode -quiet routeWithSiPostRouteFix false
Tcl Scripts
setNanoRouteMode -quiet drouteAutoStop true
setNanoRouteMode -quiet routeSelectedNetOnly false
setNanoRouteMode -quiet routeFixPrewire false
setNanoRouteMode -quiet drouteStartIteration default
setNanoRouteMode -quiet envNumberProcessor 2
setNanoRouteMode -quiet routeTopRoutingLayer default
setNanoRouteMode -quiet drouteEndIteration default
setNanoRouteMode -quiet routeReInsertFillerCellList
$data/nanoroute_filler_cells.txt
setNanoRouteMode -quiet drouteHonorMinFeature true
# New 3.2 Option to use CTE Timing Engine
setNanoRouteMode timingEngine CTE
puts "###"
puts "### Global and Detail Route with NanoRoute"
puts "###"
globalDetailRoute
puts "###"
puts "### Verify Connectivity, Geometry and Process Antenna"
puts "###"
fillNotch -reportfile notch.rpt
verifyConnectivity -type regular -reportfile ${block}.verifyConn.regular.rpt
verifyConnectivity -type special -reportfile ${block}.verifyConn.special.rpt
verifyGeometry -allowSameCellViols -allowRoutingBlkgPinOverlap
-allowRoutingCellBlkgOverlap -noSameNet -reportfile ${block}.verifyGeom.rpt
verifyProcessAntenna -reportfile ${block}.verifyProc.rpt
#########################################################
Example C-51 BI: Insert Metal Fill
#########################################################
puts "###"
puts "### Setup Metal Fill Parameters"
puts "###"
setMetalFill -layer { 1 2 3 4 5 6 } -windowSize 200.000 200.000
-windowStep 100.000 100.000 -minDensity 20.000 -maxDensity 80.000
-preferredDensity 50.000
Tcl Scripts
puts "###"
puts "### Add Metal Fill"
puts "###"
addMetalFill -layer { 1 2 3 4 5 6 } -nets { VSS VDD }
#########################################################
Example C-52 BI: Verify Connectivity, Geometry and Process Antenna
#########################################################
verifyMetalDensity -reportfile ${block}.density.rpt
#########################################################
Example C-53 BI: Extraction
#########################################################
puts "###"
puts "### Run FE Detailed Extractor"
puts "###"
setExtractRCMode -detail
extractRC
saveDesign prePRO.enc
rcOut -spef prePRO.enc.dat/${block}.spef
#########################################################
Example C-54 BI: Post-Route Optimization Sub Flow
#########################################################
puts "###"
puts "###"
buildTimingGraph
Tcl Scripts
puts "###"
puts "### verifyACLimit: Hold time mode gives you larger current"
puts "###"
buildTimingGraph
verifyACLimit -reportfile ${block}.aclimit.rpt -error 1000
-scaleIrms 1.0 -toggle 1.0
puts "###"
puts "### Delete Filler Cells"
puts "###"
deleteFiller -cell FILL64 -prefix FILL
puts "###"
puts "### Delete Metal Fill"
puts "###"
editDelete -shapes FILLWIRE
deleteNotchFill
puts "###"
puts "### Remove DRC Markers"
puts "###"
clearDrc
puts "###"
puts "### Update extract mode"
puts "###"
setExtractRCMode -detail -assumeMetFill -noReduce
extractRC
puts "###"
puts "### Optionally call PKS for post route optimization"
puts "###"
# runPostRouteOpt
Tcl Scripts
puts "###"
puts "### IPO - fix setup"
puts "###"
# V3.2 ECO Experimental Enhancement: Copy wire to guide ECO routing
set dbgInsertBufferWithWireCopy 1
puts "###"
puts "### setIPOMode -noIncrRoute -preserveRoute"
puts "### keeps routes of unmodified nets + removes route of modified nets"
puts "###"
setIPOMode -noRestruct -noSwapPin -preserveRoute -noIncrRoute -highEffort

initECO ipo.txt
puts "###"
puts "### fixACLimitViolation"
puts "###"
fixACLimitViolation
puts "###"
puts "### Resize only as post-route ipo"
puts "###"
resize -postIPO
puts "###"
puts "### optCritPath may also be called if buffer addition is required"
puts "###"
optCritPath
puts "###"
puts "###"
}
endECO
cleanupECO
puts "###"
puts "###"
Tcl Scripts
puts "###"
puts "### Timing Analysis - After Post Route Opt"
puts "###"
extractRC
buildTimingGraph
puts "###"
puts "###"
puts "###"
puts "### Hold fixing may be performed by uncommenting below commands"
puts "###"
# puts "###"
# puts "### CTE TA (Best Case)"
# puts "###"
#
# puts "###"
# puts "### Hold Timing Analysis"
# puts "###"
# setAnalysisMode -hold
#
# puts "###"
# puts "### Timing Analysis - Hold Analysis"
# puts "###"
# buildTimingGraph
# -early -max_points 100 -net -summary > ${block}.summary
# -early -max_points 100 -net > ${block}.slack
#
# puts "###"
# puts "### IPO - fix holds"
# puts "###"
# setIPOMode -highEffort -fixDrc -addPortAsNeeded -incrTrialRoute
# initECO ipo.txt
# fixHoldViolation -excTermFile critical_terms.rpt
Tcl Scripts
# endECO
# cleanupECO
#
# puts "###"
# puts "### Timing Analysis - post Hold IPO"
# puts "###"
# extractRC
# buildTimingGraph
#
# puts "###"
# puts "### Return to setup analysis"
# puts "###"
# setAnalysisMode -setup
puts "###"
puts "### Add Filler Cells"
puts "###"
puts "###"
puts "### Need to connect power for all newly added cells"
puts "###"
user_connect_power
saveDesign preECORoute.enc
puts "###"
puts "### SI Aware ECO Route"
puts "###"
setNanoRouteMode -quiet optimizeBi true
setNanoRouteMode -quiet optimizeGs true
setNanoRouteMode -quiet routeWithTimingOpt true
Tcl Scripts
setNanoRouteMode -quiet optimizeFixMaxCap true
setNanoRouteMode -quiet optimizeFixMaxTran true
setNanoRouteMode -quiet optimizeFixHoldTime true
setNanoRouteMode -quiet routeWithSiPostRouteFix true
setNanoRouteMode -quiet drouteAutoStop false
setNanoRouteMode -quiet routeWithECO true
# KPnS 3.2: CTE Mode automatically runs trialroute.
setNanoRouteMode timingEngine Nano
# KPnS 3.2: Shield vias are not ripped up
globalDetailRoute
puts "###"
puts "### Insert Metal Fill"
puts "###"
puts "###"
puts "### Run Fire & Ice (QX) for sign-off quality extraction."
puts "### (A separate license is required.)"
puts "###"
puts "### QX does not support LEF/DEF 5.4 or 5.5 and since "
puts "### metal fill is 5.4 syntax, 5.3 def has to be output instead. defOut of "
puts "### 5.3 has been modified to output a special grounded net which contains the"
puts "### fill shapes."
puts "###"
set dbgDefOut53 1
runQX -outputFileName ${block}.spef -grayData obs
-techFile ${library}/simplex/icecaps.tch -libraryName $library/simplex/tsmc18_6lm
# Reset back to def 5.5 default
set dbgDefOut53 0
puts "###"
puts "###"
buildTimingGraph
Tcl Scripts
saveDesign preSI.enc
Example C-55 BI: Timing/SI Closure Sub Flow
See Flow on page 45 for the Block Implementation flow or see Timing/SI Closure Sub Flow
on page 75.
puts "###"
puts "### fixCrosstalk does not yet support filler cells in input design"
puts "###"
puts "###"
puts "### fixCrosstalk does not yet support metal fill in input design"
puts "###"
deleteNotchFill
puts "###"
puts "###"
clearDrc
puts "###"
puts "### fixCrosstalk does not yet support met fill"
puts "### Assume metal fill"
puts "###"
setExtractRCMode -detail -noReduce -assumeMetFill
extractRC
puts "###"
puts "### Nanoroute SI Options"
puts "###"
Tcl Scripts
puts "###"
puts "### fixCrosstalk does not support CTE mode"
puts "### Switch to FE mode"
puts "###"
setFeReport
puts "###"
puts "### fixCrosstalk: Performs series of SI analysis + fixing loops"
puts "### based on the input config file: ${scripts}/siFix.option "
puts "###"
set xngNoiseThreshold 0.2
setSIMode -load ${scripts}/siFix.option
setSIMode -runRouteWithEco
# Report SI Fix Mode
setSIMode
fixCrosstalk -signoff
# fixCrosstalk -incr
puts "###"
puts "###"
puts "###"
puts "###"
user_connect_power
puts "###"
puts "###"
Tcl Scripts
#########################################################
Example C-56 BI: Insert Metal Fill
#########################################################
saveDesign preVerify.enc
#########################################################
Example C-57 BI: Verify Connectivity, Geometry and Process Antenna
#########################################################
#########################################################
Example C-58 BI: Extraction
#########################################################
puts "###"
puts "###"
puts "### QX does not support LEF/DEF 5.4 or 5.5"
puts "### and since metal fill is 5.4 syntax, 5.3 def has to be output instead."
puts "### defOut of 5.3 has been modified to output a special grounded net"
puts "### which contains the fill shapes."
puts "###"
set dbgDefOut53 1
runQX -outputFileName ${block}_done.spef -grayData obs
-techFile ${library}/simplex/icecaps.tch
-libraryName $library/simplex/tsmc18_6lm
Tcl Scripts
puts "###"
puts "### Reset back to def 5.5 default"
puts "###"
set dbgDefOut53 0
#########################################################
Example C-59 BI: Final Xtalk and Timing Analysis
#########################################################
puts "###"
puts "### Initialize the Switching windows"
puts "###"
initSwitchingWindows -nativeCeltIC
# initSwitchingWindows -signOff
loadCDB $library/cdb/$cdblib
puts "###"
puts "### Report on the glitch noise. Changed the threshold to report on more paths"
puts "###"
reportGlitchNoise -th 30 -vh -vl -viofile nets.si_vio
# reportCouplingCaps <noise_net>
# printSpice -f fe1.sp -v 0 -drvRes 400 -a <noise_net> -aggTran 5e-10
puts "###"
puts "### Calculate incremental delays due to x-coupling"
puts "###"
incrDelayCal -maxNrPass 1 -maxError 0.1
puts "###"
puts "### Switch back to CTE Mode after SI Analysis and Fixing"
puts "###"
setCteReport
puts "###"
puts "### Import Celtic Incremental SDF (Use sdfIn in CTE Mode)"
puts "###"
sdfIn -file celtic/celtic.sdf -mode max
puts "###"
puts "### Use Signal Storm to calculate sign off delays"
puts "### Signal Storm libraries should be built already using"
Tcl Scripts
puts "### source ${scripts}/build_ecsm.tcl"
puts "###"
setDelayCalMode -signalStorm -slowCorner slow -fastCorner fast
puts "###"
puts "### Final Timing Analysis (with Signal Storm Delays)"
puts "###"
buildTimingGraph
saveDesign preVS.enc
puts "###"
puts "### If Timing/Noise Analysis contain violations return to"
puts "### Fix Crosstalk Delete Fillers "
puts "###"
#########################################################
Example C-60 BI: Power Rail Analysis (VoltageStorm)
#########################################################
puts "###"
puts "### Power Analysis using Voltage Storm"
puts "### Requires additional license"
puts "###"
puts "###"
puts "###"
puts "###"
puts "###"
puts "###"
puts "### Generate Simplex libraries if none already exist"
puts "###"
Tcl Scripts
# runLibGen -groundPinList {VSS 0} \
# -layerMapping $library/simplex/lefdef_layer.map.txt \
# -genPortPowerView -techFile ${library}/simplex/icecaps.tch \
# -libraryName $library/simplex/tsmc18_6lm.cl \
# -powerPinList {VDD 1.62} \
# -lefFileList $dbgLefFile
puts "###"
puts "### Update Power VDD"
puts "### Using pp file (which includes voltages) generated during budgeting"
puts "###"
displayPadLoc -file ${block}_VDD.pp
updatePower -irDropAnalysis average -postCTS -toggleFile ${data}/${block}.tg
-pad ${block}_VDD.pp -reportInstancePower VDD_instance.power -mode layout VDD
clearPadLocDisplay
puts "###"
puts "### Update Power VSS"
puts "### Using pp file (which includes voltages) generated during budgeting"
puts "###"
displayPadLoc -file ${block}_VSS.pp
updatePower -irDropAnalysis average -postCTS -toggleFile ${data}/${block}.tg
-pad ${block}_VSS.pp -reportInstancePower VSS_instance.power -mode layout VSS
clearPadLocDisplay
catch {exec rm -rf ${block}.PGlib.cl}
# KPnS 3.2: VStorm fails with existing dirs
catch {exec rm -rf VStorm_VDD}
catch {exec rm -rf VStorm_VSS}
catch {exec rm -rf VSTORM}
puts "###"
puts "### Run Voltage Storm on VDD"
puts "###"
runVStorm -net VDD -voltLimit 1.4 -libs ${library}/simplex/tsmc18_6lm.cl
-powerFile VDD_instance.power -ppFile ${block}_VDD.pp -analyzeIR 1 -analyzeTC 1
-analyzeRC 1 -analyzeRJ 1 -analyzeER 1 -analyzeVV 1 -analyzeVC 1 -analyzeIV 1
-keepTempFiles 0 -outDir VSTORM -workDir VStorm_VDD -emLifetime 10
-emModelFile {} -useCellView {} -layerBias {} -layerMap {} -genView 1
-genViewLef ../dtmf_chip/${block}.partition.lef
-genViewView detailed -genIV 0 -isOutDir 1
puts "###"
puts "### Workaround. ${block}.PGlib.cl must ne renamed for next VStorm run"
puts "###"
catch {exec rm -rf ${block}.PGlib.VDD.cl}
file rename ${block}.PGlib.cl ${block}.PGlib.VDD.cl
Tcl Scripts
puts "###"
puts "### Run Voltage Storm on VSS"
puts "###"
runVStorm -net VSS -voltLimit 1.4 -libs ${library}/simplex/tsmc18_6lm.cl
-powerFile VSS_instance.power -ppFile ${block}_VSS.pp -analyzeIR 1 -analyzeTC 1
-analyzeRC 1 -analyzeRJ 1 -analyzeER 1 -analyzeVV 1 -analyzeVC 1 -analyzeIV 1
-keepTempFiles 0 -outDir VSTORM -workDir VStorm_VSS -emLifetime 10
-emModelFile {} -useCellView {} -layerBias {} -layerMap {}
-genViewLef ../dtmf_chip/${block}.partition.lef
-genViewView detailed -genIV 0 -isOutDir 1
puts "###"
puts "### Workaround. ${block}.PGlib.cl must ne renamed for next VStorm run"
puts "###"
catch {exec rm -rf ${block}.PGlib.VSS.cl}
file rename ${block}.PGlib.cl ${block}.PGlib.VSS.cl
puts "###"
puts "### Display VStorm Results"
puts "###"
displayVStormResults -net VDD -type ir -inDir VSTORM/VDD_25C_avg_1
-visibleLayer M6 V56 M5 V45 M4 V34 M3 V23 M2 V12 M1
puts "###"
puts "###"
displayVStormResults -net VSS -type ir -inDir VSTORM/VSS_25C_avg_1
#########################################################
Example C-61 BI: Create Noise Model
#########################################################
runCeltIC -auto -initSW -cdb $library/cdb/$cdblib -spef ./${block}_done.spef
-save_cdb -signOff -th 20.0
Tcl Scripts
#########################################################
Example C-62 BI: Generate DEF, GDSII, Netlist, OA DB
#########################################################
puts "###"
puts "### Save Design "
puts "###"
saveDesign ${block}_done.enc
puts "###"
puts "### Create DEF"
puts "###"
defOut -placement -routing -floorplan ${block}_done.def
puts "###"
puts "### Create Netlist"
puts "###"
saveNetlist -excludeLeafCell ${block}_done.v
puts "###"
puts "### Create Constraints"
puts "###"
writeTimingCon -pt -filePrefix ${block}_done
puts "###"
puts "### Create TLF Model: <blockName>.tlf"
puts "###"
# KPnS 3.2: Required otherwise issue with instance numbers mismatch
saveRC -rcdb ${block}.rcdb.gz
genTlfModel
puts "###"
puts "### Create Open Access Database - will create oa_${block}/${block}/layout"
puts "###"
oaOut oa_${block} ${block} layout -refLibs tsmc18 -leafViewNames layout
puts "###"
puts "### Create GDSII"
puts "###"
streamOut ${block}.gds -mapFile streamOut.map -libName DesignLib -stripes 1
-units 2000 -mode ALL
Tcl Scripts
puts "###"
puts "### Create LEF"
puts "###"
# KPnS 3.2: oaOut at top level requires <HCELL>_partition.lef LEF file name to
# recognise LEF as a partition LEF
lefOut ${block}_done
exit
Tcl Scripts
Important
Following is the Top-Level Implementation Tcl script example. See Flow on page 53 for the
Top-Level Implementation flow.
#########################################################
# FLOW SECTION = Top Level Implementation
#########################################################
puts "###"
puts "###"
puts "###"
puts "###"
setCteReport
Example C-63 TI: Load Data
See Flow on page 53 for the Top-Level Implementation flow.
#########################################################
#########################################################
puts "###"
puts "###"
loadConfig ${block}.conf
# KPnS 3.2: savePartition is not saving the min max .lib entries correctly
Tcl Scripts
set {rda_Input(ui_timelib,max)} \
"$ROOTDIR/library/synopsys/stdcell/slow.lib \
$ROOTDIR/library/synopsys/memory/rom_512x16A_slow_syn.lib \
$ROOTDIR/library/synopsys/analog/pllclk_slow.lib \
$ROOTDIR/library/synopsys/iopads/tpz973gwc-lite.lib"
set {rda_Input(ui_timelib,min)} \
"$ROOTDIR/library/synopsys/stdcell/fast.lib \
$ROOTDIR/library/synopsys/memory/rom_512x16A_fast_syn.lib \
$ROOTDIR/library/synopsys/analog/pllclk_fast.lib \
$ROOTDIR/library/synopsys/iopads/tpz973gbc-lite.lib"
set {rda_Input(ui_timelib)} {}
puts "###"
puts "### Remove Stamp Model Dependency"
puts "###"
set rda_Input(ui_smodDef) {}
set rda_Input(ui_smodData) {}
if { [file exists ../tdsp_core/tdsp_core.tlf] &&
[file exists ../results_conv/results_conv.tlf] &&
[file exists ../tdsp_core/tdsp_core_done.lef] &&
[file exists ../results_conv/results_conv_done.lef] } {
puts "###"
puts "### Loading the timing models of the implemented blocks"
puts "###"
set {rda_Input(ui_timelib)} {../tdsp_core/tdsp_core.tlf ../results_conv
/results_conv.tlf}
# set {rda_Input(ui_timelib,max)} "$rda_Input(ui_timelib,max) ../tdsp_core
/tdsp_core.tlf ../results_conv/results_conv.tlf"
# set {rda_Input(ui_timelib,min)} "$rda_Input(ui_timelib,min) ../tdsp_core
/tdsp_core.tlf ../results_conv/results_conv.tlf"
puts "###"
puts "### Loading Lef files with process antenna data of the implemented blocks"
puts "###"
puts "### These files were created by lefOut after verifyProcessAntenna"
puts "### was run as part of block implementation"
puts "###"
set rda_Input(ui_leffile) [lreplace $rda_Input(ui_leffile) 7 8
../tdsp_core/tdsp_core_done.lef ../results_conv/results_conv_done.lef]
} else {
Tcl Scripts
puts "###"
puts "### Loading the timing models of blocks. Generated during partitioning"
puts "###"
set {rda_Input(ui_timelib)} "$rda_Input(ui_timelib) $block.top.lib"
# set {rda_Input(ui_timelib,max)} "$rda_Input(ui_timelib,max) $block.top.tlf"
# set {rda_Input(ui_timelib,min)} "$rda_Input(ui_timelib,min) $block.top.tlf"
# KPnS 3.2: oaOut at top level requires _partition in LEF file name to
puts "###"
puts "### load *_partition.lef"
puts "### oaOut at top level workaround"
puts "###"
set rda_Input(ui_leffile) [lreplace $rda_Input(ui_leffile) 7 8
../dtmf_chip/tdsp_core_partition.lef ../dtmf_chip/results_conv_partition.lef]
}
commitConfig
setDrawMode fplan
loadFPlan ${block}.fp
puts "###"
puts "###"
#########################################################
Example C-64 TI: Check Timing
#########################################################
puts "###"
puts "###"
setAnalysisMode -setup -async -skew -noClockTree -sequentialConstProp
reportAnalysisMode
checkTA -verbose > ${block}_check.rpt
Tcl Scripts
#########################################################
Example C-65 TI: Detailed Placement
#########################################################
amoebaPlace -slow -ignoreScan -timingdriven
checkPlace
setDrawMode place
#########################################################
Example C-66 TI: Reorder Scan Chains
#########################################################
puts "###"
puts "###"
specifyScanCell tdsp_core -in BG_scan_in -out BG_scan_out
specifyScanCell results_conv -in BG_scan_in -out BG_scan_out
specifyScanCell results_conv -in BG_scan_in_2 -out BG_scan_out_2
set scan_in {{IOPADS_INST/Pscanin1ip/C} {IOPADS_INST/Pscanin2ip/C}}
set scan_out {{IOPADS_INST/Pscanout1op/I} {IOPADS_INST/Pscanout2op/I}}
set n 0
specifyScanChain ${block}_chain_$n -start [lindex $scan_in $n]
-stop [lindex $scan_out $n]
incr n
}
scanTrace
scanReorder
puts "###"
puts "###"
defOut -scanChain ${block}_scan.def
Tcl Scripts
#########################################################
Example C-67 TI: Trial Route/Extract/Timing Analysis
#########################################################
puts "###"
puts "###"
puts "###"
puts "###"
extractRC
puts "###"
puts "### Timing Analysis - preIPO"
puts "###"
buildTimingGraph
#########################################################
Example C-68 TI: Physical Synthesis
#########################################################
See Flow on page 53 for the Top-Level Implementation flow or see PKS Physical
Optimization Sub Flow on page 73.
## using PKS
# runPhySyn
#########################################################
Example C-69 TI: Timing Optimization (IPO)
#########################################################
Tcl Scripts
puts "###"
puts "###"
-topomap -boolean -moveInst -fixFanoutLoad -drcMargin 0.1
initECO ipo.txt
puts "###"
puts "### XTalk Prevention: congOpt"
puts "###"
congOpt
extractRC
buildTimingGraph
puts "###"
puts "### XTalk Prevention: balanceSlew"
puts "###"
balanceSlew
extractRC
buildTimingGraph
puts "###"
puts "### Insert Repeaters"
puts "###"
insertRepeater -rule ${data}/${block}.repeater.rules
extractRC
buildTimingGraph
puts "###"
puts "###"
extractRC
Tcl Scripts
fixSetupViolation
extractRC
buildTimingGraph
puts "###"
puts "### Skew Clock Opt"
puts "###"
setAnalysisMode -usefulSkew
buildTimingGraph
# KPnS 3.2: Remove previously created files
file delete scheduling_file.cts latency_file.sdc
skewClock
extractRC
buildTimingGraph
puts "###"
puts "### optCritPath fixes new critical paths due to new clock latencies"
puts "###"
optCritPath
extractRC
buildTimingGraph
puts "###"
puts "### Reclaim Area"
puts "###"
downsizeFAR -checkNextStage -nrDownIter 4 -checkTargetSlack -checkDriverFanin
extractRC
buildTimingGraph
Tcl Scripts
puts "###"
puts "### DRC Fixing"
puts "###"
puts "###"
puts "###"
}
puts "###"
puts "### Optimize Leakage Power by downsizing non-critical gates"
puts "### Does not affect timing or DRVs"
puts "###"
getReport reportLeakagePower > leakage_power_pre_opt.rpt
optLeakagePower
getReport reportLeakagePower > leakage_power_post_opt.rpt
extractRC
buildTimingGraph
endECO
cleanupECO
puts "###"
puts "###"
puts "###"
puts "### Timing Analysis - post IPO, pre-Clock Tree "
puts "###"
extractRC
buildTimingGraph
# KPnS 3.2: reportTA does not take useful skew latencies into account
Tcl Scripts
#########################################################
Example C-70 TI: Clock Tree Synthesis
#########################################################
puts "###"
puts "###"
puts "###"
puts "### Load Constraints including Clock Skew Latencies"
puts "###"
if { [getSchedulingFile] != {} } {
specifyClockTree -clkfile [getSchedulingFile]
}
specifyClockTree -clkfile $data/${block}.cts
checkUnique
puts "###"
puts "###"
ckSynthesis -rguide ${block}.rguide -report ${block}.ctsrpt -fix_added_buffers
# Useful Skew Mode not required after CTS, real clock tree present
setAnalysisMode -noUsefulSkew
saveClockNets -output ${block}.ctsntf
displayClockTree -skew -gcts -allLevel
clearClockDisplay
#########################################################
Example C-71 TI: Trial Route/Extract/Timing Analysis
#########################################################
Tcl Scripts
puts "###"
puts "###"
trialRoute -highEffort -guide ${block}.rguide
extractRC
reportClockTree -postRoute -localSkew -report ${block}_post_troute_local.ctsrpt
reportClockTree -postRoute -report ${block}_post_troute.ctsrpt
puts "###"
puts "### Timing Analysis - post Clock Tree"
puts "###"
setAnalysisMode -clockTree
buildTimingGraph
saveDesign preIpo.enc
#########################################################
#########################################################
## using PKS
# runPhySyn
#########################################################
Example C-73 TI: Fix Setup/Hold (IPO High Effort)
#########################################################
puts "###"
puts "###"
Tcl Scripts
initECO ipo.txt
puts "###"
puts "### Useful Skew IPO"
puts "###"
skewClock
extractRC
buildTimingGraph
puts "###"
puts "### optCritPath"
puts "###"
optCritPath
extractRC
buildTimingGraph
# if timing is not met can iterate with skewClock
# puts "###"
# puts "### Useful Skew IPO"
# puts "###"
# skewClock
# extractRC
# buildTimingGraph
# reportIPOSlacks -outfile ${block}.slack
# reportIPOViolation -plusNonViolating -num 50 -outfile ${block}.tarpt

puts "###"
puts "###"
}
endECO
cleanupECO
Tcl Scripts
puts "###"
puts "###"
puts "###"
puts "### Timing Analysis - post Clock Tree + IPO"
puts "###"
extractRC
buildTimingGraph
puts "###"
puts "###"
puts "###"
puts "### Begin Hold Fixing"
puts "###"
puts "###"
puts "### Timing Analysis - Hold Analysis"
puts "###"
reportAnalysisMode
buildTimingGraph
puts "###"
puts "### IPO for Hold Violations"
puts "###"
extractRC
Tcl Scripts
initECO ipo.txt
fixHoldViolation -excTermFile critical_terms.rpt
endECO
cleanupECO


puts "###"
puts "### Timing Analysis - post Hold IPO"
puts "###"
extractRC
buildTimingGraph
# KPnS 3.2: reportTA freezes post IPO
#########################################################
#########################################################
## using PKS
# runPhySyn
puts "###"
puts "### End of Hold Fixing Flow"
puts "###"
puts "###"
puts "### Return to setup analysis"
puts "###"
reportAnalysisMode
#########################################################
Example C-75 TI: Add Filler Cells
#########################################################
Tcl Scripts
puts "###"
puts "###"
user_connect_power
saveDesign preRoute.enc
#########################################################
Example C-76 TI: Routing w/CCAR
#########################################################
puts "###"
puts "### CCAR Chip Assembly Router Nets to Route"
puts "###"
set ccar_nets {{DTMF_INST/lpcm[7]} {DTMF_INST/lpcm[6]} {DTMF_INST/lpcm[5]}
{DTMF_INST/lpcm[4]} {DTMF_INST/lpcm[3]} {DTMF_INST/lpcm[2]}
{DTMF_INST/lpcm[1]} {DTMF_INST/lpcm[0]}}
runCCAR -nets $ccar_nets -doFile ${scripts}/top_implement_ccar.do
-lib soce2ccar -cell ${block} -view layout -refLibs tsmc18
puts "###"
puts "### Fix CCAR routed wires + set NRoute skip attribute"
puts "###"
foreach net_name $ccar_nets {
dbSetNetWireStatus [dbGetNetByName $net_name] Fixed
setAttribute -net $net_name -skip_routing true
}
Tcl Scripts
#########################################################
Example C-77 TI: Routing w/SI Prevention
#########################################################
puts "###"
puts "### NanoRoute Options"
puts "###"
set critNet {@clock}
setAttribute -net $critNet -weight 100
# setAttribute -net $critNet -preferred_extra_space 2
setAttribute -net $critNet -avoid_detour true
setAttribute -net $critNet -bottom_preferred_routing_layer 4
setAttribute -net $critNet -top_preferred_routing_layer 5
# KPnS 3.2: Second NRoute doesn't rip up shield vias
# setAttribute -net $critNet -shield_net VSS
setAttribute -net $critNet -shield_net none
setNanoRouteMode -quiet drouteFixAntenna true
setNanoRouteMode -quiet routeInsertAntennaDiode false
setNanoRouteMode -quiet routeAntennaCellName default
setNanoRouteMode -quiet optimizeBi false
setNanoRouteMode -quiet optimizeGs false
setNanoRouteMode -quiet optimizeFixMaxCap false
setNanoRouteMode -quiet optimizeFixHoldTime false
setNanoRouteMode -quiet optimizeFixMaxTran false
setNanoRouteMode -quiet optimizeDontUseCellFile default
setNanoRouteMode -quiet routeWithSiDriven true
setNanoRouteMode -quiet routeSiEffort normal
setNanoRouteMode -quiet siNoiseCTotalThreshold 0.050000
setNanoRouteMode -quiet siNoiseCouplingCapThreshold 0.005000
setNanoRouteMode -quiet routeWithSiPostRouteFix false
setNanoRouteMode -quiet drouteAutoStop true
Tcl Scripts
setNanoRouteMode -quiet routeSelectedNetOnly false
setNanoRouteMode -quiet routeFixPrewire false
setNanoRouteMode -quiet drouteStartIteration default
setNanoRouteMode -quiet envNumberProcessor 2
setNanoRouteMode -quiet routeTopRoutingLayer default
setNanoRouteMode -quiet drouteEndIteration default
setNanoRouteMode -quiet drouteHonorMinFeature true
# New 3.2 Option to use CTE Timing Engine
# setNanoRouteMode timingEngine CTE
puts "###"
puts "### Global and Detail Route with NanoRoute"
puts "###"
globalDetailRoute
puts "###"
puts "###"
#########################################################
Example C-78 TI: Insert Metal Fill
#########################################################
puts "###"
puts "###"
setMetalFill -layer { 1 2 3 4 5 6 } \
-windowSize 200.000 200.000 -windowStep 100.000 100.000 \
-minDensity 20.000 -maxDensity 80.000 -preferredDensity 50.000
Tcl Scripts
puts "###"
puts "### Add Metal Fill"
puts "###"
#########################################################
Example C-79 TI: Verify Connectivity, Geometry and Process Antenna
#########################################################
#########################################################
Example C-80 TI: Extraction
#########################################################
puts "###"
puts "### Run FE Detailed Extractor"
puts "###"
setExtractRCMode -detail
extractRC
rcOut -spef preSI.enc.dat/${block}.spef
#########################################################
Example C-81 TI: Post Route Optimization Flow
#########################################################
puts "###"
puts "###"
buildTimingGraph
Tcl Scripts
puts "###"
puts "###"
buildTimingGraph
verifyACLimit -reportfile ${block}.aclimit.rpt -error 1000 -scaleIrms 1.0
-toggle 1.0
puts "###"
puts "###"
puts "###"
puts "###"
deleteNotchFill
puts "###"
puts "###"
clearDrc
puts "###"
puts "### Update extract mode"
puts "###"
setExtractRCMode -detail -extendedCapTbl -assumeMetFill -noReduce
extractRC
puts "###"
puts "### Optionally call PKS for post route optimization"
puts "###"
# runPostRouteOpt
Tcl Scripts
puts "###"
puts "### IPO - fix setup"
puts "###"
# V3.2 ECO Experimental Enhancement: Copy wire to guide ECO routing
set dbgInsertBufferWithWireCopy 1
puts "###"
puts "### setIPOMode -noIncrRoute -preserveRoute"
puts "### keeps routes of unmodified nets + removes route of modified nets"
puts "###"
setIPOMode -noRestruct -noSwapPin -preserveRoute -noIncrRoute -highEffort

initECO ipo.txt
puts "###"
puts "### fixACLimitViolation"
puts "###"
fixACLimitViolation
puts "###"
puts "### Resize only as post-route ipo"
puts "###"
resize -postIPO
puts "###"
puts "### optCritPath may also be called if buffer addition is required"
puts "###"
optCritPath
puts "###"
puts "###"
}
endECO
cleanupECO
puts "###"
puts "###"
Tcl Scripts
puts "###"
puts "### Timing Analysis - After Post Route Opt"
puts "###"
extractRC
buildTimingGraph
puts "###"
puts "###"
puts "###"
puts "### Hold fixing may be performed by uncommenting below commands"
puts "###"
# puts "###"
# puts "### CTE TA (Best Case)"
# puts "###"
#
# puts "###"
# puts "### Hold Timing Analysis"
# puts "###"
# setAnalysisMode -hold
#
# puts "###"
# puts "### Timing Analysis - Hold Analysis"
# puts "###"
# buildTimingGraph
#
#
# puts "###"
# puts "### IPO - fix holds"
# puts "###"
# setIPOMode -highEffort -fixDrc -addPortAsNeeded -incrTrialRoute
# initECO ipo.txt
Tcl Scripts
# fixHoldViolation -excTermFile critical_terms.rpt
# endECO
# cleanupECO
#
# puts "###"
# puts "### Timing Analysis - post Hold IPO"
# puts "###"
# extractRC
# buildTimingGraph
#
# puts "###"
# puts "### Return to setup analysis"
# puts "###"
# setAnalysisMode -setup
puts "###"
puts "###"
puts "###"
puts "###"
user_connect_power
saveDesign preECORoute.enc
puts "###"
puts "### SI Aware ECO Route"
puts "###"
setNanoRouteMode -quiet optimizeBi true
Tcl Scripts
setNanoRouteMode -quiet optimizeGs true
setNanoRouteMode -quiet routeWithTimingOpt true
setNanoRouteMode -quiet optimizeFixMaxCap true
setNanoRouteMode -quiet optimizeFixMaxTran true
setNanoRouteMode -quiet optimizeFixHoldTime true
setNanoRouteMode -quiet routeWithECO true
# KPnS 3.2: Shield vias are not ripped up
globalDetailRoute
puts "###"
puts "### Insert Metal Fill"
puts "###"
puts "###"
puts "###"
puts "### QX does not support LEF/DEF 5.4 or 5.5 and since"
puts "### metal fill is 5.4 syntax, 5.3 def has to be output instead. defOut of"
puts "### 5.3 has been modified to output a special grounded net which contains the"
puts "### fill shapes."
puts "###"
set dbgDefOut53 1
runQX -outputFileName ${block}.spef -grayData obs
set dbgDefOut53 0
puts "###"
puts "###"
buildTimingGraph
Tcl Scripts
#########################################################
Example C-82 TI: Timing/SI Closure Flow
#########################################################
See Flow on page 53 for the Top-Level Implementation flow or see Timing/SI Closure Sub
Flow on page 75.
puts "###"
puts "### fixCrosstalk does not yet support filler cells in input design"
puts "###"
puts "###"
puts "### fixCrosstalk does not yet support metal fill in input design"
puts "###"
deleteNotchFill
puts "###"
puts "###"
clearDrc
puts "###"
puts "### fixCrosstalk does not yet support met fill"
puts "### Assume metal fill"
puts "###"
setExtractRCMode -detail -noReduce -assumeMetFill
Tcl Scripts
extractRC
puts "###"
puts "### Nanoroute SI Options"
puts "###"
# KPnS 3.2: Deferred for 3.2 with fixCrosstalk
# setNanoRouteMode -quiet routeWithECO true
puts "###"
puts "### fixCrosstalk does not support CTE mode"
puts "### Switch to FE mode"
puts "###"
setFeReport
puts "###"
puts "### fixCrosstalk: Performs series of SI analysis + fixing loops"
puts "### based on the input config file: ${scripts}/siFix_top_level.option "
puts "###"
setSIMode -load ${scripts}/siFix_top_level.option
setSIMode -runRouteWithEco
# Report SI Fix Mode
setSIMode
fixCrosstalk -signoff
# fixCrosstalk -incr
puts "###"
puts "###"
Tcl Scripts
puts "###"
puts "###"
user_connect_power
puts "###"
puts "###"
#########################################################
Example C-83 TI: Insert Metal Fill
#########################################################
saveDesign preVerify.enc
#########################################################
Example C-84 TI: Verify Connectivity, Geometry and Process Antenna
#########################################################
#########################################################
Example C-85 TI: Extraction
#########################################################
puts "###"
Tcl Scripts
puts "###"
puts "### QX does not support LEF/DEF 5.4 or 5.5 and since"
puts "### metal fill is 5.4 syntax, 5.3 def has to be output instead."
puts "### defOut of 5.3 has been modified to output a special grounded net which "
puts "### contains the fill shapes."
puts "###"
set dbgDefOut53 1
runQX -outputFileName ${block}_done.spef -grayData obs
set dbgDefOut53 0
#########################################################
Example C-86 TI: Final Xtalk and Timing Analysis
#########################################################
# Could alternatively run stand-alone celtic
# runCeltIC -effort high -auto -cdb $library/cdb/$cdblib \
# -spef ./${block}_done.spef -save_cdb -th 20.0
puts "###"
puts "### Initialize the Switching windows"
puts "###"
initSwitchingWindows -nativeCeltIC
# initSwitchingWindows -signOff
loadCDB $library/cdb/$cdblib ../results_conv/celtic/results_conv.cdb
../tdsp_core/celtic/tdsp_core.cdb
puts "###"
puts "### Report on the glitch noise. Changed the threshold to report on more paths"
puts "###"
reportGlitchNoise -th 30 -vh -vl -viofile nets.si_vio
# reportCouplingCaps <noise_net>
# printSpice -f fe1.sp -v 0 -drvRes 400 -a <noise_net> -aggTran 5e-10
puts "###"
puts "### Calculate incremental delays due to x-coupling"
puts "###"
Tcl Scripts
incrDelayCal -maxNrPass 1 -maxError 0.1
puts "###"
puts "### Switch back to CTE Mode after SI Analysis and Fixing"
puts "###"
setCteReport
puts "###"
puts "### Import Celtic Incremental SDF (Use sdfIn in CTE Mode)"
puts "###"
sdfIn -file celtic/celtic.sdf -mode max
puts "###"
puts "###"

puts "###"
puts "###"
buildTimingGraph
saveDesign preVS.enc
puts "###"
puts "### If Timing/Noise Analysis contain violations return to"
puts "### Fix Crosstalk Delete Fillers "
puts "###"
#########################################################
Example C-87 TI: Power Rail Analysis (VoltageStorm)
#########################################################
puts "###"
puts "###"
Tcl Scripts
puts "###"
puts "###"
puts "###"
puts "###"
puts "###"
puts "### Generate Simplex libraries if none already exist"
puts "###"
# runLibGen -groundPinList {VSS 0} \
# -layerMapping $library/simplex/lefdef_layer.map.txt \
# -genPortPowerView -techFile ${library}/simplex/icecaps.tch \
# -libraryName $library/simplex/tsmc18_6lm.cl \
# -powerPinList {VDD 1.62} \
# -lefFileList $dbgLefFile
puts "###"
puts "###"
clearPadLocDisplay
setDrawMode place
updatePower -irDropAnalysis average -toggleProb 0.2 -clockRate 100
-pad dtmf_chip_autofetch_VDD.pp -reportInstancePower VDD_instance.power
-mode layout VDD
clearPadLocDisplay
puts "###"
puts "###"
clearPadLocDisplay
savePadLocation -file dtmf_chip_autofetch_VSS.pp
Tcl Scripts
setDrawMode place
updatePower -irDropAnalysis average -toggleProb 0.2 -clockRate 100
-pad dtmf_chip_autofetch_VSS.pp -reportInstancePower VSS_instance.power
-mode layout VSS
clearPadLocDisplay
catch {exec rm -rf ${block}.PGlib.cl}
puts "###"
puts "###"
runVStorm -net VDD -voltLimit 1.4
-libs ${library}/simplex/tsmc18_6lm.cl ${currentdir}/../tdsp_core/
tdsp_core.PGlib.VDD.cl ${currentdir}/../results_conv/results_conv.PGlib.VDD.cl
-powerFile VDD_instance.power -ppFile dtmf_chip_autofetch_VDD.pp -analyzeIR 1
-analyzeTC 1 -analyzeRC 1 -analyzeRJ 1 -analyzeER 1 -analyzeVV 1 -analyzeVC 1
-analyzeIV 1 -keepTempFiles 0 -outDir VSTORM -workDir VStorm_VDD -emLifetime 10
-genViewLef {} -genViewView detailed -genIV 0 -isOutDir 1 -genBbv 0
puts "###"
puts "###"
runVStorm -net VSS -voltLimit 1.4
-libs ${library}/simplex/tsmc18_6lm.cl ${currentdir}/../tdsp_core/
tdsp_core.PGlib.VSS.cl ${currentdir}/../results_conv/results_conv.PGlib.VSS.cl
-powerFile VSS_instance.power -ppFile dtmf_chip_autofetch_VSS.pp -analyzeIR 1
-analyzeTC 1 -analyzeRC 1 -analyzeRJ 1 -analyzeER 1 -analyzeVV 1 -analyzeVC 1
-analyzeIV 1 -keepTempFiles 0 -outDir VSTORM -workDir VStorm_VSS -emLifetime 10
-genViewLef {} -genViewView detailed -genIV 0 -isOutDir 1 -genBbv 0
puts "###"
puts "###"
Tcl Scripts
puts "###"
puts "###"
displayVStormResults -net VSS -type ir -inDir VSTORM/VSS_25C_avg_1
#########################################################
Example C-88 TI: Generate DEF, GDSII, Netlist, OA DB
#########################################################
puts "###"
puts "###"
saveDesign ${block}_done.enc
puts "###"
puts "###"
defOut -placement -routing -floorplan ${block}_done.def
puts "###"
puts "###"
saveNetlist -excludeLeafCell ${block}_done.v
puts "###"
# Create Constraints
writeTimingCon -pt -filePrefix ${block}_done
puts "###"
puts "###"
puts "### Create Open Access Database - will create oa_${block}/${block}/layout"
puts "###"
# KPnS 3.2: oaOut at top level requires partition in LEF file name to
oaOut oa_${block} ${block} layout -refLibs tsmc18 -leafViewNames layout
puts "###"
puts "###"
Tcl Scripts
streamOut ${block}.gds -mapFile streamOut.map -libName DesignLib -stripes 1
-units 2000 -mode ALL
exit
Tcl Scripts
Important
Following is the Chip Assembly / Sign-Off Tcl script example. See Flow on page 61 for the
Chip Assembly / Sign-Off flow.
#########################################################
# FLOW SECTION = Chip Assembly / Sign-Off
#########################################################
puts "###"
puts "###"
puts "###"
puts "###"
setCteReport
#########################################################
#########################################################
puts "###"
puts "###"
loadConfig ${data}/dtmf_chip_assembly.conf
set {rda_Input(ui_netlist)} "PARTITION/dtmf_chip/dtmf_chip_done.v \
PARTITION/results_conv/results_conv_done.v \
PARTITION/tdsp_core/tdsp_core_done.v \
$ROOTDIR/data/stubs.v"
commitConfig
Tcl Scripts
puts "###"
puts "###"
#########################################################
Example C-89 CA: Flatten Design
#########################################################
See Flow on page 61 for the Chip Assembly / Sign-Off flow.
puts "###"
puts "### Load the floorplan file from the initial Floorplanning stage"
puts "###"
loadFPlan dtmf_chip_floorplan_refine.fp
puts "###"
puts "### Re-specify Physical partition "
puts "###"
setDrawMode fplan
#deleteAllPartitions
createPartition tdsp_core DTMF_INST/TDSP_CORE_INST 560 560 0 0
createPartition results_conv DTMF_INST/RESULTS_CONV_INST 560 560 0 0
createPtnCut 557.4800 980.2800 756.8400 1171.8000
createPtnCut 553.5600 315.0000 783.7200 526.6800
puts "###"
puts "### Commit Partition without any pin assignment"
puts "###"
commitPartition -noTrialIPO -noPinAssign
set dbgDefInCoreBox 1
puts "###"
# Restore Top level Placement and Routing
puts "###"
defIn ./PARTITION/dtmf_chip/dtmf_chip_done.def
puts "###"
puts "### Load all Partitions by changing the TopCell and reading in the def files"
puts "###"
setTopCell results_conv
defIn ./PARTITION/results_conv/results_conv_done.def
Tcl Scripts
setTopCell dtmf_chip
setTopCell tdsp_core
defIn ./PARTITION/tdsp_core/tdsp_core_done.def
setTopCell dtmf_chip
puts "###"
puts "### Finally unpartition the design to get a complete flat database"
puts "###"
flattenPartition results_conv
flattenPartition tdsp_core
puts "###"
puts "###"
verifyConnectivity -type regular -reportfile dtmf_chip_flat.verifyConn.regular.rpt
verifyConnectivity -type special -reportfile dtmf_chip_flat.verifyConn.special.rpt
-allowRoutingCellBlkgOverlap -noSameNet -reportfile dtmf_chip_flat.verifyGeom.rpt
verifyProcessAntenna -reportfile dtmf_chip_flat.verifyProc.rpt
puts "###"
puts "###"
setMetalFill -layer { 1 2 3 4 5 6 } -windowSize 200.000 200.000
-windowStep 100.000 100.000 -minDensity 20.000 -maxDensity 80.000
-preferredDensity 50.000
verifyMetalDensity -reportfile dtmf_chip_flat.density.rpt
#########################################################
Example C-90 CA: Extraction
#########################################################
# Run Fire & Ice (QX) for sign-off quality extraction. (A separate license is
# required.)
# QX does not support LEF/DEF 5.4 or 5.5
# and since metal fill is 5.4 syntax, 5.3 def has to be output instead. defOut
# of 5.3 has been modified to output a special grounded net which contains the
# fill shapes.
set dbgDefOut53 1
Tcl Scripts
runQX -outputFileName dtmf_chip_flat.spef -grayData obs
-techFile ${library}/simplex/icecaps.tch
-libraryName ${library}/simplex/tsmc18_6lm
puts "###"
puts "###"
set dbgDefOut53 0
#########################################################
Example C-91 CA: Flat Power Analysis
#########################################################
puts "###"
puts "###"
puts "###"
puts "###"
puts "###"
puts "###"
puts "###"
puts "### Auto Detect DC Sources from Design"
puts "###"
savePadLocation -file dtmf_chip_flat_autofetch_VDD.pp
puts "###"
puts "###"
updatePower -postCTS -irDropAnalysis average -toggleFile ${data}/dtmf_chip.tg
-pad dtmf_chip_flat_autofetch_VDD.pp -reportInstancePower VDD_instance.power
-mode layout VDD
Tcl Scripts
puts "###"
puts "### Auto Detect DC Sources from Design"
puts "###"
savePadLocation -file dtmf_chip_flat_autofetch_VSS.pp
puts "###"
puts "###"
updatePower -postCTS -irDropAnalysis average -toggleFile ${data}/dtmf_chip.tg
-pad dtmf_chip_flat_autofetch_VSS.pp -reportInstancePower VSS_instance.power
-mode layout VSS
puts "###"
puts "###"
runVStorm -net VDD -voltLimit 1.4 -libs ${library}/simplex/tsmc18_6lm.cl
-powerFile VDD_instance.power -ppFile dtmf_chip_flat_autofetch_VDD.pp
-analyzeIR 1 -analyzeTC 1 -analyzeRC 1 -analyzeRJ 1 -analyzeER 1 -analyzeVV 1
-analyzeVC 1 -analyzeIV 1 -keepTempFiles 0 -outDir VSTORM -workDir {}
-emLifetime 10 -emModelFile {} -useCellView {} -layerBias {} -layerMap {}
-genView 0 -genViewLef {} -genViewView detailed -genIV 0 -isOutDir 1
puts "###"
puts "###"
runVStorm -net VSS -voltLimit 1.4 -libs ${library}/simplex/tsmc18_6lm.cl
-powerFile VSS_instance.power -ppFile dtmf_chip_flat_autofetch_VSS.pp
-analyzeIR 1 -analyzeTC 1 -analyzeRC 1 -analyzeRJ 1 -analyzeER 1 -analyzeVV 1
-analyzeVC 1 -analyzeIV 1 -keepTempFiles 0 -outDir VSTORM -workDir {}
-emLifetime 10 -emModelFile {} -useCellView {} -layerBias {} -layerMap {}
-genView 0 -genViewLef {} -genViewView detailed -genIV 0 -isOutDir 1
puts "###"
puts "###"
puts "###"
puts "###"
Tcl Scripts
displayVStormResults -net VSS -type ir -inDir VSTORM/VSS_25C_avg_1 \
#########################################################
Example C-92 CA: Flat Xtalk Analysis
#########################################################
puts "###"
puts "### XTalk Analysis using standalone Celtic"
puts "###"
runCeltIC -auto -initSW -cdb ${library}/cdb/${cdblib}
-spef ./dtmf_chip_flat.spef
-signOff -th 20.0
#########################################################
Example C-93 CA: Flat Timing Analysis
#########################################################
puts "###"
puts "### runCeltIC above reset back to FE Reporting"
puts "###"
setCteReport
puts "###"
puts "###"

puts "###"
puts "###"
user_set_opcond slow
buildTimingGraph
Tcl Scripts
puts "###"
puts "###"
buildTimingGraph
verifyACLimit -reportfile dtmf_chip_flat.aclimit.rpt -error 1000 -scaleIrms 1.0
-toggle 1.0
#########################################################
Example C-94 CA: Create OA DB
#########################################################
puts "###"
puts "###"
saveDesign dtmf_chip_flat.enc
puts "###"
puts "###"
defOut -placement -routing -floorplan dtmf_chip_flat.def
puts "###"
puts "###"
saveNetlist -excludeLeafCell dtmf_chip_flat.v
puts "###"
puts "### Create Constraints"
puts "###"
writeTimingCon -pt -filePrefix dtmf_chip_flat
puts "###"
puts "### Create OA Database - will create oa_dtmf_chip_flat/dtmf_chip/layout"
puts "###"
catch {exec rm -rf oa_dtmf_chip_flat}
oaLibCreate oa_dtmf_chip tsmc18
oaOut oa_dtmf_chip_flat dtmf_chip layout -refLibs tsmc18 -leafViewNames layout
puts "###"
puts "###"
Tcl Scripts
streamOut dtmf_chip_flat.gds -mapFile streamOut.map -libName DesignLib
-stripes 1 -units 2000 -mode ALL
exit
Tcl Scripts
Chip Finishing
No Tcl scripts are available for this flow procedure. See Flow on page 67 for the Chip
Finishing flow.
Tcl Scripts
Miscellaneous Scripts
The following scripts provide additional information.
CTS File Script
Example C-95 MI: CTS File
RouteTypeName CK1
# PreferredExtraSpace 1
TopPreferredLayer 5
BottomPreferredLayer 4
# Shielding VDD VSS
Shielding VSS
End
#----------------------------------------------------------
# set_clock vclk1 -period 10.0 -waveform { 0 5.0 }
# set clock_pin [find -hier -pin DTMF_INST/TEST_CONTROL_INST/m_clk]
# set drive_pin [get_drive_pin -hier [get_info $clock_pin net] ]
# set drive_inst [find -full -hier -inst [get_info $drive_pin instance] ]
# set_clock_root -clock vclk1 -pos $drive_pin
# set_clock_insertion_delay -pin $drive_pin 2.0
#----------------------------------------------------------
AutoCTSRootPin DTMF_INST/TEST_CONTROL_INST/i_150/Y
MaxDelay 2.5ns
MinDelay 0ns
MaxSkew 250ps
SinkMaxTran 250ps
BufMaxTran 250ps
DetailReport YES
Obstruction YES
# RouteClkNet YES <---------- for NanoRoute Invoking.
# PostOpt YES
Buffer CLKBUFX8 CLKBUFX16 CLKBUFX20 CLKINVX8 CLKINVX16 CLKINVX20
MaxCap
+ CLKBUFXL 1pf
+ CLKBUFX2 1pf
+ CLKBUFX4 1pf
Tcl Scripts
+ CLKBUFX8 1pf
RouteType CK1
End
#----------------------------------------------------------
# set clock_pin [find -hier -pin DTMF_INST/TEST_CONTROL_INST/m_rcc_clk]
#----------------------------------------------------------
MaxDelay 2.5ns
MinDelay 0ns
MaxSkew 250ps
SinkMaxTran 250ps
BufMaxTran 250ps
DetailReport YES
Obstruction YES
# PostOpt YES
MaxCap
+ CLKBUFXL 1pf
+ CLKBUFX2 1pf
+ CLKBUFX4 1pf
+ CLKBUFX8 1pf
RouteType CK1
End
#----------------------------------------------------------
# set clock_pin [find -hier -pin DTMF_INST/TEST_CONTROL_INST/m_digit_clk]
#----------------------------------------------------------
MaxDelay 2.5ns
Tcl Scripts
MinDelay 0ns
MaxSkew 250ps
SinkMaxTran 250ps
BufMaxTran 250ps
DetailReport YES
Obstruction YES
# PostOpt YES
MaxCap
+ CLKBUFXL 1pf
+ CLKBUFX2 1pf
+ CLKBUFX4 1pf
+ CLKBUFX8 1pf
RouteType CK1
End
#----------------------------------------------------------
# set clock_pin [find -hier -pin DTMF_INST/TEST_CONTROL_INST/m_spi_clk]
#----------------------------------------------------------
MaxDelay 2.5ns
MinDelay 0ns
MaxSkew 250ps
SinkMaxTran 250ps
BufMaxTran 250ps
DetailReport YES
Obstruction YES
# PostOpt YES
MaxCap
+ CLKBUFXL 1pf
+ CLKBUFX2 1pf
+ CLKBUFX4 1pf
+ CLKBUFX8 1pf
Tcl Scripts
RouteType CK1
End
#----------------------------------------------------------
# set clock_pin [find -hier -pin DTMF_INST/TEST_CONTROL_INST/m_ram_clk]
#----------------------------------------------------------
MaxDelay 2.5ns
MinDelay 0ns
MaxSkew 250ps
SinkMaxTran 250ps
BufMaxTran 250ps
DetailReport YES
Obstruction YES
# PostOpt YES
MaxCap
+ CLKBUFXL 1pf
+ CLKBUFX2 1pf
+ CLKBUFX4 1pf
+ CLKBUFX8 1pf
RouteType CK1
End
#----------------------------------------------------------
# set clock_pin [find -hier -pin DTMF_INST/TEST_CONTROL_INST/m_dsram_clk]
#----------------------------------------------------------
MaxDelay 2.5ns
MinDelay 0ns
MaxSkew 250ps
Tcl Scripts
SinkMaxTran 250ps
BufMaxTran 250ps
DetailReport YES
Obstruction YES
# PostOpt YES
MaxCap
+ CLKBUFXL 1pf
+ CLKBUFX2 1pf
+ CLKBUFX4 1pf
+ CLKBUFX8 1pf
RouteType CK1
End
Tcl Scripts
D
The following information is provided to help resolve timing closure issues related to the Block
and Top-Level Implementation flow procedures. It includes examples that use BuildGates/
Physically Knowledgeable Synthesis (BG/PKS) commands.
BG/PKS commands can usually be distinguished from Encounter commands by the use of
the underscore character (for example, do_optimize). The hyperlinks from these
commands go to the Command Reference for BuildGates Synthesis and Cadence
PKS.
Overview on page 184
Preplacement Optimization on page 184
Floorplanning/Initial Placement on page 185
Routability on page 185
Timing on page 186
Path Groups on page 187
Critical Path Replacement on page 193
Example Approach on page 194
Overview
This section describes some approaches for determining the root cause of timing closure
issues and some techniques for improving the overall performance of difficult designs.
Because of tight timing constraints in cutting-edge circuitry, designers need to consider:
Logic restructuring of netlists prior to placement.
Better initial placement of extremely tight timing paths (that is, high speed RAM access
or IO timing), useful skew (primarily) in areas where the clocks can be isolated (for
example, RAMs).
Critical path replacement has become evident.
Preplacement Optimization
In some situations, the input netlist (typically from a WLM optimization) is not a good
candidate for placement (over-buffered, for example). In other cases, the netlist might contain
poorly structured logic that can lead to timing closure problems.
Typically, high fanout nets should be buffered after placement. It is often more reliable to allow
buffer insertion algorithms to build and place buffer trees rather than to rely on the placer to
place previously built trees in optimal locations. In addition, having buffer trees in the initial
netlist has been known to adversely affect the initial placement. Because of these effects, it
can be advantageous to run preplacement optimization or simple buffer and double-inverter
removal (area reclamation) prior to initial placement.
For designs where the logic structuring of the critical path is the source of closure problems,
you might need to restructure or remap the elements on that path (or related portions of the
design) to get better timing results.
To see if remapping helps, use the command do_optimize -remap_for_timing. You
can also isolate certain paths in the design to work on for quicker run times (see Path Groups
on page 187).
Unmapping and then remapping the entire design has not been shown to improve the quality
of results and is very expensive in terms of run time. If there are modules in particular where
remapping might be helpful and all else has failed, set the current module to that particular
module, unmap it and remap it. After performing this operation, use the command do_place
-fix_placed_cell to place only the newly mapped components.
Floorplanning/Initial Placement
The initial placement (and hence the floorplan) has a first order impact on the performance of
the design. It is highly recommended that you analyze various placements and floorplans
before investing time in long optimization runs. That is the inherent value of the prototyping
processarriving at a floorplan that can be implemented with high confidence before
committing days of CPU time to optimizing and routing.
Prototyping involves multiple iterations to converge on a solution which meets a designs
routability, timing (including clocks), power, and signal integrity requirements. The initial
floorplan drives the constraints leveraged by Amoeba Placement and partitioning to meet
these objectives.
It is recommended that you run the initial placement without any regions and guides. It is
always best to get a baseline placement without constraining the placer. After the placement
has been analyzed for timing and routability issues, you can employ module guides, density
screens, placement blockages, and other techniques to refine the floorplan.
Routability
Initial iterations should focus on routability as the key to achieving a predictable route. Tools
such as module guides, block placements, obstructions, and density screens are used to
control the efficient routing of the design.
To converge on routability, apply these principles of floorplanning:
1. Assess different floorplan styles such as hard macro placement in periphery, island or
doughnut (periphery and island). Keep the macro depth at 1 to 2 for best CTS, IPO, and
DFT results. If possible, consider different aspect ratios to accommodate macro depth.
2. Preplace high speed and analog cores based on their special requirements for noise
isolation and power domains.
3. Review I/O placement to identify I/O anchors and associated logic. Verify that logic
blocks and hard macros which communicate with I/O buffers are properly placed and
have optimal orientation for routability. Push down into module guides to further assess
quality of the floorplan and resulting placement.
4. Review hard macro connectivity and placement based on minimum distance from a hard
macro to its target connectivity.
5. Review the placement of module guides related to datapath and control logic relative to
associated hard macros. Datapath can be a source of congestion problems due to poor
aspect ratio, high fanouts, and large amounts of shifting. Consider tuning the locations
of these module guides and lowering the density to reduce congestion.
6. Review the placement of module guides related to memories. These modules can
typically have higher densities due to the inclusion of the memories.
7. Use placement obstructions around blocks prior to IPO or CTS. Placement generally
does not do a good job of placing cells between macros. Provide sufficient space around
macros for IPO and CTS to add buffers between macros once the blockage is removed.
8. Place module guides when greater control is required. Be careful not to place too many
module guides early in the floorplanning process because this is time consuming and
greatly constrains the placement. Using module guides should be viewed as a
refinement step.
Typical Flow: Review congestion, modify floorplan, and repeat as needed.
loadConfig myDesign.conf
loadFPlan myDesign.fp
amoebaPlace -ignoreScan
scanReorder
As the routability of the floorplan stabilizes, begin reviewing the timing critical path.
Depending on the size of the design, it might be difficult to see the critical path without
proceeding through an IPO.
Timing
It is a good practice to analyze the zero load timing for the netlist
(buildTimingGraph -noLoad). This provides a basis of timing to start from. Zero load
timing is far from being the maximum attainable performance, but it is a good starting point
for the timing closure process.
The other metric worth gathering is the preplacement timing reported by PKS. This process
uses an automated wireload estimation and gives an indication of the validity of the incoming
netlist. These approaches can help to uncover any gross issues with the constraints. If these
trials produce bad timing numbers, there is no point in moving on to placement and
optimization until timing issues are resolved.
To converge on timing, apply these principles of floorplanning:
1. Review the critical paths reported by Encounter and/or PKS and trace them through the
floorplan. Validate that the path takes a reasonable route and does not zigzag across the
chip. Use module guides to gain tighter control over the critical path.
2. Review the placement of module guides to determine if a region or fence constraint is
required to achieve sufficiently tight clustering. Sometimes, critical cells are widely
dispersed from a module guide; a tighter constraint can resolve this.
3. Ensure that there is sufficient area between hard macros for the logic in question. Try
using the Encounter command optCritPath or the PKS command
do_xform_reclaim_area to reduce the logic. You might be able to apply a higher
density and ignore some initial routing congestion.
Typical Flow: Review critical path. Repeat optCritPath as needed.
loadConfig myDesign.conf
loadFPlan myDesign.fp
amoebaPlace -timingDriven -noipo -reorderScan
scanReorder
deleteAllObstructs
optCritPath
Run PKS.
After partitions are created (if the design is being done hierarchically) and a good candidate
placement has been generated, route the design to quantify congestion, routability, and
timing. Remember that congestion does not always equate to DRC violations, but it
sometimes has a more measurable impact on timing due to deviations. By routing (and
extracting) the design and running timing analysis on those results, both routability and
congestion-related timing issues can be solved early in the design process.
Path Groups
It is highly recommended that you use path groups to isolate specific areas of the design. This
helps to assist in uncovering areas that are prone to closure issues and allows the optimizer
to close timing on the rest of the design.
The syntax for the set_path_group command is:
set_path_group -name name -from from_list -to to_list
+----------------------------------------------------------------+
| Path Group Options Report |
|----------------------------------------------------------------|
| PathGroup | Effort | All | Target | Critical | Worst | TEFS |
| | | Pts | Slack | Endpoints | Slack | |
|-----------+--------+-----+--------+-----------+-------+--------|
| default | medium | - | 0.00 | 0/523 | 0.18 | 0.00 |
| ff | low | - | 0.00 | 0/1455 | 3.43 | 0.00 |
| macro_1 | medium | - | 0.00 | 12/57 | -0.69 | -1.20 |
| macro_2 | low | - | 0.00 | 0/26 | 6.96 | 0.00 |
| macro_3 | high | - | 0.00 | 51/55 | -0.53 | -24.40 |
| macro_4 | low | - | 0.00 | 0/3 | 2.57 | 0.00 |
+----------------------------------------------------------------+
The sample path group report was generated after the initial pass of optimization. Paths
related to macro_1 and macro_3 are critical (that is, missing timing). It is important to know
this but it is equally important to know that the rest of the design can meet timing. The nature
of the timing criticality will drive the closure strategy.
For example, a design in which the flop/flop timing is critical and the percentage of critical
endpoints to total endpoints is high is a very different situation to the one above. Those timing
issues would require that you alter the floorplan and/or use module guides during initial
placement. These issues probably wont be fixed through incremental optimization
techniques.
In the above example, the paths to and from macro_1 have a worst slack of -0.69 ns with a
TEFS (total endpoints failing slack) of -1.20 ns. This means that of the 12 critical endpoints,
11 of them have slacks that total 0.51 ns (1.20-0.69). This is an average of 50ps per endpoint
and does not raise much of a concern.
However, macro_3 has 51/55 endpoints missing timing, and the TEFS is almost 25 ns. That
averages to about 0.5 ns per endpoint, which is close to the worst path. This does raise a
concern and warrants some further analysis.
In this case, a possible strategy is the following command sequence:
set_path_group_options macro_3 -all_end_points
foreach group {default ff macro_1 macro_2 macro_4} {
set_path_group_options $group -effort none
}
do_optimize
report_path_group_options
This approach isolates the macro_3 path group for optimization and determines whether the
TEFS can be reduced. The optimizer will stop when the worst path cannot be improved so
the critical paths 2-51 of this path group have not yet been optimized. After optimization, if the
TEFS are significantly reduced, then possibly there is only a minor issue with that path group.
However, if the slack is not significantly reduced, isolating the clock network to the RAM and
using useful skew is probably the only strategy that will work. Alternatively, you could re-place
the design with regions or net weights bt this can be a major setback for large blocks where
the placement and optimization times are long.
To determine if this is a possibility, you need to know the slack margin of the RAM. In other
words, you need to determine the worst case timing to and from the RAM. If all the critical
timing is to the RAM and there is enough margin on the paths from the RAM, then slowing
down the clock to the RAM will help. If all the critical timing is from the RAM and there is
enough margin on the paths to the RAM, then the clock to the RAM must be sped up or the
clock to the critical registers being driven by the RAM must be slowed down. This is a much
more difficult process and might require rebuilding clock trees instead of simply running clock
tree optimization.
Useful Skew
The purpose of useful skew is to borrow slack from one side of a sequential element and lend
it to the other side of that same element. This is typically accomplished by either delaying the
clock to the path end point or by speeding up the clock to the path begin point. For most
optimization runs, useful skew is used after clock tree insertion and design optimization.
A relatively quick way to see if there is an opportunity for useful skew on the critical path is to
measure the slack on each side of the path endpoint:
get_timing [find -pin begin/end_point_pin] slack
To determine the margin for a component like a RAM (with multiple inputs and outputs), use
a script similar to the following:
set macro macro_instance
set worst_input_slack 1000
set worst_input "??"
foreach input [find -hier -pin -input $macro/*] {
if {[get_timing $input clkordata] != "CLOCK"} {
set slack [get_timing $input slack]
if {$slack != ""} {
if {$slack < $worst_input_slack} {
set worst_input_slack $slack
set worst_input $input
}
}
}
}
set worst_output_slack 1000
set worst_output "??"
foreach output [find -hier -pin -output $macro/*] {
set slack [get_timing $output slack]
if {$slack != ""} {
if {$slack < $worst_output_slack} {
set worst_output_slack $slack
set worst_output $output
}
}
}
If there is margin available (difference between $worst_output_slack and
$worst_input_slack), then useful skew can probably improve the worst-case path.
In some cases, both sides of the critical paths might have violations (for example, if the
constraints are not achievable). However, some time could still be borrowed to help the
overall solution. This could hamper useful skew optimizations, but issues can be worked
around through a couple of options. The following example helps illustrate this point.
+----------------------------------------------------------------+
| Path Group Options Report |
|----------------------------------------------------------------|
| PathGroup | Effort | All | Target | Critical | Worst | TEFS |
| | | Pts | Slack | Endpoints | Slack | |
|-----------+--------+-----+--------+-----------+-------+--------|
| default | medium | - | 0.00 | 0/523 | 0.18 | 0.00 |
| ff | low | - | 0.00 | 2400/1455 | -0.25 | 100.00 |
| from_rams | medium | - | 0.00 | 518/2400 | -0.69 | 500.20 |
| to_rams | medium | - | 0.00 | 300/5254 | -0.20 | 101.00 |
+----------------------------------------------------------------+
Note how the register-to-register (ff) and to-ram (to_rams) path groups are in much better
shape than the from-ram (from_rams) paths. In this case, you can reduce the worst-case
paths from the rams at the expense of the to-ram paths and the register-to-register paths
(potentially making their worst-case slack worse).
The first approach is to use the target_slack option to the do_optimize command.
This allows the worst-case slack in the paths to degrade to -0.4 ns while the useful skew
optimization attempts to improve the from-ram paths to -0.4 ns.
A second approach is to use negative clock uncertainty. This shifts the slack positively
instead of imposing the usual negative shift associated with using uncertainty. This approach
creates many more paths with positive slack, and potentially allows the worst-case paths to
improve using useful skew. An example of how this would work is as follows:
set_clock_uncertainty -clock {ideal_clock_associated_with_path} -0.4
This has the effect of shifting the worst-case path slack to -0.29 ns (-0.69 ns (-0.4 ns)) and
shifting the other path groups worst-case slack above 0 ns. In this case, the useful skew can
now directly borrow from the now non-violating path groups to attempt to improve the worst-
case paths.
Once the design is ready to perform useful skew, simply use the command:
do_xform_optimize_clock_tree -useful_skew
The default useful skew command might not be able to improve the worst-case slack. In these
cases, the best approach is to do further optimizations on all end points, and then call useful
skew. If this still does not help, the useful skew optimization can be done in increasing slack
order. This ordering has the effect of relieving violating paths starting with those just violating
up to those with the worst-case path. By relieving the underneath paths, you provide more
flexibility for improving the harder paths.
This flow would look like:
do_optimize -incremental -all_end_points
do_optimize -incremental
do_xform_optimize_clock_tree -useful_skew -increasing_slack_order
do_optimize -incremental
This process can become time consuming on large designs. The process can also be
scripted to iteratively improve the timing by successively reducing the target_slacks.
set current_slack [get_module_worst_slack]
set previous_slack -99999
while {$previous_slack<$current_slack&&$current_slack<0} {
set previous_slack $current_slack
# Shift so worst-case slack at -0.1ns
set_clock_uncertainty -clock \
{ideal_clock_associated_with_path} \
[expr $current_slack+0.1]
do_optimize -incremental -all_end_points
# Shift so worst-case slack at -0.05ns
{ideal_clock_associated_with_path} \
[expr $current_slack+0.05]
set tmp_wc_slk1 [get_module_worst_slack]
if {[get_module_worst_slack]>=$tmp_wc_slk1} {
do_xform_optimize_clock_tree -useful_skew \
-increasing_slack_order
}
do_place -eco
# Unshift the clock
{ideal_clock_associated_with_path} 0
# Get the current slack
set current_slack [get_module_worst_slack]
}
In situations where data transfers between sets of registers and/or memories have easily
isolated clocks (RAMs, registers in module hierarchies and/or partitions, etc.), useful skew
can be inserted during initial clock tree generation. This is done by setting minimum and
maximum insertion delay requirements that define the desired skew. In the following
example, the clock to the DSP core (isolated by buffer dsp_core_clk_i_4194/Y) was delayed
to 50 ps (minimum) and 150 ps (maximum):
set_clock_tree_constraints \
-pin [find -pin dspcore_clk_i_4194/Y] \
-min_delay [expr $avg_insertion+0.05] \
-max_delay [expr $avg_insertion+0.15] \
-max_skew 0.09 \
-max_leaf_transition 0.2 \
-max_tree_transition 0.3
do_build_clock_tree \
-pin [find -pin dspcore_clk_i_4194/Y] \
-move_gated
do_xform_optimize_clock_tree \
-resize_gating \
-pin [find -pin dspcore_clk_i_4194/Y]
The following is a similar example using Encounter CTS. In this case, the critical path was
from RAM to register(s). To give the data more propagation time, the clock to the RAM was
sped up by using a MacroModel statement to create a positive insertion delay on the RAM:
MacroModel pin MEM1/RAM1/CK 700ps 500ps 750ps 500ps 0.2pf
This creates the following situation (for a maximum insertion delay of 1.2 ns):
Critical Path Replacement
Critical path replacement is new functionality available in PKS. It attempts to move
components in the critical path to improve timing when the use of other logical transforms
have failed. There are a few modes to this functionality, but the one deemed to yield the best
results, after several test cases have been analyzed, is the following:
set_global _pks_opt_re_place 2
When this global is set prior to running do_optimize, it causes PKS to attempt replacement
moves early and throughout the optimization process. Below is the result from an example
design. The timing possible after normal optimization is -24 ps. After critical path
replacement, the design meets timing.
Path 1: VIOLATED Setup Check with Pin BIT0_REG/CK
Endpoint: BIT0_REG/D (v) checked with leading edge of 'CK'
Beginpoint: FOUT (v) triggered by leading edge of 'CK'
Other End Arrival Time 942.00
- Setup 100.28
+ Phase Shift 700.00
Mem1/RAM1
Critical
Path
700 ps useful skew
CLK
0.2ns
0.4ns
0.6ns
0.3ns
= Required Time 1541.72
- Arrival Time 1565.56
= Slack Time -23.83
+-------------------------------------------------------+
| Delay | Instance | Instance | Load | Arrival |
| | | Location | | Time |
|-------+----------+------------------+-------+---------|
| | | | 0.03 | 1493.10 |
| 70.15 | PKS797 | (160.82, 277.39) | 0.05 | 1563.25 |
| 2.30 | BIT0_REG | (317.22, 255.25) | | 1565.56 |
+-------------------------------------------------------+
After critical path replacement, the buffer (PKS797) is no longer needed:
Path 1: MET Setup Check with Pin BIT0_REG/CK
Endpoint: BIT0_REG/D (v) checked with leading edge of 'CK'
Beginpoint: FOUT (v) triggered by leading edge of 'CK'
Other End Arrival Time 942.00
- Setup 116.85
+ Phase Shift 700.00
= Required Time 1525.15
- Arrival Time 1504.48
= Slack Time 20.66
+------------------+------------------------------------+
| Delay | Instance | Instance | Load | Arrival |
| | | Location | | Time |
|-------+----------+------------------+-------+---------|
| | | | 0.03 | 1504.39 |
| 0.09 | BIT0_REG | (172.04, 277.39) | | 1504.48 |
+-------------------------------------------------------+
Example Approach
The following procedure illustrates the steps used to achieve timing closure.
1. Optimize the pre clock tree design (using path groups):
a. I/O
b. Register to Register
c. Register to RAM
d. RAM to Register
e. Default (clock gating)
This should be done with a simple do_optimize command using low or medium effort.
Do not spend too much time on this process because the clocks change a lot of things.
Analyze the results and which path groups are the most difficult to close on timing. If
types c or d (to/from RAMs) are the most challenging, useful skew can help significantly.
2. Insert the clock trees. CTS is preferred, but CTPKS can be used, if necessary.
If the to/from RAM paths are the most challenging, attempt to isolate the clocks to the
RAMs from the clocks to the registers. This is a manual process if the netlist does not
already have clock separation built in. By separating the clocks in this fashion, the clock
separation can be tuned to provide a first pass of useful skew (at a much quicker speed).
3. do_xform_optimize_clock_tree -incremental
This command works fairly quickly and does a good job reducing skew/delay/transition
violations. The -asymmetric option can also be used; it is very effective but it takes
more time.
4. Run post-clock optimization with the same path groups
Either use do_optimize or do_optimize -incremental depending on how much
the clock tree changed the results. If the worst-case slack increased significantly, do not
use -incremental. This time the effort can be set higher.
5. do_xform_optimize_clock_tree -useful_skew
This does a relatively quick pass trying to fix the worst-case slack only. If things improve,
use the do_optimize -incremental command to see if further optimization can be
performed.
6. Run the useful skew iteration approach outlined below. This has the ability to squeeze
more performance out of the design, but at a very high cost for run time.
a. Get the worst-case slack.
b. Set the clock uncertainty to a negative number (typically,
worst_case_slack - 0.1).
c. do_optimize -incremental -all_end_points
This removes all the negative slack possible out of the design (between the
worst_case_slack and the uncertainty set in step b). This is time consuming.
d. do_xform_optimize_clock_tree -useful_skew
This does any quick useful skew fixes.
If step d made the worst_case_slack better, then iterate steps b through d,
otherwise go to step e.
e. do_xform_optimize_clock_tree -useful_skew
-increasing_slack_order
This is very time consuming, but helps lower the worst_case_slack by improving
everything underneath, giving room to borrow for the worst paths.
f. Remove the clock uncertainty. If the worst_case_slack is less than or equal to
the target_slack, stop; otherwise, iterate steps a through e.
7. Global route the design.
Use the do_route -timing_driven true option to route the design. Make sure
clock nets are routed first.
8. Perform post-route optimization.
Fix any paths that got non-preferred routing by using do_optimize -ipo.
9. If using WRoute, redo step 7; otherwise, output the DEF/Verilog then use NanoRoute to
route the design and perform extraction.
10. If more problems exist after extraction, repeat steps 8 and 9.
Index
A
Amoeba placement
hierarchical floorplan generation
flow 38
virtual prototyping flow 30
B
BG/PKS
logical synthesis and scan insertion 22
bump placement
flip chip 28
C
CCAR
routing (Tcl script) 150
CeltIC
block implementation flow 48
chip assembly/signoff flow 63
description 14
Clock Tree Synthesis (CTS)
physical optimization sub flow 74
top-level implementation flow 55
congestion optimization
crosstalk prevention
slew balancing
CTE
CTE timing analysis
chip assembly and sign-off flow 62
D
DEF
output of Block Implementation Flow 44
output of Top-Level Implementation
Flow 52
version used 17
density screen (blockages) 29
E
Echo noise model
F
Fire & Ice (QX)
chip assembly flow 62
description 14
First Encounter
description 14
flip chip
bump placement 28
Flow Steps
Block Implementation 46, 74, 76
Chip Assembly and Sign-Off 62
Chip Finishing 68
Hierarchical Floorplan Generation 38
Logic Synthesis and Scan Insertion 22
Top-Level Implementation 54
Virtual Prototyping 28
G
GDSII
chip finishing flow 68
Flow 52
GDSII (block)
output of Chip Assembly and Sign-Off
Flow 60
GDSII (top-level)
Flow 60
I
IPO
hierarchical floorplanning flow 39
virtual prototyping flow 31, 32
IR drop analysis
using Voltage Storm 14
J
JTAG cells
JTAG/BIST
logical synthesis flow 22
L
LEF
version recommended 17
library formats
list of 17
M
MSV
See multiple supply voltages 29
multiple supply voltages
N
NanoRoute
description 14
NC-Verilog
output of chip assembly and sign-off flow
(SDF file) 63
Noise model
O
OpenAccess
block implementation flow 49, 57
Flow 60
P
pads
I/O, power, and ground
refine I/O, power, and ground
parasitics extraction
floorplan refinement flow 39
hierarchical floorplan generation
flow 38
virtual prototyping flow 30, 31, 32
partitions
committing 39
saving 40
power analysis
Power model
power rings
power stripes
R
RC
RTL Compiler 22
routing
CCAR (Tcl script) 150
RTL Compiler
logic synthesis flow 22
RTL to GDSII
overall flow procedures 15
S
scan chain reordering
block implementation 46
scan chains
logical synthesis flow 22
SDC
Synopsys Design Constratints 17
SDF (Verilog)
Flow 60
SDF file
NC-Verilog output in chip assembly and
sign-off flow 63
Signal Integrity (SI)
SignalStorm
slew balancing (crosstalk prevention)
SPEF
Flow 52
T
Tcl scripts
block implementation 108
chip assembly / sign-off 168
chip finishing 176
hierarchical floorplanning 102
logical synthesis and scan insertion 87
top-level implementation 137
virtual prototyping 88
TLF
timing libraries 17
TLF model
V
Verilog
output of chip assembly and sign-off flow
(SDF file) 63
VoltageStorm
description 14
for IR drop analysis 14

Flow DW

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Design Flow Guide

Physically Knowledgeable Synthesis (BG/PKS) commands.

tool to perform an equivalence check.

tool to perform an equivalence check.

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