heat that drives a chemical reaction in which OH- radicals from the NaOH oxidize

the silicon. The SiO2 particles abrade the oxide away. Slurry consists
of nano- particles (10nm SiO2 or Al2O3) and chemicals (NaOH).
Why do we want SOI wafer? parasitic-- ; speed++ Better isolations between devices: prevent latchup
Si Photonics latch-upSOI Wafer Manufacturing SIMOX (Separation by IMplantation of Oxygen)
Wafer bonding/Smart Cut
SIMOX was invented earlier.
Wafer bonding is more popular now.1. Silicon crystal structure and defects.
2. Czochralski (CZ) single crystal growth.
3. Float zone single crystal growth and doping.
4. Wafer fabrication.
5. Measurement methods.
Crystal growth, wafer fabrication and basic
properties of silicon wafers
Hot probe measurement of carrier type
The hot probe technique is used to determine the type of dopant in a wafer.
It relies on the generation of the Seebeck voltage (open circuit), i.e. the diffusion
of free carriers (electrons or holes) as a result of a temperature gradient.
The sign of the voltage tells the carrier type.
Alternatively, one can measure the current direction (short circuit).
The current that flows due to the majority carrier is given by
Pn is thermoelectric power, negative for electrons, positive for holes.
Electrical measurement techniques four point probe
The four point probe method measures the resistance/resistivity of a wafer.Using values of carrier mobility, one can calculates the carrier concentration.
Use four points (rather than two) to eliminate the effect of contact resistance. =(en) 1, ismobility, n is carrier density.
Why can four point probe eliminate contact resistance? No current on voltage
probes.
Hall voltage (VH) measurement
Silicon is placed inside a magnetic field and the resultant motion of charge will experience a force perpendicular to the electric field. F=qvB
In equilibrium this results in a transverse potential difference known as the Hall
voltage VH. (such that F=qE=qVH/w=qvB, i.e. forces are balanced, so VH=vBw)
The magnitude and sign of the Hall voltage leads directly to the carrier concentration,
type, and mobility (if the resistivity is known).
Current density j=I/tw=E/=qnv, VH=vBw=(I/twqn)Bw=IB/ t qn.
Hall coefficient RH VHt / BI=1/ qn=H, H is Hall mobility (we know that =1/ qn).
( is slightly lower than conductivity mobility, due to more scattering when Hall measurement of carrier type & mobility
Thickness of the slab is t (along B direction), width is
w (along VH direction). VH is measured, and used to
calculate RH. Then carrier
concentration p, n=1/ qRH.
Ion implantation: gas ionized, ions accelerated by a high electric field(damage to lattice), and injected Thermally
activated (600-1100C) Ion: P, As, Sb, B, In, O: Dose: 1011 - 1018 cm-2 ; Ion energy: 1 - 400 keV ;
Uniformity and reproducibility: 1% ; Temperature: room temperature; Ion flux: 1012-1014 cm-2s-1
Dose ()= # of atoms/cm2.; Concentration (C) = # of atoms/cm3.
Old: diffusion-bulk gas source top of surface, or pre-deposited chemical source on wafer surface.
Advantage:
Not limited by solid solubility; doping uniformity; Flexibility, control in peak depth and spread range- breadth(lateral
diffusion) of spread but as long as they are small as deep implant not possible, precise control on Dose;
Low-temperature process (can use photoresist as mask but
masking materials can be knocked into the wafer creating unwanted impurities,
or even destroying the quality of the interface.)
Wide selection of masking materials, e.g. photoresist, oxide, poly-Si, metal
Less sensitive to surface cleaning procedures.
Very fast (6" wafer can take as little as 6 seconds for a low and moderate dose), slow for high doze values.;
Complex profiles can be achieved by multi-energy implants.
The ion implanter forms a simple electrical circuit. By monitoring the current in the circuit (or by a monitoring circuit with Faraday cups), significant accuracy in the implanted d
ose can be maintained. ; High dose introduction is not limited to solid solubility limit values.
Disadvantage: Done in high vacuum, it is a very clean process step.; Very expensive equipment ( $1M or more). ;
At high dose values, throughput is less than diffusion (chemical source pre-deposition on surface). ; Ions damage the semiconductor lattice. Not all can be corrected by
annealing.; Very shallow and very deep doping are difficult or impossible. ; Masking materials can be knocked into the wafer creating unwanted impurities,
or even destroying the quality of the interface. During high temperature steps after implant (most commonly an activation anneal),
the implanted impurities will begin to diffuse, broadening the implantation profile. End of Range EOR lattice damage
which might evolve from simple point defect into complex dislocations TED is the biggest single problem with ion implantation
Schematic of Ion Implanter because it leads to huge enhancements in dopant diffusivity and difficulty in achieving shallow junctions.
Ion source: operates at a high voltage and convert the electrically neutral dopant atoms in
the gas phase into plasma ions and undesired species. Some sources: Arsine, Phosphine,
Diborane, Solid can be sputtered in special ion sources.
Mass separator: a magnet bend the ion beam through right angle, and select the desired
impurity ion and purge undesired species. Selected ion passes through an aperture.
Accelerator: add energy to beam up to 5MeV. (contained, to shield possible x-ray).
Scanning system: x and y axis deflection plates are used to scan the beam across the wafer
to produce uniform implantation of desired dose. The beam is bended to prevent the
neutral particles from hitting the target .
Ion Current will give idea of no of doped ions in the sample.
ION EXTRACTION
Positive ions are attracted to the exit side of the source chamber, which is biased at a large
negative potential with respect to the filament.
Filament emits electrons, which are accelerated to gain enough energy.
The electrons collide with the molecules or atoms, and ionize them.
The ions are extracted, rough-focused, then travel toward the magnetic analyzer.
(extraction)
Select Implantation Specie:
Only one mass will have exactly the correct radius of curvature to exit the source through the slit.
Dopant gas containing desired species, BF3, BCl3, B2H6, PH3, AsH3, AsF5. If using solid or liquid source, they need to
be heated to vaporize . Plasma provides positive ions, (B11)+, BF2+, (P31)+, (P31)++.
Drawback
NEUTRAL TRAP
There may be ions that collided with other ions in the beam, undergoing a charge exchange.
Neutrals are highly undesirable since they will not be deflected in electrostatic end-station
scanning mechanisms and so do not follow the beam, but instead strike a beam stop.
Neutrals are not deflected. The ions are sufficiently deflected by the plates to continue to travel down the tube.
To avoid this problem, most systems are equipped with a bend, i.e. parallel plates of an
electrostatic deflection system. Beam scanning good for low dose
For high dose: Mechanical Scanning but drawbacks
Excellent wafer cooling needed. Substantial load/unload time.
15 - 25 wafers /disc. Excellent throughput for high dose implants.
High current (20mA) Scan speed adjustment to insure uniform dose.
Practical implantation dosimetry (dose measurement)
Q*t=Dose*Cup Area
Two Positive Polarity Faraday Cup removes Secondary Electron Effect
Dopant Impurity Profile Approximated by Gaussian Distribution for first order
approximation.
Rp= projected range, is a function of ion
energy and mass, and atomic number
of impurity as well as target material.
Delta Rp =straggle = standard deviation.
Np = peak concentration at x=Rp.
Dose Q=N(x)dx=((2PI )^1/2)Np( Delta Rp)
In textbook, C is used for concentration, to
replace N used here.
Mi and Mt are the masses for incident and target ion.
Junction depth in Si Junction formation by impurity
implantation. Two pn junctions are formed at xj1 and xj2.
Implant into Si already doped at NB.
E.g. implant P into Bdoped Si.
P: n-type doping; B: p-type.

doping profiles other than the simple Gaussian are required.
implantations far away from the surface and for reasonable short characteristic
diffusion lengths, the new profile can be approximated by:
Sometimes Softwares used to curve out implantation distribution
Simulation software: SRIM - The Stopping and Range of Ions in Matter
How are drain and self aligned source formed today?
Implant only certain part of the wafer by a mask such that its Rp lies within the mask material.
Unfortunately lateral spread still happens; In order to act as an efficient mask, the
thickness of the mask should be large enough that the tail of the implant profile in
the silicon should not significantly alter the doping concentration.
How thick mask is needed? Rule of thumb: good masking thickness; Xm = Rp + 4.3Rp, C(x=Xm)/C(x=Rp) ; order equal to 10-4.; Better way: using simulation software.
Mask Material ; Photoresist is commonly used as implant mask. Resist may flow or be baked. 1. Outgassing: Heavily implanted resist layers often break apart organic
molecules have a hardened carbonized Layer post H2 released near surface difficult to remove later on. The outgassing can raise the pressure in the end
station sufficiently to cause neutralization of ion beam through impact with the H2 molecules, resulting in significant dose rate errors.
Resist damage at high implant currents ---------------
BF2 + implant at 80A in Varian 400 without a water cooled chuck (water cool can reduce the problem)31Mask material thickness
Lateral scattering
The implanted ion also scatter laterally around the impact point, which can also
be approximated by Gaussian distribution with transverse straggle RT.
2-D formulation of implantation profile
Monte Carlo simulation of many ions into Si
Occur when ion velocity is parallel to a major crystal orientation.
Some ions may travel considerable distances with little energy loss. 2D Formulation of Implantation Profi
Once in a channel, ion will continue in that direction, making many glancing
internal collisions that are nearly elastic (their stopping is then dominated
by electronic drag only), until it comes to rest or finally dechannels. The
latter may be result of a crystal defect or impurity.
LOOKING INTO Si AT DIFFERENT ORIENTATION ------- Occur when ion velocity is parallel to a major crystal orientation.
Some ions may travel considerable distances with little energy loss.
Once in a channel, ion will continue in that direction, making many glancing
internal collisions that are nearly elastic (their stopping is then dominated
by electronic drag only), until it comes to rest or finally dechannels. The
latter may be result of a crystal defect or impurity. Impurity Dis due to this effect








Methods to reduce channeling effect 1. thin screen oxide which is amorphous is often used, or make Si layer amorphised by exceeding critical implant
dose causing some randomization of incident beam before it enters the lattice.
Most IC implantation is done off axis.
2. A typical tilt angle is 7o.
3. Destroy the lattice before implantation
High dose Si+ implantation to convert the surface layer into
amorphous Si. After exceeding critical implant dose. Heavy atoms
will form critical implant dose early
4. Implantation of desired dopant
Ion substrate interaction
The ions are stopped at random positions,
mostly not in crystalline
sites, so not active as dopant
(need anneal to active them).
Ion implantation energy loss mechanisms Nuclear stopping Energy Loss, crystalline Si
substrate damaged by collision. Electronic stopping energy Loss, electronic excitation creates heat.
Total energy loss is the sum of the two processes.
Nuclear stopping power: Coulomb scattering (does most damage)(dominates at low velocity)
As fast particle have less interaction time with the scattering nucleus, the nuclear energy loss
is small at very high energies/velocity.
Thus the nuclear energy loss tends to dominant towards the end of the range when ion has
lost much of its energy and where nuclear collisions produced most of the damage.
Light ion slowed down at the end of range
Heavy ion is slow (v M1/ 2), more loss at the start of movement.
There are also inelastic collisions that transfer energy.
Electronic stopping power(dominates at high velocity) (does less damage)
also Coulomb interactions, but inelastic
Nonlocal: ion experiences drag due to free or polarizable electrons.
Local: passing ion causes internal electronic transitions => energy and moment transfer
Because electrons can follow fields up to optical frequencies (velocities of 105 m/s - 100
times faster than phonons), electronic losses dominate at higher
ion velocities.
Electronic and nuclear stopping power

EOR damage

Damage at end of range (EOR) nuclear damage
The main disadvantage of ion implantation is the production of
lattice damage (vacancies and interstitials, or V/I) which may
evolve from simple point defects into complex
dislocations or voids.
Solution to Problem? Most damage can be repaired by annealing. However, annealing cycles of 30 min at close to
1000oC can cause considerable spreading of the implant by diffusion.
47(Si)Si-> Si Interstitial + Si Vacancy
Damage to the lattice: target atom displacement
Energetic incident ions collide with target atoms, leading to their displacement.
The result is an interstitial atom and a vacancy, V-I pair = Frankel defect.
The displaced atoms may have energy high enough to further displace other
target atoms along its path.Ed is the minimum energy required to break four covalent
bonds and dislodge a lattice atom.
Number of displaced target atoms
Ed is called threshold energy
or displacement energy (for Si, Ed15eV).
For example, 30keV As ion will lead to roughly 1000 displaced
atoms.(More is the damage due to nuclear energy loss). The number will be less for 30keV light ions, whose energy is mainly lost by electronic stopping.(Electronic loss little
daamage) For light ion (lighter than target), small energy transfer to target atom for each collision, generate few displaced target atoms, and ion
scatted at large angle. Low density non-overlapping damage, but over large area with a saw-tooth shape.For heavy ion, large energy transfer for each collision, small scatter an
gle. The displaced atom can further displace other target atoms. Small range, large damage density over small volume.

Annealing 900oC, 30min: repair damage and activate dopants. After implantation, we need an annealing step, usually under Ar, N2 or vacuum.
Restore silicon lattice to its perfect crystalline state - silicon atoms can move back into lattice sites at these temperatures.
Put dopants into Si substitution sites for electrical activation - nearly the entire implanted dose becomes electrically active except for impurity concentrations >>10^19/cm3.
Restore the electron and hole mobility now that the lattice becomes perfect again.
Annealing and Solid Phase epitaxy (SPE): Restoring crystal structure-- when substrate has been rendered amorphous, the crystallinity is repaired by SPE, where crystal reforms
using the underlying undamaged substrate as a template. Most of impurities are incorporated into the growing lattice .
If the substrate is amorphous, it can re-grow by solid state epitaxy (SPE).
Due to the high activation energies required to annihilate defects (5eV), it is often easier to regrow the crystal from an amorphous layer via SPE
(activation energy 2.3eVin Silicon) than it is to anneal out defects. Thus, two schemes for implants are used: Implant above the critical dose and use low temperature
anneal to regrow material. Implant below the critical dose and use high temperature anneal to get rid of defects.

transient enhanced diffusion (TED). Stable defects formation near a/c-amorphous/crystalline interface
But, the tail of the damage beyond the a/c (amorphous/crystalline) interface can nucleate stable, secondary defects (defects caused directly by implanted ion are primary defec
ts), and cause transient enhanced diffusion (TED). TED is the result of interstitial damage from the implant enhancing the dopant diffusion for a brief transient period.
It is anomalous diffusion, because profiles can diffuse more at low temperatures than at high temperatures for the same Dt. TED is the biggest single problem with ion
implantation because it leads to huge enhancements in dopant diffusivity and difficulty in achieving shallow junctions. Physically based understanding of TED has led
to the methods to control it (rapid thermal annealing, or RTA).




Intrinsic diffusivity Di; E.g. at 1000oC, ni=7.141018/ cm3.
Intrinsic: impurity concentration NA, ND < ni
Note that ni is quite high at typical diffusion temperatures, so "intrinsic" actually applies under many conditions.
Solve TED by Rapid thermal processing/annealing

Dopants can diffuse during high temperature anneal (activation energy 34eV) Activation energies of defects annihilation (~5eV) > the activation of diffusion. That
means annihilation speed increases faster with temperature. To minimize this unwanted diffusion, high temperature short time annealing is
preferred. Rapid Thermal Processing (RTP) or Rapid Thermal Anneal (RTA) is used. RTA is extremely important for shallow junction devices.
Rapid heating source:
high power laser
electron beam
high intensity








Wet oxide: thick <2.5 m, good insulator, for field oxides or masking. Thick; less dense ; Quality suffers due
to the diffusion of the hydrogen gas out of the film, which creates paths that electrons
can follow. Advantage: higher growth rate than dry oxidation. Reason for higher rate: much larger solubility in oxide
(Henrys constant H) for H2O compared with O2. C*(bulk concentration, =HPG) for H2O: 3x1019/cm3; and for O2:
5x1016/cm3.
Disadvantage: oxides grown wet are less dense, with a more open structure, because out-diffusion of H2 creates
voids along its path. Thus wet oxidation is typically used when a thick oxide is required that will not be
subjected to any significant electrical stress that may lead to electrical breakdown.
H2O has much higher solubility in SiO2. The it is easier for mass transport to the SiO2/Si
interface for the reaction, so faster growth rate.
Dry oxidation: slow, higher quality than wet oxidation, used for gate oxide.
Note that dry oxidation appears to always have some initial oxide present (i.e. xi0).
Surface profilometry (Dektak): mechanical thickness measurement ---------------

Oxide thickness for constructive interference (viewed from above =0o)Xo=k*Lambda/2n, n=1.46,
k=1, 2, 3
Film thickness (nm)









3. Deal-grove model (linear parabolic model). D-G model is applicable for: oxidation on flat un-patterned surface, lightly doped substrates, using simple O2
or H2O ambient, and when the oxide thickness is larger than about 30nm.

O gets in or Si gets out for reaction?
Considering dry oxygen molecules as the oxidant species, by radio active tracer, it has been shown that oxidation proceeds by inward movement of O2 molecules
through SiO2 to the Si SiO2 interface where the reacon Si(solid) + O(gas) SiO2 takes place. This forms a contrast with the case of Copper whose
oxidation proceeds by the outward motion of the metallic ion and also with the case of anodic oxidation of silicon, where silicon moves outward.

Then the oxidation rate R (F is flux, F=F1=F2=F3=KSCI, unit is number/(s*cm^2); unit for R is cm/s).
Assume N1 as the number of oxidant molecules incorporated per unit volume of oxide grown.
X is thickness and t is time, tox is thickness of oxide


















hg is mass transfer coefficient in cm/sec.
Models to explain the excess growth of thin oxidation n electric field exists across oxide that enhances diffusion (if diffusing species is O2
ut it is not.) during early states of oxidation.
Thin micro-channels in oxide aid in the movement of O2 to the Si surface. Mismatch in thermal expansion coefficients of oxide and Si causes stress in oxide
and this stress may enhance the diffusivity of the oxidizing species. But NONE of these mechanism gained wide acceptance. The exact mechanism is still unknown.

For Xo>>7nm, Massoud model
approaches DG model.
Oxidation rises with temp as well as pressure

Dependence on crystal orientation
Oxidation rate depends on the availability of reaction
sites on the silicon substrate.
Oxidation on the <111> crystal
plane occurs at a higher rate
because there are a higher
number of surface atoms/chemical bonds than the<110> which is in turn greater than <100> plane.

KS0 is a constant, roughly proportional to the number of available Si bonds for reaction per unit area.
Interface reaction rate constant Ks (cm/sec) depends on crystal orientation.
So the liner grown rate B/A depends on crystal orientation. (B/A)111= 1.68 (B/A)100
The parabolic rate constant B is NOT dependent on crystal orientation. With Cl addition, dopants of Si in high conc. and Temperature both B/A and B increases
The effect is particularly important at lower temperatures and for thinner oxides, and is more important for N+ doping than P+ doping.
The oxidation rate depends on:
The Cs dopant concentration in SiO2 for diffusion controlled oxidation (B dominates).
The C0 dopant concentration at Si surface for reaction controlled oxidation (B/A dominates).
-- Peculiarly this effect dont keep on increasing but decreases for high temperature and/or
long time oxidation when oxide become thick.
Phosphorous piles up at Si surface, leads to more vacancies in Si (oxidation process need
space/vacancies), enhances oxidation rate in the reaction controlled regime (increase ks).
In this case
Linear rate coefficient B/A increases rapidly for surface doping levels greater than 1020/cm3.
Parabolic rate coefficient B shows only modest increases.
Effect of Diffusion on Doping Boron: B segregates into oxide, weakens SiO2 bond structure, increases oxidant diffusivity D. B increases rapidlyWhy
Si<100> is used??
Qf<111> : Qf<110> : Qf<100>=3 : 2 : 1
This is one of the reasons why IC uses <100> Si.
The other reason is that the mobility is high

Two dimensional oxidation( More bonds more oxidation, more radius more oxidation)
Oxidation is slower for convex or concave corners.
Concave corner is even slower than convex corner.
The smaller the curvature radius is, the slower.
More serious for low temperature oxidation, no effect for high temperature
1200oC (when oxide can flow).

Stress due to Volume Expansion(Causes more of Activation Energy Requirement.)
Stress due to volume expansion (we know when Si oxidizes, it expands). As the oxide
grows, the newly formed oxide pushes out the old oxide which
rearranges itself through viscous flow. Stress occurs typically on curved
surfaces.

Oxidation Rate after Chlorine Addition Addition of Cl (1-3%) bearing species to oxidation ambient leads to: faster oxide growth.
Both B/A and B increases, because bond energy of Si-O is 4.25eV, Si-Cl is 0.5eV, so Cl2
reacts with Si first to form Si-Cl, which then reacts with O2 to form SiO2. Cl2 is a kind of catalyst.
Cleaner oxide, less metallic contamination, since Cl is a metal getter. Most heavy metal atoms react with Cl to form volatile metal chloride.







Interface trapped charge (Qit): located at Si/SiO2 interface. Energy of those interface states are within the band gap, so Qit can be +, - or neutral, depending on bias voltage.
(i.e. those states can be filled with e- or h+) result of structural defects due to the oxidation process, metallic impurities, and bond-breaking (dangling bond Si).
It has the same origin as Qf(incomplete oxidation) , so high Qf always means high Qit. Low oC H2 (forming gas, 10% H2 + 90%N2) anneal at 400-450oC after
metallization process effectively neutralizes most interface-trapped charges-Qit--
Fixed oxide charge (Qf): positive charge located within 3nm of Si/SiO2 interface. incomp. Oxidn; small for high oC; Cl++ causes Qf--; fast cooling small Qf;
Qf<111> : Qf<110> : Qf<100>=3 : 2 : 1; Qf cannot be charged or discharged easily (unchanged during device operation), and it is reproducible/predictable.
Oxide trapped charges (Qot): associated with defects in the SiO2. may be positive or negative, due to holes or electrons being trapped in the bulk of the oxide.
It is caused by broken Si-O, Si-H or Si-OH bonds, due to ionization irradiation and other energetic processes during evaporation (generate x-ray for e-beam
evaporation), sputtering (plasma), RIE and ion implantation. They can be annealed out by low-temperature (300oC) treatment in H2 or inert gas.
1000oC dry oxidation improves oxide structure and make it less susceptible to irradiation. Oxide can also be protected from irradiation by covering with Al2O3 and Si 3N4
that are resistant to irradiation. It received more attention in recent years because, as the device shrinks, the electric field within the oxide is increased.
The high field may cause electrons to inject to the traps in the oxide (charge trapping), which shifts the threshold voltage.
Mobile ionic charges (Qm): result from contamination from Na or other alkali ions, K, Li, - ions and heavy metals originate from processing materials, chemicals,
ambient, or handling. It can be anywhere in the oxide layer, can move at high temperature or bias voltage.an shift MOSFET threshold voltage and cause device stability problems.
Common techniques employed to minimize Qm include:
o Cleaning the furnace tube in a chlorine ambient
o Addition of cl-containing gas during oxidation
o Gettering with phospho-silicate glass (PSG) to replace quartz tube
o Using masking layers such as Si-3N4 to prevent the contaminants from getting into the oxide.
It was a big problem in 1960s, nowadays no longer a serious issue.
That was why Si MOSFET couldnt be made in the early days.

SEGREGATION COEFFICIENT : Two additional factors influence the redistribution process:
o The diffusivity of the impurity in the oxide (if large, the dopant can diffuse
through the oxide rapidly, thereby affecting the profile near the Si-SiO2 interface).
o The rate at which the interface moves with respect to the diffusion rate.







>30A DGmodel, <30A RTO
Rapid thermal oxidation (RTO) Conventional thermal oxidation for gate oxides < 30 must be performed
at < 800C, which increases Si/SiO2 interfacial roughness and reduces channel mobility.
Solution: RTO at around 1050C using radiation heating source, time can be < 1min.
RTO also reduces dopant re-distribution.
RTO may be influenced by both thermally activated processes and a photon-induced
process involving mono-atomic O atoms generated by UV, thus creating a parallel oxidation
reaction that dominates at lower temperature.
RTO growth kinetics exhibit activation energies differing from conventionally grown oxides.
In the initial stage (20seconds), the RTO growth rate is linear followed by nonlinear
growth. Duration of the linear region is hardware dependent, particular the heating source.
TSUPREM4
SUPREM: Stanford University PRocess Engineering Model TSUPREM4 is a commercialized version of SUPREM from Synopsis It is a computer program for simulating the processing
steps used in the manufacture of silicon integrated circuits and discrete devices. TSUPREM4 simulates the incorporation and redistribution of impurities in a two-dimensional
device cross-section perpendicular to the surface of the silicon wafer. The output information provided by the program includes:
Boundaries of the various layers of materials in the structure
Distribution of impurities within each layer
Stresses produced by oxidation, thermal cycling, or film deposition
Conformal/Good Step Coverage: good for electrical connection
Non Conformal/Poor Step Coverage: good for lift off; caused by evaporation
Thin film deposition processes

Physical vapor deposition (PVD)
o Evaporation/vacuum Deposition
o Sputtering
Chemical vapor deposition (CVD)
oAtmospheric Pressure CVD
oLow pressure CVD
o Plasma enhanced CVD
oAtomic layer deposition (ALD)
Epitaxial deposition
o MBE (molecular beam epitaxy)
o MOCVD (Metal-Organic CVD)
Lower HF etch rate means better film quality (denser film)
In PVD, chemical reactions are not involved, except for reactive (add reactive gases into chamber) evaporation or reactive sputter deposition,
which are not widely used.
Evaporation(Line of S & Shadow Ef. Control more than sputtering)(Thermal(1600oC)-directional-more contamination or e beam(3000oC) less directional less
contamination)/vacuum deposition/fast((>1micrometer/min possible)/poorfilm/popular in thin film deposition by nanofab. Involving easy lift off/non conformal
coverage./SharonThermalEvaporator//little gas in film//large grain size//fewer grain orientation//poor adhesion
High sticking coefficient (at low T, adatom stays wherever it hits with limited surface migration), leading to poor conformal coverage/significant shadow.
But this also makes evaporation the most popular thin film deposition for nanofabrication using liftoff process. Material source is heated to high temperature in vacuum
(P < 10^-5 Torr) either by resistive,thermal or e-beam methods. High vacuum is required to minimize collisions of source atoms with background species (light of site deposition)
Material is vapor transported to target in vacuum. Film quality is often not as good as sputtered film .The film thickness can be monitored precisely using a quartz balance
This is necessary as the deposition is not reproducible (tiny change in T leads to large change of deposition rate. T is not monitored, power is.
Deposition rate is determined by emitted flux and by geometry of the source and wafer. For microfabrication R&D, evaporation is as important as sputter deposition.

Sputter deposition/non vacuum deposition-self sustained glow discharge /slow/good_film/popular in industry used/used for insulators /shadow effect (the reverse
of sputter etching) composite material -good(that involves energetic bombardment of ions to the as-deposited film, which makes the film denser)//gas in film//small grain
size//many grain orientation//better adhesion//micro thin film growing fabrication
Material is removed from target by momentum transfer. Gas molecules are ionized in a glow discharge (plasma), ions strike target and remove mainly neutral atoms.
Sputtered atoms condense on the substrate. Not in vacuum, gas (Ar) pressure 5-50mTorr.


Low pressure more mean free path, slow rate of deposition







Arrival Ratio: at 1nm/sec deposition rate, ratio of molecular vapor arrival
to molecular impact of residual gas.



Thermal evaporation(ebeam Eva)
Widespread use for materials whose
vapor pressure can be reasonable at
1600oC or below. (
high temp of melting)
Contamination Problem(Evaporation
occurs at a highly localized point on
the source surface, so little
contamination from the crucible
) (as only small source area heated to very high T)
Eddy current, joule heating(No contamination
As focused electron beam to heat and
evaporate metals)
Common evaporant materials:
Au, Ag, Al, Sn, Cr, Sb, Ge, In, Mg, Ga;
CdS, PbS, CdSe, NaCl, KCl, AgCl, MgF2,
CaF2, PbCl( W, Ta, )
Materials are evaporated from
heated crucible (resistance heating).
Suitable for high vapor pressure
metals, e.g. Au, Al,(High melting point metals)
Good for organic materials (organic
semiconductors)( not suitable for organic materials. But good for metals and dielectric)
Has deposition Uniformity (Thickness uniformity poor but can be improved by substrate rotation.)
Deposition Rate : 1-20A/s(10-100A/s)
Temp: 1600oC(3000oC)
Cost:Low(High)
Typical filament currents are 200-300 Amperes.
Simple, robust, and in widespread use. (More complex, but extremely versatile, virtually any material).
Good for MOSFET(Since x-rays producing both primary and secondary e will damage substrate
and dielectrics (leads to trapped charge), e-beam evaporators cannot be used in MOSFET.
Major issues
O High contamination level Substrate is exposed to IR Radation(Radiation damage)
Exposes substrates to secondary electron radiation. X-rays can also be generated by
y high voltage electron beam.
o Cant work on composite films(XaYb)( Composite films can be deposited using
dual e-beams with dual targets)
o Limited choice of materials(More complex, but extremely versatile, virtually any material).
High contamination: the crucible is heated as well, so may deposit to the substrate.
On the contrary, e-beam evaporation heats only the evaporate material from the top.
Residual stresses: usually of CTE and micro-structures transformation. (CTE:
coefficient of thermal expansion)

Background vacuum pressure can cause deposition Uniformity
Shadowing effect at wafer edge makes lift off difficult.

Evaporation advantages: Films can be deposited at high rates (e.g., 1m/min, though for research typically < 0.1m/min).
Low energy atoms (~0.1 eV) leave little surface damage. Little residual gas and impurity incorporation due to high vacuum conditions.
No or very little substrate heating.
Limitations:
Accurately controlled alloy compounds are difficult to achieve. No in-situ substrate cleaning. Poor step coverage (but this is good for liftoff).
Variation of deposit thickness for large/multiple substrates has to rely on quartz crystal micro-balance for thickness monitoring. Xray damage.

Evaporation is the most useful thin film deposit techniques for nanofabrication,
because:
o It is directional (poor step coverage), good for liftoff.o It is directional, good for shadow evaporation.o The film thickness can be
monitored precisely using a quartz crystal monitor.

Variation of deposit thickness Thickness Measurement : Quartz Crystal Micro-balance (QCM): (similar idea to quartz clock)
Quartz is a piezoelectric material. With a high frequency AC voltage activation, the amplitude of vibration is maximum at resonance frequency.
This resonance frequency will shift when film is deposited on its surface. Thus by measuring frequency shift f, one can measure film thickness
with sub- accuracy. Variation of deposit thickness for large/multiple substrates has to rely on
quartz crystal micro-balance for thickness monitoring.

Evaporation issues: alloy evaporation
Stoichiometrical problem of evaporation: Compound material breaks down at high temperature. Each component hs different vapor pressure,
therefore different deposition rate, resulting in a film with different stoichiometry compared to the source.One solution is co-evaporation
(use two e-beam guns).This again leads to shadow effect.

Poor step coverage could be useful. Shadow/angle evaporation is routinely used for nano-electronics fabrication.

Shadow evaporation: for non conformal shape and easy lift off.
The pictures above show shadow-masks for
niobium rings containing a Josephson
junction, prior to evaporation.
The metals are evaporated under different
angles without breaking the vacuum.
The mask consists of Germanium while the
sacrificial layer below the mask is made of
high temperature capable plastic (polyether
sulphone).

GLAD (glancing angle deposition): self assembly of film
Angle >80o, with (or without) substrate rotation.
Self assembly mainly due to shadowing effect that
magnifies the otherwise grain structures.










Sputtering (overview)
Sputter is carried out in a self-sustained glow
discharge (plasma).not vacuum
Heavy inert gas is the major carrier, e.g. Ar.
Reactive chemical species (e.g. O2 to
deposit oxide) may be introduced
reactive sputtering
The ionized atoms bombard the target and
cause the transport of sputtered atoms onto
the substrate.
Sputtering process can be run in DC or RF
mode (insulator must be run in RF mode)
Major process parameters:
o Operation pressure (~10-100mTorr)
o Power (few 100W)
o Substrate bias (in addition to self-bias)
o Substrate temperature (20-500oC)
Dielectric materials can also be deposited, but are usually formed by sputtering
metals in O2 , N2, CH4 gases, forming AlN, Al2O3, TiN, TiC
A wide range of industrial products use sputtering: CD,LCD, computer disks, hard
coatings for tools, metals on plastics.

Advantages:
o Able to deposit a wide variety of metals, insulators and composites & dielectric.
o Replication of target composition in the deposited films.
o Capable of in-situ cleaning prior to film deposition by reversing the potential on the electrodes .
o Better film quality dense and step coverage than evaporation, preferred deposition technique for micro-fabrication (semiconductor
industry).(nano fab thin film for R&D by evaporation)
Sputter yield: the number of sputtered atoms per impinging ion. SY increases with ion Energy Ion energy, spuering yield
Thus, 95% of incoming energy goes to target heating & secondary electron.
Can be used as etching method
The ion impact may set up a series of collisions between atoms of the target, possibly leading to the ejection of some
of these atoms. This ejection process is known as sputtering.Here we are interested in sputter deposition. Of course sputter can also be used as an etching method (the substrate
to be etched will be the target), which is called sputter etching.
Sputter increases with ion mass.

Disadvantages:
o Substrate damage due to bombardment
Slow rate of deposition but Ion energy, spuering yield
High rate sputter processes need efficient cooling techniques to avoid target damage from overheating.

ALLOY Better Compared to Evaporation where Alloy has stoichiometry problem
Unlike evaporation, composition of alloy in film is approximately the same as target.
Target NOT melted so no stoichimotery problem due to dif. In vapour pressure and dif. In deposition rate,
arrival time, slow diffusion (no material flow) mixing.
When target reaches steady state, surface composition balances sputter yield.

Sputter increases with ion mass.
Sputter yield is a maximum for ions with full valence shells: noble gasses such
as Ar, Kr, Xe have large yields.Dependence of sputter yield on ion mass
Sputter rate for Ag is higher than Cu, and Cu higher than Ta


DC Sputtering, RF Sputtering: Magnetron Sputtering
Ionization Eff: Low ; Ionization Eff: Medium ; Ionization Eff: High ;
Charge acc at cathode and anode; non ionized collision insulator
Eletrostatic plates control %e hitting and causing ionization, magnet control deposition as a result, trap e helical pattern
The ionization and sputtering efficiencies are increased significantly
Atom migration along surface also important
Atoms ejected from cathode escape with energies of 10 to 50 eV, which is 10-100 times the energy of evaporated atoms.
This additional energy (together with bombardment by other ions) provides sputtered
atoms with additional surface mobility for improved step coverage relative to evaporation.
(This additional energy also makes the deposited film denser - better film quality than evaporated film).
-Deposition Rate: Low; Medium: High
deposition rates increase by 10-100X, to 1 microm per minute.
electrons involved; neutral particle; trap e generated due to E and B
perpendicular to each other, their Orbital motion of electrons increases
probability that they will collide with neutral species and create ions.
Deposition parameters:
Process pressure: compromise between the number of Ar ions
and the scattering of Ar ions with neutral Ar atoms
Sputter voltage: maximum yield, typical -2 to -5 kV, for high deposition rate.
Substrate bias: control ion bombardment characteristics.
Substrate temperature: modify deposited film properties.
Always
RF: When frequencies less than about 50kHz, just like medium pressure in DC
electrons and ions in plasma are
mobile o DC sputtering of both surfaces When frequencies above about 50kHz,
just like high pressure in DC here in RF
ions (heavy) can no longer follow the switching o Electrons can neutralize positive
charge build up.
Operate at moderate Pressure(RF: Capable of running in lower pressure
(1-15 mTorr)
Higher chamber pressure:
Mean-free path of an atom =4.810 3/ P(t orr) (cm). E.g. 0.1cmfor P=50mTorr.
Therefore, as typically target-substrate separation is many cm, sputtered atoms have to
go through tens of collisions before reaching the substrate.
This reduces deposition rate considerable materials are deposited onto chamber
walls.
Too many collisions also prevent ionization (reduce ion density and deposition rate).
Lower chamber pressure:
(For same power) higher ion energy that increases sputter yield/deposition rate.
But fewer Ar ions to bombard the target for deposition, which reduces deposition rate.
Therefore, there exist an optimum pressure (provided that such a pressure can sustain
the plasma) for maximum deposition rate.
This optimum pressure depends on target-substrate configurations (their separation,
target/substrate size).
A lower Ar pressure (to 0.5mTorr, can still sustain plasma) can be utilized since
ionization efficiency is larger which can improve film quality as less argon will be
incorporated into the film.


Drawback
For conducting materials only. positive charge builds up on the
cathode (target) in DC sputtering so ionization is low (RF alternating V avoids charge buildup
and good for insulators as well but neutral particles combine; ionization is medium) trap e so Ionization is max
Unintentionall wafer heating happens; Unintentionall wafer heating happens;
Unintentional wafer heating is reduced since the dense plasma is confined near the
target and ion loss to the wafers is less.

Need Heating and Cooling Mechanism easy in DC;( RF: cooling of insulating targets is difficult in RF systems).
Dependence of deposition rate on chamber pressure

Arrival angle can be tailored to some degree
However, when the mean free path of the target atom is much shorter than target
substrate separation, many collisions will occur, which broaden the arrival angle
distribution (in contrary to evaporation).




How to get uniform conformal step coverage
Besides tilting and rotating substrate, step coverage can be further improved by:
Substrate heating: improve step coverage due to surface diffusion, but may produce
unacceptably large grains.
Apply bias to wafers: increase bombardment by energetic ions, but it will also sputter the
deposited material off the film and thus reduce deposition rate.
Atoms ejected from cathode escape with energies of 10 to 50 eV, which is 10-100 times the
energy of evaporated atoms.
This additional energy (together with bombardment by other ions) provides sputtered
atoms with additional surface mobility for improved step coverage relative to evaporation.
(This additional energy also makes the deposited film denser - better film quality than
evaporated film).
Atom migration along surface also important




Pulsed laser deposition (PLD)
Laser Beam
Target
Substrate
Plume
(Plasma)
Plume generated by laser ablation
with different tiny or micro-particles
PLD Characteristics:
Reproduce the composition of the target
Fabricate multi-component multilayer structures
Fast response and well controlled deposition rate
Environmentally benign technique
Pulse of fs to ns with peak power high
enough (hundreds of MW/cm2) to melt
boil vaporize ablate the target
surface material, to atoms, ions,
electrons, and clusters.
(a) (b) (c) (d)
Figure 5.1. Schematic laser-material interaction. (a)
Absorption and heating; (b) Melting and flowing; (c)
Vaporization; (d) Plasma formation in front of the
target. Under certain conditions the plasma can
detach from the target and propagate toward the
laser beam.
CVD film growth steps
Source production of appropriate gas
Transport of gas to surface
Form thin films on the surface of a substrate by thermal decomposition
and/or reaction of gaseous compounds
Usually performed at high temperature
Can be performed at various pressure and with assistance of plasma (PECVD)
Adsorption of gas on substrate
Reactions on substrate
Transport of by-products away from substrate
Types of CVD reactions Peculiarity of CVD
Thermal decomposition
AB(g) ---> A(s) + B(g)
ex: Si deposition from Silane at 650oC: SiH4(g) Si(s) + 2H2(g)
Reduction (using H2)
AX(g) + H2(g) <===> A(s) + HX(g)
W deposition at 300oC: WF6(g) + 3H2(g) <===> W(s) + 6HF(g)
Oxidation (using O2)
AX(g) + O2(g) ---> AO(s) + [O]X(g)
SiO2 deposition from silane and oxygen at 450oC (lower temp than thermal
oxidation): SiH4(g) + O2(g) ---> SiO2(s) + 2H2(g)
Compound formation (using NH3 or H2O)
AX(g) +NH3(g) --> AN(s)+HX(g) or AX(g)+H2O(g)-->AO(s)+HX(g)
Deposit wear resistant film (BN) at 1100oC: BF3(g) + NH3(g) ---> BN(s) + 3HF(g)













CVD process
Advantages:
High growth rates possible
Can deposit materials which are hard to evaporate
Good reproducibility
Can grow epitaxial films (in this case also termed as vapor phase
epitaxy (VPE). For instance, MOCVD is also called OMVPE.)
Generally better film quality than PVD films.
Disadvantages:
High process temperatures
Complex processes
Toxic and corrosive gasses
Film may not be pure (hydrogen incorporation).

Types of CVD
APCVD (Atmospheric Pressure CVD) (not very popular for nanofabrication), mass
transport limited growth rate, leading to non-uniform film thickness.
APCVD, wafers have to be laid
horizontally side by side.

LPCVD (Low Pressure CVD)
Low deposition rate limited by surface reaction, so uniform film thickness (many
wafers stacked vertically facing each other; in APCVD, wafers have to be laid
horizontally side by side.
Gas pressures around 1-1000mTorr (lower P => higher diffusivity of gas to substrate)
Better film uniformity & step coverage and fewer defects
Process temperature 500 C
Film Quality better than PECVD
Reaction at high temperature
Reaction rate (determined by
temperature) limited deposition rate.


PECVD (Plasma Enhanced CVD)
Plasma helps to break up gas molecules: high reactivity, able to process at lower temperature and lower pressure (good for electronics on plastics).
Reaction at low temperature, assisted by plasma
Pressure higher than in sputter deposition: more collision in gas phase, less ion bombardment on substrate
Can run in RF plasma mode: avoid charge buildup for insulators
Film quality is poorer than LPCVD.
Process temperature around 100 - 400C.
PECVD process parameterSubstrate temperature
Control by external heater, very little heating from PECVD process Gas flow
Higher flow rates can increase deposition rate and uniformity Pressure
Changes the energy of ions reaching electrodes
Can change deposition rate
Increases pressure may lead to chemical reactions in the gas
Effects also depend on gas concentration Power
Affects the number of electrons available for activation and the energy of those electrons
Increased power may lead to chemical reactions in gas
Increased power increases deposition rate Frequency (for PECVD)
Changes plasma characteristics
Changes ion bombardment characteristics

ALD (Atomic layer deposition)

MOCVD (Metal-organic CVD, also called OMVPE - organo metallic VPE), epitaxial growth
for many optoelectronic devices with III-V compounds for solar cells, lasers, LEDs,
photo-cathodes and quantum wells.

Silicon nitride deposition Application:
o Masks to prevent oxidation for LOCOS process
o Final passivation barrier for moisture and sodium contamination
o Etch stop for Cu damascene process
o Popular membrane material by Si backside through-wafer wet etch.
Atomic layer deposition (ALD, break CVD into two steps)
Similar in chemistry to chemical vapor deposition (CVD), except that the ALD reaction breaks the CVD reaction into two half-reactions, keeping the precursor materials separate
during the reaction. The precursor gas is introduced into the process chamber and produces a monolayer of gas on the wafer surface. A second precursor
of gas is then introduced into the chamber reacting with the first precursor to produce a monolayer of film on the wafer surface.
Film growth is self-limited (monolayer adsorption/reaction each half-cycle), hence atomic layer thickness control of film grown can be obtained.
That is, one layer per cycle; thus the resulting film thickness may be precisely controlled by the number of deposition cycles.
Two fundamental mechanisms: 1.o Chemi-sorption saturation process 2. Sequential surface chemical reaction process
Introduced in 1974 by Dr. Tuomo Suntola and co-workers in Finland to improve the quality of ZnS films used in electroluminescent displays.
Recently, it turned out that ALD also produces outstanding dielectric layers and attracts semiconductor industries for making High-K dielectric materials.
Advantages and disadvantages
Advantages Stoichiometric films with large area uniformity and 3D conformality. Precise thickness control. Low temperature deposition possible. Gentle deposition
process for sensitive substrates. Each layer formed each cycle, controlled thickness. ALD: slowest, best step coverage
Disadvantages Deposition rate slower than CVD. Number of different material that can be deposited is fair compared to MBE.
Epitaxy
Epitaxy refers to the method of depositing a
monocrystalline film on a monocrystalline substrate.
The word epitaxy comes from the Greek for above (epi)
and in an ordered manner (taxis): to arrange upon.
Autoepitaxy(or Homoepitaxy): extension of the substrate
lattice by the overgrowth of a layer of identical material
(e.g. Si on Si or GaAs on GaAs) with no problem of
compatibility or mismatch.
Heteroepitaxy: any two materials of different crystalline
structure and orientation (e.g. (001) GaAs on (001) Si or
(01) Si on Sapphire)

Heteroepitaxy conditions
Heteroepitaxy Conditions)(AlGaN && GaN) GaAs&Si
Substrate must be physically and chemically inert to the growth environment
and being prepared with a damage-free surface.
Chemical compatibility between the materials to avoid compound formation or massive
dissolution of one layer by the other.
Matched thermal expansion characteristics between the layer and substrate to avoid
excess stress upon cooling formaon of dislocaon at the interface, or even breaking
of the structure
Matched lace parameters between the layer and substrate not a serious
problem

MOVCVD MOCVD: metal-organic CVD = OMVPE: organo-metallic vapor phase epitaxy
Many materials that we wish to deposit have very low vapor pressures and thus are
difficult to transport via gases.
One solution is to chemically attach the metal (Ga, Al, Cu, etc) to an organic compound
that has a very high vapor pressure.
The organic-metal bond is very weak and can be broken via thermal means on wafer,
depositing the metal with the high vapor pressure organic being pumped away.
It is the main workhorse for III-V semiconductor industry (semiconductor laser, LED,
optoelectronics).
Some MOCVD precursor gases:
Tri-methyl-aluminum, liquid
Tri-methyl-gallium, liquid
Arsine AsH3, gas
Di-methyl selenide, liquid
Di-methyl zinc, liquid



The organometallic process
Advantages: Highly flexible we can deposit semiconductors, metals, dielectrics
Disadvantages: Highly toxic, very expensive source material, and environmental
disposal costs are high.
Material deposited:
III-V semiconductors AlGaAs, AlGaInP, AlGaN, AlGaP, GaAsP, GaAs, GaN, GaP, InAlAs, InAlP,
InSb , InGaN, GaInAlAs, GaInAlN, GaInAsN, GaInAsP, GaInAs, GaInP, InN, InP.
II-VI semiconductors - Zinc selenide (ZnSe), HgCdTe, ZnO, Zinc sulfide (ZnS)
IV semiconductors - Si, Ge, strained silicon












Molecular-beam epitaxy (MBE)
MBE is an epitaxial process involving the reaction of one or more thermal beams of atoms
or molecules with a crystalline surface under UHV conditions.
Precise control in both chemical composition and doping profiles.
It has a very low growth rate (e.g. for GaAs, a value of 1m/hr is typical.)
Single-crystal multilayer structures with dimensions on the order of atomic layers can be
made.

Liquid-phase epitaxy (LPE)
LPE involves the growth of epitaxial layers on crystalline substrate by direct precipitation from the liquid phase.
In LPE, the substrate is held in contact with the supersaturated solution (As saturated solution of Ga).
Cooling the arsenic saturated solution of gallium causes the arsenic to precipitate in the form of GaAs.
Typical deposition rates for monocrystalline films range from 0.1 to 1 m/min.
LPE in most cases is a very economic deposition techniques, especially when up-scaled to mass-production































































Three types of solids - amorphous, polycrystalline, mono-crystalline (single-crystal).
Semiconductor devices and VLSI (very large scale integrated) circuits require high-purity single-crystal semiconductors. Because:
o Better quality control
o Higher mobility


Amorphous silicon is used in photovoltaic cells, electronic displays (large-area).
Polycrystalline silicon is used as a gate contact in MOSFETs (VLSI circuits).
Dislocation
Stacking Fault
Precipitate
6Point defects
Point defects. a) Substitutional. b) Interstitial. c) Vacancy (Schottky defect). d) Frenkel-type defect (interstitial - vacancy pair).
Point defects dictate most dopant diffusion mechanisms, and thus determine the impurity profile.

You may want a dopant impurity to be on a substitutional site, but you may not want a heavy metal atom or other
unwanted impurity to be on a substitutional site (harder to remove).
Dopant atoms diffuse through the semiconductor faster as interstitials, but we
need to place them in substitutional sites to make use of them (i.e. they act as dopants only
when in substitutional sites).

Interstitials can be foreign unwanted impurities, intentionally introduced impurities, or
misplaced host atoms (an intrinsic defect, the self-interstitial).

Point defects: interstitial
Line Defect: Dislocation
Dislocation causes low yield strength of solids.
Dislocation sources: by stress due to temperature gradient, due to agglomeration.
Stacking : 2D defect
Precipitate: 3D defect









Electrical grade silicon (polycrystalline) EGS
Basically, the solid Si is first converted into a liquid form (SiHCl
3) for purification, then
converted back into solid Si.
Both reactions occur at high temperatures.

Metallurgical grade silicon is treated with hydrogen chloride to form trichlorosilane:
Si + 3HClSiHCl
3(g) + H2(g) (use catalyst)
SiHCl3 is liquid at room temperature, boiling point 32oC. Multiple distillation of the liquid
removes the unwanted impurities (99.9999% pure).
The purified SiHCl3 is then used in a hydrogen reduction reaction to prepare the
electronic grade Si (EGS):SiHCl
3(g) + H2(g) Si(s)+ 3HCl(g)
(this is the reverse reaction of the above reaction)
EGS is the raw material for Si single crystal production.

Oxygen and carbon in CZ silicon
The CZ growth process inherently introduces O (from
SiO2 crucible) and C (from graphite
susceptor/supporter).
Typically, CO 1018 cm-3 and CC 1016 cm-3.
The O in CZ silicon often forms small SiO2 precipitates
in the Si crystal under normal processing conditions.
Critical size is about 1nm: stable precipitates above
1nm, may shrink and disappear below 1nm.
O and these precipitates can actually be very useful:
provide mechanical strength, internal gettering.

Most k0 values are <1 which means the impurity prefers to stay in the liquid.
Thus as the crystal is pulled, dopant concentration will increase.
In other words, the distribution of dopant along the ingot will be graded.








LEC: high defect density ; HB: low defect density
CZ: Impurity by C and O allowed FZ: not allowed impurity
CZ: large dia of wafer FZ: small dia
CZ: uniform radial distribution of charge FZ: not unit
CZ: normal electronics; HB: optoelectronics FZ: power electronics

Float-zone crystal growth: overview

For CZ-grown Si, impurities (O and C) can be introduced from the melt contacting the SiO2 crucible and from
Graphite susceptor/supporter.
This limits the resistivity to 20cm, while intrinsic Si is 230kcm.
These float-zone grown crystals are more expensive and have very low oxygen and carbon.
Carrier concentrations down to 1011 atoms/cm3 have been achieved.
It is far less common, and is reserved for situations where oxygen and carbon impurities cannot be tolerated.
Float-zone does not allow as large Si wafers as CZ does and radial distribution of dopant in FZ wafer is not as uniform as in CZ wafer.
Mainly used in power electronics and THz applications.
Float-zone crystal growth process Polycrystalline silicon is converted into single-crystal by zone heating (zone melting).
The entire poly-Si rod from the EGS process is extracted as a whole. The rod is clamped at each end, with one end in contact with a single crystal seed.
An RF heating coil induces eddy currents (power I
2R) in the silicon, heating it beyond its melting point in the vicinity of the coil. The "floating" melt zone is about 2cm wide/high.
The seed crystal touches the melt zone and is pulled away, along with a solidifying Si boule
following the seed. The crystalline direction follows that of the seed single crystal.
Limited to about a 4" wafer, as the melt zone will collapse - it is only held together by
surface tension (and RF field levitation).
Poly-Si
c-Si
Melt is not held in a
container, it is
float, thus the
name float zone.
Float-zone: zone refining
Dopants/impurities prefer to stay in the liquid than in the solid. Thus, the impurities generally stay in the melt zone,
and don't solidify in the boule. That is, segregation (and evaporation) of impurities
in the melt zone help purify the Si further. One can "purify" FZ wafers further by successively passing the coil along the boule. The impurities then
segregate towards the end of the boule. Of course, if neglecting impurity evaporation, the total amount of impurity is the same. Yet the
impurity at the lower part is much lower than, and at the upper part approaches to, the original impurity concentration.
Thermal instability in the melt zone can cause micro-variations in composition and doping. Difficult in making a uniform dopant concentration.
Doping in FZ growthGas doping:Dopants are introduced in gaseous form during FZ growth.n-doping: PH3 (Phosphine), AsCl3p-doping: B2H6 (Diborane), BCl3
Good uniformity along the length of the boule.
Pill doping:
Drill a small hole in the top of the EGS rod, and insert the dopant.If the dopant has a small segregation coefficient, most of it will be carried with the
melt as it passes the length of the boule.Resulting in only a small non-uniformity.Ga and In doping work well this way.
Zone refiningZone length is L. The rod has initial uniform impurity concentration of C0.
If the molten zone moves upwards by dx, the number of impurities in the liquid (=I) will change
since some will be dissolved into the melting liquid at the top (=C0dx) and
some will be lost to the freezing solid on the bottom (=CSdx=k0CLdx).
Thus: (assume cross-sectional area =1)














(actually Si cleaves naturally along {111}
wafer usually breaks along {110} plane
at 100 it gves best mobility and least orientation

Silicon-on-insulator (SOI)
Why do we want SOI wafer?
Lower parasitic capacitance: faster transistor
Better isolations between devices: prevent latch-up