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=
(1)
where G
TAG
is the antenna gain of the tag, and
0
is the wave-
length.
However, the signal power received by the reader from the
tag has to be higher than the reader sensitivity (S
R
). Therefore,
taking into account this limit, the maximum distance between
the reader and the tag can be estimated by using the following
formula:
0
4
max 2
4
R TAG
R
EIRP G G
r
S
=
(2)
Obviously the operating range is the smaller between r
max1
and r
max2
. Now, by considering a plausible value of the tag an-
tenna gain G
TAG
of at least 0 dBi (see results in Section III),
the minimum tag power consumption of about 5 W as in [6],
and the efficiency of the rectifier at 60 GHz close to 5% as in
[7], then the P
TAG
has to be at least 100 W, and then
r
max1
= 12.6 cm. Moreover, S
R
depends on the bit error rate
(BER) of the system and the noise figure of the reader. A feas-
ible value of S
R
for 60 GHz designs can be close to -60 dBm
with a BER of 10
-6
[8] and then r
max2
= 70.76 cm. Therefore
the operating range for 60-GHz RFID tags is due to r
max1
.
The RFID tag architecture in Fig. 2 is similar to other state-
of-art designs apart the on-chip antenna, the new key element
of this design described in details in Section III. In order to
build the 60-GHz fully-integrated tag proposed in this paper,
an accurate design of the on-chip antenna is required for
transmission and reception. It is worth nothing that the inte-
gration of antennas on silicon substrates is a critical require-
Fig. 2. Block diagram of the fully integrated 60-GHz passive RFID tag.
Fig. 3. Worldwide frequency allocation around 60 GHz.
TABLE I - EIRP LIMITS FOR THE READER (WCAI)
Reader
Antenna Gain
EIRP limit Transmitter Power
30 dBi 40 dBm (10 W) 10 dBm
40 dBi 60 dBm (1 KW) 20 dBm
50 dBi 80 dBm (100 KW) 27 dBm
458
ment enabling the entire system to be realized as a monolithic
unit that does not require any external transmission line con-
nections or sophisticated packaging. As shown in the next sec-
tion the 65-nm SOI CMOS process is a good candidate to effi-
ciently implement integrated antennas in the 60 GHz band.
B. SOI CMOS: Technology description
The SOI CMOS technology shows very attractive perfor-
mance for the millimeter-wave system-on-chip design, since
the high active performance of MOS transistors, such those
available in standard CMOS technology used in digital de-
signs [16-24], are combined with the high-resistivity (HR) of
the SOI substrate. Indeed, the feature that the circuit elements
are isolated dielectrically allows the SOI technology to signif-
icantly reduce junction capacitances and allows the circuits to
operate at high speed or substantially with lower power at the
same speed. Moreover, the device structure also eliminates the
latch-up in bulk CMOS and improves the short channel effect
immunity. A comparison between SOI and bulk CMOS tech-
nologies is shown in Fig. 4, in which the buried oxide (BOX)
layer (
r
= 4) and the high resistive (HR) substrate (
r
= 11.7,
Si
= 0.0001 S/m, and h
Si
= 355 m) can be noted in the SOI
process. Finally, the performance of the antennas designed in
SOI CMOS process are better than those designed on standard
CMOS process, as demonstrated in [9-13]. This improvement
is due to a reduced amount of energy stored in the supporting
substrate.
III. 60-GHZ ANTENNAS DESIGN
In this section the designs and the simulation results of two
different antennas, integrated in 65-nm SOI CMOS technolo-
gy, will be described.
A. Cross-section of the SOI CMOS process
The cross-section of a standard industrial SOI CMOS back-
end is shown in Fig. 5a. In this technology the back-end con-
sists of a very complex multi-layer in which the dielectric
multi-layer is composed by an alternation of SiO
2
and Si
2
N
4
.
For computing time reasons, since the 3D-EM simulator used
is a volume field solver (i.e. Ansoft HFSS), the multi-layer
back-end has been simplified to an equivalent back-end with a
reduced number of equivalent ticker layers that results in a
more efficient solution. In detail, the parameters took into ac-
count in order to build the simplified cross-section of the SOI
CMOS process are the metallization thickness made of 6 thick
copper staked layers (M
1
-M
6Z
), the aluminum capping layer
(AP) and the multi-layer dielectrics. The simplified cross-
section for the 3D-EM simulations are reported in Fig. 5b
where the multi-layer stack has been significantly compressed
without compromising the accuracy. For that purpose, a
weighted average of the dielectric material properties and
thickness calculated by means of the formula described in [14]
has been applied. The relative permittivity of each equivalent
layer (
r,eq
) is calculated by:
( )
2
1
, 1
1
n
e eq n n n
n n
h
h h
= +
+
(3)
where n is the layer index,
n
and h
n
are the relative permittivi-
ty and the thickness of the n
th
layer, respectively.
B. Antennas design
According to the above analysis, the CPW (Coplanar wave-
guide) topology is a good candidate to design the antenna for
the 60-GHz RFID tag. The work in [15] has also demonstrat-
ed that in HR SOI substrates the losses are drastically reduced
if compared with the bulk silicon technology, in which the
CPW transmission lines are made only on top metal layer in
order to reduce substrate losses. The design presented herein
makes use of staked structure (M
1
-AP) for the ground paths
and AP and M
6Z
metal layers for the signal paths. It is worth
noting that the ground planes have to be large enough to intro-
duce negligible effects on the antenna property, and then a
compromise has been reached between infinite ground planes
and suitable dimensions for silicon applications. Fig. 6 shows
the simplified CPW architecture dedicated to SOI CMOS
process; in Fig 6 W is the width of the signal line and G is the
gap between the signal line and the ground plane.
To realize a balanced and simpler feeding line for the radia-
Fig. 4. a) Simplified cross section of SOI CMOS process and b) Simplified
cross-section of bulk CMOS process.
Fig. 5. a) Cross section of SOI CMOS back-end and b) Simplified cross-
section of SOI CMOS back-end for 3D-EM simulations.
Fig. 6. Simplified CPW architecture implemented for the SOI CMOS tech-
nology.
Fig. 5. a) Cross section of SOI CMOS back-end and b) Simplified cross-
section of SOI CMOS back-end for 3D-EM simulations.
459
tion structure, also the CPS (Coplanar strip) topology has been
looked at. In Fig 7, a CPS with a finite dielectric thickness
configuration is depicted, where S, W, H, and
r
represent the
slot width, strip width, substrate thickness, and relative dielec-
tric constant of the substrate material, respectively. The design
presented herein makes use of M
6Z
metal layers for the signal
paths.
The integrated antennas proposed hereafter in Sections III.C
and III.D are designed taking into account the following
guidelines: i) the 65-nm SOI CMOS process by ST-
Microelectronics has been used, ii) the 3D-EM designs did not
consider the pad effects since these parasitic effects will be
removed by de-embedding during the measurements, iii) the
knowledge of the effective dielectric constants are necessary
to determine the resonant frequency.
At the operating frequency the antenna reactance (Im{Z
IN
})
must be null and the real part of intrinsic antenna impedance
(Re{Z
IN
}) must be matched to the communication circuit out-
put impedance. In the considered case of an on-chip integrated
antenna the impedance value can be taken as a parameter of
the design.
C. CPW Double slot antenna
The first proposed antenna is a CPW double slot (see geo-
metrical parameters and layout in Fig. 8). There are many
coupling matching networks that can be used to connect the
transmission line to the antenna element such as quarter-
wavelength transformer, stub, T-match and others. For exam-
ple, a /4 transformer can be used to match CPW double slot
antenna to the canonical 50 impedance. In order to provide
the matching, the /4 transformer characteristic impedance Z
/4
has been set equal to:
/ 4 0 IN
Z R Z
=
where Z
0
= 50 represents the characteristic impedance of
the CPW transmission line and R
IN
= Re{Z
IN
} is the input im-
pedance of the antenna.
In this design, the gap between ground plane and antenna
(G
S1
and G
S2
in Fig. 8) is carefully selected to obtain a good
radiation pattern and resonant behavioral at the operating fre-
quency. An unbalanced CPW feed line is choice as input of
the antenna.
The final 60 GHz fully integrated double-slot antenna is
realized with the following parameters: slots length = 910.22
m (L
S
), width = 22.76 m (W
S
) and 40 m gap between
ground plane and antennas arm. The CPW parameters are W
= 12 m and G = 12.2 m. The feeding lines length is of 560
m (L
CPW
). Output impedance is about 14.3 at work fre-
quency. The simulated radiation pattern of this antenna is
mainly directed toward the SOI substrate, therefore, with a
backside metallization the radiation pattern is directed outward
the substrate. The distance between radiating arms and the ref-
lector (355 m ~
g
/4) is close to the optimal distance to pre-
vent TM mode which reduces radiation efficiency.
The area needed for the antenna design is roughly 1 mm
2
,
compliant with on-chip realization. The 3D polar plot of the
antenna gain and the radiation pattern obtained by means of
3D-EM simulations are shown in Fig. 9. In detail, a maximum
Fig. 8. 60-GHz SOI CMOS CPW double slot antenna a) geometrical para-
meters and b) design on the 3D-EM simulator.
Fig. 9. 60-GHz SOI CMOS CPW double slot antenna. 3D polar plot of the
antenna gain and radiation pattern.
Fig. 7. Simplified CPS architecture implementation.
460
gain of 4.44 dBi, a return loss (S11) equal to - 21.82 dB and an
efficiency of 67% at 59.4 GHz have been obtained. Finally, a
directivity peak of about 4.15 is obtained. With a tag antenna
gain (G
TAG
) of 4.44 dBi the value of r
max1
in equation (1),
which determines the operating range, is about 21 cm.
D. CPS dipole antenna
As alternative to the antenna in Section III.C we also de-
signed and characterized by 3D-EM simulations a CPS dipole
antenna. The antenna we designed (see Fig. 10) is directly fed
by a coplanar strip (CPS) input matching network. The area
occupied by the antenna is 0.244 mm
2
, which is suited for on
chip integration. The radiation pattern of the CPS dipole an-
tenna obtained by means of 3D-EM simulations is shown in
Fig. 11. In detail, a maximum gain of 3.23 dBi and a return
loss (S11) equal to -23.7 dB at 60 GHz, respectively, have
been obtained. With a tag antenna gain (G
TAG
) of 3.23 dBi the
value of r
max1
in equation (1), which determines the operating
range, amounts to 18.25 cm.
In this design, the arm width is carefully selected to reduce
the quality factor of resonance and obtain a wider operating
bandwidth. A balanced CPS feed line is choice as input of the
dipole antenna, and its length is tuned in order to obtained the
wished input impedance ( 20 at work frequency). The final
60 GHz fully integrated dipole antenna is realized with the fol-
lowing parameters: dipole's length = 760 m (L
D
), width =
22.76 m (W
D
) and 1.1 m gap between the two dipoles
arms. The feeding lines length is of 300 m (L
CPS
).
The radiation pattern of the integrated dipole shows that the
radiation is mainly directed toward the SOI substrate, where
losses occur. The backside metallization under the wafer can
be advantageously used to act as a reflector. The radiation pat-
tern is directed outward of the substrate when backside metal-
lization is added. The distance between radiating arms and the
reflector (355 m ~
g
/4) is close to the optimal distance. Fi-
nally, the dipole antenna has 68.8% of radiation efficiency,
with peak directivity of about 3.
Both designed antennas are suitable for on chip integration.
The first type of antenna is the most conventional, and takes
larger chip area, but it presents a higher gain and a particular
behavioral of imaginary part of impedance. As we can see in
Fig. 12, there are many resonant points, so the antenna can be
useful in different frequency ranges. The bandwidth of the
double-slot antenna is thin, only 900 MHz, however, its
enough for the RFID applications. The dipole antenna, instead,
presents a balanced feed line, useful in differential elaboration
of signals, and a very small chip area.
IV. CONCLUSION
A fully integrated passive RFID tag for applications in the
60-GHz license-free band has been presented and the advan-
tages of a fully integration have been described. The 60-GHz
tag does not require pads, bonding or package and does not
needs battery, therefore it represents an important innovation
to further extend the applications of RFIDs. The 65-nm SOI
CMOS process by ST-Microelectronics used in the design,
allowed us, to design a more efficient antenna thanks to its
higher isolation between the substrate and active region, if
compared with a traditional CMOS bulk process. Two inte-
grated 60-GHz antennas have been designed and simulated by
means of the 3D-EM simulator HFSS. The results have shown
a gain of 4.44 dBi and 3.23 dBi, respectively, for the double-
slot and dipole antennas.
Finally, the low-cost, the very low-weight, and the low-area
occupation due to the fact that there are no external elements,
makes the proposed RFID tag very attractive for the mass-
market, especially in those sectors where traditional tags can-
not be used.
Fig. 10. 60-GHz SOI CMOS Dipole antenna: a) geometrical parameters
and b) design on the 3D-EM simulator.
Fig. 11. 60-GHz SOI CMOS CPS dipole antenna: radiation pattern.
461
REFERENCES
[1] K. Takaragi, M. Usami, R. Imura, R. Itsuki, T. Satoh, An ultra small
individual recognition security chip, IEEE Micro, Vol. 21, Issue 6,
Nov.-Dec. 2001, pp. 43 49
[2] M. Usami, A. Sato, K. Sameshima, K. Watanabe, H. Yoshigi, R. Imura,
Powder LSI: an ultra small RF identification chip for individual
recognition applications, IEEE International Solid-State Circuits
Conference, Digest of Technical Papers, Vol. 1, 2003 pp. 398 501
[3] S. Genovesi et al., Double loop antenna for wireless tyre pressure
monitoring, Electronics Letters, vol. 44, n.25, pp.1385-1387, 2008
[4] ETSI "EN 302 217-3", Fixed Radio Systems and Characteristics and
requirements for point-to-point equipment and antennas
[5] Federal Communications Commission (FCC), 18-07-0082-01-0000d1,
Amendment of Part 15 Rules for License-Exempt 57-64 GHz Band
[6] G. De Vita et al., Design criteria for the RF section of UHF and
microwave passive RFID transponders, IEEE Tran. on Microwave
Theory and Techniques, vol. 53, n.9, 2005, pp.2978-2990
[7] M. Pinuela et al., Analysis of Scalable Rectenna Configurations for
Harvesting High Frequency Electromagnetic Ambient Radiation, Po-
werMEMs 2010, pp.41-44
[8] Sien Wu et al., 60 GHz Wireless Link Using Frequency Division Dup-
lex QPSK Architecture, University of Florida, project6374
[9] R. Pilard, S. Montusclat, D. Gloria, F. Le Pennec, C. Person, "Folded-
Slot Integrated Antenna Array for Millimeter-Wave CMOS Applications
on Standard HR SOI Substrate", IEEE Topical Meeting on Silicon
Monolithic Integrated Circuits in RF Systems, 19-21 Jan. 2009, pp. 1 4
[10] S. Montusclat, F. Gianesello, D. Gloria, "Silicon full integrated LNA,
filter and antenna system beyond 40 GHz for MMW wireless
communication links in advanced CMOS technologies", IEEE Radio
Frequency Integrated Circuits (RFIC) Symposium, 2006
[11] S. Montusclat, F. Gianesello, D. Gloria, S. Tedjini, "Silicon integrated
antenna developments up to 80 GHz for millimeter wave wireless links",
IEEE Microwave Conference, European, Vol. 3, 2005
[12] S. Montusclat, F. Gianesello, D. Gloria, S.; Tedjini, "Silicon integrated
antenna developments up to 80 GHz for millimeter wave wireless links",
The European Conference on Wireless Technology, 3-4 Oct. 2005, pp.
237 240;
[13] S. Montusclat, F. Gianesello, D. Gloria, Silicon integrated antenna
substrate benchmarking for MMW wireless applications in advanced
CMOS technologies, EuCAP, 2006, p.680
[14] Kraszewski, Prediction of dielectric properties of two phases mixtures,
Journal of Microwave Power, Vol. 12, 1977.
[15] F. Gianesello, D. Gloria, S. Montusclat, C. Raynaud, S. Boret, C.
Clement, G. Dambrine, S. Lepilliet, F. Saguin, P. Scheer, P. Benech,
J.M. Fournier, "65 nm RFCMOS technologies with bulk and HR SOI
substrate for millimeter wave passives and circuits characterized up to
220 GHz", IEEE MTT-S International Microwave Symposium Digest,
11-16 June 2006, pp. 1927 1930.
[16] N. LInsalata et al., Automatic synthesis of cost effective FFT/IFFT
cores for VLSI OFDM systems, IEICE Transactions on Electronics,
vol. E91C, n.4, pp.487-496, 2008
[17] F. Vitullo et al., Low-complexity link micro-architecture for
mesochronous communication in networks-on-chip, IEEE Transactions
on Computers, vol.57, n.9, pp. 1196-1201, 2008
[18] S. Saponara et al., Architectural exploration and design of Time-
interleaved SAR arrays for low-power and high speed A/D converters,
IEICE Transactions on Electronics, vol. E92-C, n.6, pp. 843-851, 2009
[19] S. Saponara et al., Performance and complexity co-evaluation of the
advanced video coding standard for cost-effective multimedia
communications, EURASIP JOURNAL ON APPLIED SIGNAL
PROCESSING , Vol. 2004, n. 2, pp. 220-235, 2004
[20] S. Saponara, L. Fanucci, VLSI design investigation for low-cost, low-
power FFT/IFFT processing in advanced VDSL transceivers,
Microelectronics Journal, vol. 34, n. 2, pp. 133-148, 2003
[21] F. Baronti et al., Design and verification of hardware building blocks
for high-speed and fault-tolerant in-vehicle networks, IEEE Trans.
Industrial Electronics, vol. 58, n. 3, pp. 792-801, 2011
[22] L. Fanucci et al., A parametric VLSI architecture for video motion
estimation, Integration-The VLSI Journal, vol.31, n.1, pp. 79-100, 2001
[23] S. Saponara et al., Algorithmic and architectural design for real-time
and power-efficient Retinex image/video processing, Journal of Real-
time Image Processing, vol. 1, n. 4, pp. 267-283
[24] S. Saponara et al., Dynamic control of motion estimation search
parameters for low complex H.264 video coding, IEEE Tran. on
Consumer Electronics, vol. 52, n.1, pp. 232-239, 2006
-300
-200
-100
0
100
200
300
400
500
600
700
30 35 40 45 50 55 60 65 70 75 80 85 90
Freq [GHz]
Imag(Zin),Re(Zin)
im_Zin
re_Zin
Fig. 12. 60-GHz SOI CMOS CPW double slot antenna a) input resistance and b) input reactance.
462