IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO.

3, MARCH 2012 1579

Single-Stage, Universal-Input AC/DC LED Driver
With Current-Controlled Variable PFC
Boost Inductor
Yuequan Hu, Laszlo Huber, Member, IEEE, and Milan M. Jovanovi c, Fellow, IEEE
AbstractThis paper presents a single-stage yback power-
factor-correction (PFC) circuit with a variable boost inductance
for high-brightness LED applications for the universal input volt-
age (90270 V
rms
). The proposed circuit overcomes the limitations
of the conventional single-stage PFC yback with a constant boost
inductance that cannot be designed to achieve a practical max-
imum bulk-capacitor voltage level (i.e., less than 450 V) at high
line while meeting required line-current harmonic specications
at low line. According to the proposed method for achieving vari-
able boost inductance, the boost inductance has a constant high
value at high line, while at low line it is reduced proportionally
to the load current, so that the IEC 61000-3-2 class C and corre-
sponding Japanese JIS C 61000-3-2 class C line-current harmonic
limits are satised. The proposed single-stage PFC yback LED
driver with the variable boost inductor is experimentally veried
on a 24-V/91-W prototype circuit.
Index TermsLEDdriver, power factor correction(PFC), single
stage, variable boost inductance.
I. INTRODUCTION
T
HE technology and performance of high-brightness LEDs
(HB LEDs) has undergone signicant improvements
driven by new applications in liquid-crystal-display (LCD)
backlighting, automobiles, trafc lights, and general-purpose
lighting [1][3]. As a solid-state light source that does not con-
tain mercury, HB LEDs have been widely accepted because
of their superior longevity, low-maintenance requirements, and
continuously improving luminance with a great potential to re-
place existing lighting sources such as incandescent and uo-
rescent lamps in the future.
For input-power levels above 25 W, ac/dc LED drivers must
comply with the line-current harmonic limits set by the IEC
61000-3-2 class C [4] and the corresponding Japanese JIS C
61000-3-2 class C [5] regulations. Generally, it is difcult to
meet these requirements by employing passive power-factor-
correction (PFC) techniques, especially for the universal input-
Manuscript received March 8, 2010; revised August 28, 2010; accepted
September 20, 2010. Date of current version February 7, 2012. This paper
was presented at the 25th Annual IEEE Applied Power Electronics Conference
(APEC), Palm Springs, CA, Feb. 2125, 2010. Recommended for publication
by Associate Editor M. Alonso.
Y. Hu is with Cree Inc., Morrisville, NC 27560, USA (e-mail:
yuequan_hu@cree.com).
L. Huber and M. M. Jovanovi c are with Power Electronics Laboratory,
Delta Products Corporation, Research Triangle Park, NC 27709 USA (e-mail:
lhuber@detlartp.com, milan@deltartp.com).
Color versions of one or more of the gures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identier 10.1109/TPEL.2010.2082564
Fig. 1. Conventional two-stage LED driver.
Fig. 2. Single-stage yback LED driver without energy-storage capacitor at
primary side [8].
voltage-range (90270 V
rms
) applications. As a result, the
majority of todays universal-input-voltage-range ac/dc LED
drivers are implemented with active PFC.
A conventional two-stage LED driver with active PFC is
shown in Fig. 1. The rst stage provides a near unity power
factor and a low total harmonic distortion (THD) in the entire
universal input-voltage range (90270 V
rms
), while the second
dc/dc stage is used to provide a tight regulation of the output.
Since the circuit in Fig. 1 requires two independently controlled
power switches and two control circuits, it suffers from an in-
creased component count and cost. In low-power lighting ap-
plications, where the cost is the dominant consideration, the
two-stage approach is less competitive than single-stage active
PFCimplementations [6], [7], where the PFCstage is integrated
with the dc/dc stage. Moreover, due to its minimal component
count and low cost, the single-stage, single-switch, PFC y-
back converter [8], [9] has emerged as the most widely used
single-stage topology.
Generally, a single-stage PFC ac/dc converter can be imple-
mented without or with a bulk capacitor at the primary side, as il-
lustrated in Figs. 2 and 3, respectively. Although the single-stage
0885-8993/$26.00 2010 IEEE
1580 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 3, MARCH 2012
Fig. 3. Single-stage yback LED driver with energy-storage capacitor at pri-
mary side [9].
PFCcircuit in Fig. 2 [8] has the advantage of a lower component
count, its output voltage has a high ripple at twice the line fre-
quency unless very large output capacitors are used. Since for
an LED load, a small variation in the driving voltage can lead to
a large variation in the LED current, a large ripple of the LED
current would seriously affect the reliability and longevity [10],
as well as the luminous efcacy [11] of the LEDs. Therefore,
the approach in Fig. 2 often requires a postregulator, which adds
cost and lowers the efciency.
The single-stage PFC yback topology shown in Fig. 3 [9]
presents one of the most cost-effective single-stage solutions.
In this converter, a PFC boost stage is integrated with the dc/dc
yback stage. The PFC boost stage operates in discontinuous
conduction mode (DCM), while the dc/dc yback stage operates
at the DCM/continuous-conduction-mode (CCM) boundary. A
low input-current harmonic distortion can be achieved due to
the inherent property of the DCM PFC boost converter to draw
a near sinusoidal current if its duty cycle is held relatively con-
stant during a half line cycle. However, voltage V
B
across bulk
capacitor C
B
is not regulated, and at high line, it can increase
to impractical levels. To reduce the bulk-capacitor voltage, one
terminal of the boost-inductor winding is connected to a tap-
ping point of the primary winding of the yback transformer,
which provides a negative magnetic feedback [12]. However,
the tapping of the yback primary winding also results in a
zero-crossing distortion of the line current. In fact, as long as
the instantaneous line voltage is lower than the voltage at the
tapping point, no current is drawn from the input, which re-
duces the power factor and increases the line-current harmonics.
Therefore, the selection of the tapping point is determined by
the tradeoff between the reduction of the bulk-capacitor voltage
and the quality of the line current.
The single-stage PFC yback in Fig. 3 has been successfully
applied in adapter/charger applications for the universal line
voltage, where the line-current harmonics need to meet the IEC
61000-3-2 and JIS C 61000-3-2 class D limits, which are less
stringent than the corresponding class C limits.
It was shown in [13] that the single-stage PFC yback in
Fig. 3 with a constant boost inductance cannot be designed to
achieve a practical maximum bulk-capacitor voltage level (i.e.,
less than 450 V) at high line while meeting the JIS C 61000-3-2
class C line-current harmonic limits at low line. To overcome
these limitations, a variable boost inductance is required, i.e.,
a high boost inductance at high line to limit the bulk-capacitor
Fig. 4. Basic variable inductor by adding a dc-bias ux to main magnetic ux:
(a) structure; (b) principle of operation [14].
voltage and a lower boost inductance at low line to ensure DCM
operation and, consequently, a low THD. In fact, at low line,
when a constant boost inductance is used, the inductor will
enter CCM operation around the peak of the line-voltage, and
the line-current waveform will have a surge around its peak
value [13], resulting in an increased THD. Furthermore, if the
bulk-capacitor voltage is slightly lower than the peak value of
the rectied line voltage, the peak charging of the bulk capacitor
through the bridge rectier will also result in a surge in the line-
current waveform [12] with an increased THD.
In this paper, it is shown that by optimizing the tapping point
of the primary winding of the yback transformer in Fig. 3, and
by employing a novel technique to reduce the boost inductance at
lowline, a high power factor and a lowTHDwith relatively high
efciency can be achieved such that the line-current harmonics
satisfy the IEC 61000-3-2 and corresponding Japanese JIS C
61000-3-2 class C limits, while the bulk-capacitor voltage is
limited below 400 V.
II. VARIABLE INDUCTOR FOR LED APPLICATIONS
A variable inductor for LED applications can be achieved
by controlling the inductance with a dc-bias current, i.e., by
adding a dc-bias ux to the main magnetic ux [14][20]. The
basic concept is shown in Fig. 4, where a control winding N
C
is added to the inductor winding N
L
on the same magnetic
core [14]. A dc-bias current I
C
owing through the control
winding produces a bias magnetic ux
C
. The main magnetic
ux
L
produced by the inductor current is superimposed on
HU et al.: SINGLE-STAGE, UNIVERSAL-INPUT AC/DC LED DRIVER WITH CURRENT-CONTROLLED VARIABLE PFC BOOST INDUCTOR 1581
Fig. 5. Improved variable inductor: (a) structure; principle of operation (b)
without and (c) with bias current [15], [16].
the bias magnetic ux
C
. As the dc-bias magnetizing force
increases, the permeability of the core material, i.e., the slope
of the BH curve (=lim
H0
B/H) decreases, as shown
in Fig. 4(b), leading to a decreased inductance.
To reduce the circuit complexity and maximize efciency, in
the LEDdriver described in this paper, the load current is used as
the dc-bias current by connecting the control winding in series
with the LED load. Because in this implementation the ripple
voltage induced in the control winding affects the LED current,
it is of the utmost importance to minimize this voltage ripple so
that the LED ripple current is minimized to the point that it does
not affect the light quality. Since the induced voltage across the
control winding depends on the coupling between the control
and inductor windings, the coupling plays a major role in the
design of a variable inductor for this LED driver application.
The basic structure of the current-controlled variable inductor
shown in Fig. 4(a) is not suitable for LED applications because
the control winding is strongly coupled to the inductor winding,
resulting in a large induced ac voltage in the control winding.
An improved variable inductor is proposed in [15] and [16],
where the inductor winding is divided into two identical por-
tions, which are wound on two identical toroidal cores and
connected in series so as to produce opposing uxes through
the control winding, which is wound over both cores, as shown
in Fig. 5(a). Ideally, due to the opposing uxes, there is no
coupling between the inductor and control windings. Without a
bias current in the control winding, both cores exhibit the same
ux-density variation, i.e., B
1
= B
2
, as shown in Fig. 5(b).
Fig. 6. Variable inductor using EEcores with control winding wound on center
leg [17].
Therefore, the total inductance is twice the inductance of the in-
dividual inductor windings. Due to the equal but opposing mag-
netic uxes through the control winding, the induced voltage in
the control winding is zero. However, with a bias current in the
control winding, a biasing eld H
0
is produced that displaces
the operating point of the cores along their BH curves, as
shown in Fig. 5(c). One core (core 1) operates in the nonlinear
to saturation region, whereas the other core (core 2) operates
in the nonlinear to linear region along their respective BH
curves. As a result, the ux-density variation and, consequently,
the permeability in both cores are reduced compared to the case
without a dc bias. Therefore, the total inductance is reduced. In
addition, the ux-density variation in core 1 is smaller than that
in core 2, i.e., B
1
< B
2
. Consequently, the total ux-density
variation through the control winding is not zero, resulting in an
induced ac voltage in the control winding. It should be noted that
with an increased eld H in Fig. 5(c), i.e., at large signals, the
difference between the two opposing uxes increases, resulting
in an increased ac voltage in the control winding.
Another implementation of the variable inductor in Fig. 5 is
presented in [17], where instead of two toroidal cores a pair of E
cores are used, as shown in Fig. 6. A variable inductor, similar
to that in Fig. 6, with the difference that the positions of the
inductor winding and control winding are interchanged, i.e., the
control winding is divided into two identical portions, which
are wound on the outer legs of the EE core and connected in
series, while the inductor winding is wound on the center leg
of the EE core, is shown in Fig. 7 [18][20]. It should be noted
in Fig. 7 that the air gaps from the outer legs of the EE core in
Fig. 6 are moved to the central leg. The basic operation of the
variable inductor in Fig. 7 is the same as that of the variable
inductor in Fig. 6. However, the variable inductor in Fig. 7 has
a signicant advantage compared to the variable inductor in
Fig. 6. As can be seen in Fig. 7, the path of the bias magnetic
ux
C
does not include an air gap and, consequently, a lower
bias magnetomotive force is required to achieve the desired
inductance value.
In this paper, a new structure of the current-controlled vari-
able inductor is proposed as shown in Fig. 8. The inductor is
1582 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 3, MARCH 2012
Fig. 7. Variable inductor using EE cores with control winding wound on outer
legs [18][20].
Fig. 8. Proposed current-controlled variable inductor.
implemented with an EE core and winding N
L
, whereas control
winding N
C
is placed on a half core (E) that is closely attached
to the bottom part of the EE core. It should be noted that in this
structure there is practically no air gap at the interface between
the two cores, except for a very small gap due to the roughness
of the contact surfaces. Other types of cores such as EI and U
cores can be also used. When dc-bias current I
C
ows in control
winding N
C
, a magnetic ux
C
is induced, that is added to the
main magnetic ux
L
at the bottom part of the boost-inductor
EE core. As a result, at the bottom part of the EE core, the effec-
tive permeability is reduced, and consequently, the inductance
is decreased.
III. SINGLE-STAGE PFC FLYBACK LED DRIVER WITH
VARIABLE BOOST INDUCTOR
A. Variable Boost Inductor
The block diagram of the proposed single-stage PFC yback
LED driver with variable boost inductor is shown in Fig. 9.
The boost inductance L
B
is controlled by the load current, i.e.,
I
C
= I
LOAD
. The control circuit includes switch Q
C
, a dc-bias
Fig. 9. Block diagram of proposed single-stage PFC yback with variable
boost inductance for HB LED applications.
control circuit, an input voltage sensing circuit, and a low-pass
LC lter. At high line, switch Q
C
is closed, shorting bias wind-
ing N
C
. As a result, there is no bias current through winding N
C
,
and the boost inductance does not change. At low line, switch
Q
C
is open and the bias current ows through bias winding N
C
,
inducing a magnetic ux
C
that is added to the main mag-
netic ux
L
B
at the bottom part of the boost-inductor EE core.
Consequently, the boost inductance is decreased. The reduction
of the boost inductance is proportional to the applied bias cur-
rent. The low-pass LC lter in parallel with control winding
N
C
essentially prevents the ac ripple component of the control-
winding current from owing through the LED load, namely,
the control-winding current, in addition to the dc component,
has a relatively large ac component, which is due to the induced
ac voltage in the control winding. Without lter inductance L
C
,
the amplitude of the ac ripple current of the control winding will
be very large if the leakage inductance of the control winding
under the dc-bias current is small. The value of inductance L
C
and capacitance C
C
should be large enough so that the ac ripple
current through the LED load is smaller than a specied per-
centage (5% in the most stringent case) of the dc load current.
B. Control Circuit
Fig. 10 shows the detailed schematic of the proposed single-
stage PFC yback HB LED driver. The input voltage is sensed
by a circuit comprising winding N
3
wound on the boost-inductor
EE core, diode D
8
, and capacitor C
1
. MOSFET Q
2
connected
HU et al.: SINGLE-STAGE, UNIVERSAL-INPUT AC/DC LED DRIVER WITH CURRENT-CONTROLLED VARIABLE PFC BOOST INDUCTOR 1583
Fig. 10. Schematic of proposed single-stage PFC yback with variable boost inductance for HB LED applications.
in series with the LED load is the bias switch Q
C
in Fig. 9.
When main switch Q
1
is turned on, diode D
8
is forward biased,
peak charging capacitor C
1
with a voltage
V
C
1
=

2V
IN

N
1
N
P
V
B

N
3
N
L
B
V
D
8
(1)
where N
1
, N
P
, and N
L
B
are the number of turns of the feedback
winding, primary winding of the yback transformer, and the
boost-inductor winding, respectively. A proper number of turns
N
3
(N
3
= 2) is chosen so that the voltage across capacitor C
1
turns on Zener diode ZD
1
(V
ZD
1
= 10 V) only at high line (180
270 V
rms
). When ZD
1
is turned on, switch Q
4
is turned on and
switch Q
3
is turned off. As a result, the gate-to-source voltage of
MOSFETQ
2
is high and Q
2
is turned on. The load current ows
through switch Q
2
and the bias current of control winding N
C
is approximately zero. Therefore, the boost inductance remains
unchanged. It should be noted that the turn-on resistance of
switch Q
2
needs to be negligible compared to the resistance
of control winding N
C
to prevent a substantial current owing
through the control winding at high line. Otherwise, the effective
boost inductance would become lower and voltage V
B
would
increase to an undesirable level. At low line, the voltage across
capacitor C
1
is lower than the turn-on voltage of ZD
1
, Q
4
is
turned off and Q
3
is turned on. As a result, the gate-to-source
voltage of MOSFET Q
2
is low and Q
2
is turned off. The entire
load current ows through the control winding. Therefore, the
boost inductance is reduced.
C. Design Considerations
The design of the yback circuit in Fig. 10 without the PFC
part is basically the same as the design of the conventional
yback circuit. Key design parameters of the PFC part of the
yback circuit in Fig. 10 are number of turns N
1
and boost
inductance L
B
. The design goal is to achieve a proper PFC
operation, i.e., the line current to meet the IEC 61000-3-2 and
JIS C 61000-3-2 class C current harmonic limits, and to limit
bulk-capacitor voltage V
B
below 400 V.
It was shown in [13] that bulk-capacitor voltage V
B
is a
function of input voltage v
IN
, ratio of inductances L
B
/L
M
,
Fig. 11. Calculated voltage V
B
versus ratio N
1
/N
P
.
ratio of number of turns N
1
/N
P
, and output voltage V
O
, i.e.,
V
B
= f(v
IN
, L
B
/L
M
, N
1
/N
P
, V
O
). (2)
The bulk-capacitor voltage increases with increasing rms
value of the line voltage, and it decreases with increasing turns
ratio N
1
/N
P
and increasing ratio L
B
/L
M
of inductances, as il-
lustrated in Figs. 11 and 12, respectively. It should be noted
that V
B
does not depend on the load current as explained
in [6].
For proper PFCoperation, in order to meet the IEC61000-3-2
and JIS C 61000-3-2 class C limits, the zero-crossing distortion
of the line current due to the tapping of the primary winding
should be optimized, and the boost inductor should be prevented
from operating in CCM.
Following the same procedure for the analysis of the bulk-
capacitor voltage as in [13], the line-current waveform and the
corresponding THD can be obtained. For example, calculated
line-current waveforms at three different turns ratios N
1
/N
P
,
at nominal low line (V
IN
= 120 V
rms
) are shown in Fig. 13. It
follows from Fig. 13 that with increasing turns ratio N
1
/N
P
the
dead-angle of the line current around zero crossing increases,
resulting in an increased THD. As another example, Fig. 14
1584 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 3, MARCH 2012
Fig. 12. Calculated voltage V
B
versus ratio L
B
/L
M
.
Fig. 13. Calculated line-current waveforms for different ratios N
1
/N
P
.
Fig. 14. Calculated THD versus ratio N
1
/N
P
at V
IN
= 230 V
rms
.
shows calculated THD versus N
1
/N
P
for three different values
of L
B
, at nominal high line (V
IN
= 230 V
rms
). It follows from
Fig. 14 that THD signicantly increases with increasing ratio
N
1
/N
P
, whereas the presented variation of L
B
does not have
signicant effect on THD. It can be seen in Fig. 14 that for a
Fig. 15. Desired range for ratio L
B
/L
M
versus ratio N
1
/N
P
: (a) in low
line-voltage range; (b) in high line-voltage range.
THDlower than 20%, which is a typical requirement for lighting
applications, turns ratio N
1
/N
P
should be smaller than 0.15.
In order to ensure DCM operation of boost inductor L
B
,
the time to completely reset the boost-inductor core should be
shorter than the turn-off time of switch Q
1
around the peak of
the line voltage (worst case), i.e.,
T
RES LB
T
OFF Q1
. (3)
In this way, the current owing through the boost inductor
decreases to zero before switch Q
1
is turned on, ensuring a high
power factor and a low THD.
The time to completely reset the boost-inductor core and the
turn-off time of switch Q
1
operating at DCM/CCM boundary
can be, respectively, expressed as
T
RES LB
=
(v
rec
IN
N
1
V
B
/N
P
)N
P
V
O
/N
S
[V
B
+ (1 N
1
/N
P
)N
P
V
O
/N
S
v
rec
IN
](V
B
+N
P
V
O
/N
S
)
T
S
(4)
and
T
OFF Q1
=

1
V
O
N
P
/N
S
V
B
+V
O
N
P
/N
S

T
S
(5)
where T
S
is the switching period of switch Q
1
and v
rec
IN
is the
instantaneous rectied line voltage.
HU et al.: SINGLE-STAGE, UNIVERSAL-INPUT AC/DC LED DRIVER WITH CURRENT-CONTROLLED VARIABLE PFC BOOST INDUCTOR 1585
Fig. 16. Proposed variable boost inductor.
Using (2)(5), the maximum ratio L
B
/L
M
versus N
1
/N
P
that will ensure DCM operation of L
B
can be obtained. In
Fig. 15(a), the calculated maximumratio L
B
/L
M
versus N
1
/N
P
that ensures DCM operation of L
B
is presented at nominal low
line (120 V
rms
). Fig. 15(a) also includes the calculated minimum
L
B
/L
M
versus N
1
/N
P
that ensures limiting the bulk-capacitor
voltage below 400 V at the upper end of the low line-voltage
range (i.e., 140 V
rms
).
The calculated maximumand minimumratios L
B
/L
M
versus
N
1
/N
P
in the high line-voltage range are presented in Fig. 15(b).
As follows from Fig. 15(b), in the high line-voltage range, the
possible range of ratio L
B
/L
M
is much narrower than in the
low line-voltage range. It also follows from Fig. 15(b) that the
minimum possible turns ratio N
1
/N
P
is 0.1.
It can be clearly seen fromFig. 15 that different ratios L
B
/L
M
are required in the low line-voltage range and in the high line-
voltage range, i.e., that a variable boost inductance is required
in the universal line-voltage range.
Based on the calculated results presented in Figs. 1114, turns
ratio N
1
/N
P
= 0.13 (N
1
=4, N
P
=30) is selected for the nal
design. It follows from Fig. 15(b) that for N
1
/N
P
= 0.13 in the
high line-voltage range, ratio L
B
/L
M
should be around 0.6,
i.e., the desired boost inductance is 390 H for the selected
L
M
= 645 H.
Finally, it follows from Fig. 15(a) that for N
1
/N
P
= 0.13 in
the low line-voltage range, ratio L
B
/L
M
should be smaller than
0.32, i.e., the desired boost inductance should be smaller than
206H for the selected L
M
= 645 H.
IV. EXPERIMENTAL RESULTS
To verify the proposed variable boost-inductance technique,
a 24-V/91-W single-stage PFC yback prototype for HB LED
applications was built. The control circuit is based on the quasi-
resonant controller NCP1207 from On Semiconductor. Fig. 16
Fig. 17. Measured boost inductance versus dc-bias current.
Fig. 18. Measured voltage v
Cc
[50 mV/div] across capacitor C
C
and mea-
sured current i
C
[2 A/div] through control winding at nominal low line (120
V
rms
) and full load (I
O
= 3.8 A). Two bottom traces obtained by zooming in
around peak value of current i
C
.
shows a photograph of the proposed current-controlled variable
boost inductor, while Fig. 17 shows the measured inductance
versus dc-bias current. As shown in Fig. 17, the effective induc-
tance drops faster with increasing dc-bias current when the turns
number N
C
of the control winding is higher, and therefore, it
requires a lower dc-bias current. However, a higher turns num-
ber N
C
leads to a higher resistance, hence, higher winding loss
at the same load current. Moreover, a lower boost inductance
generally results in a lower overall efciency of the LED driver.
Therefore, turns number N
C
should be minimized to ensure
low-enough boost inductance and DCM operation at low line
while maintaining relatively high efciency. A turns number
N
C
= 12 was selected for the nal design. The dc resistance
of winding N
C
is 20 m, while the turn-ON resistance of bias
switch Q
2
is 1.8 m (<<20 m). At low line, switch Q
2
is
turned off, and the entire load current I
O
= 3.8 Aows through
the control winding resulting in a power loss of 0.29 W, i.e.,
a 0.3% decrease of efciency. At high line, bias switch Q
2
is
turned on and control winding N
C
is essentially shorted since
1586 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 3, MARCH 2012
Fig. 19. Measured line-current (500 mA/div) and line-voltage (100 V/div)
waveforms: (a) V
IN
= 120 V
rms
; (b) V
IN
= 230 V
rms
.
its dc resistance is much higher than the turn-ON resistance of
switch Q
2
, resulting in a power loss of 22 mW at I
O
= 3.8 A.
The measured voltage across capacitor C
C
and the mea-
sured current through the control winding at nominal low line
(120 V
rms
) and full load (I
O
= 3.8 A) are shown in Fig. 18.
In the worst case (maximum ripple current), the peak-to-peak
value of capacitor C
C
voltage is around 100 mV (neglecting the
high-frequency noise), whereas the peak-to-peak value of the
ac ripple current is 3.4 A. Without the external inductor L
C
, the
peak-to-peak value of the ac ripple current increases to 7 A.
The measured line-voltage and line-current waveforms at full
load are shown in Fig. 19. At nominal low line (120 V
rms
),
THD = 15%, PF = 0.985, V
B
= 171 V, and efciency = 88%;
while at nominal high line (230 V
rms
), THD = 10.39%, PF
= 0.947, V
B
= 327 V, and efciency = 91% were obtained.
It should be noted that THD = 15% measured at 120 V
rms
is
Fig. 20. Measured line-current harmonics at (a) V
IN
= 120 V
rms
; (b) V
IN
=
230 V
rms
.
in good agreement with the calculated value (13.1%) shown in
Fig. 13. It should be also noted that THD = 10.39% measured
at 230 V
rms
is in good agreement with the calculated value
(10%) shown in Fig. 14 at N
1
/N
P
= 0.1 and L
B
= 400 H.
Measured line-current harmonics at full load are shown in
Fig. 20. It can be seen that the line-current harmonics are below
the IEC 61000-3-2 and JIS C 61000-3-2 class C limits with
enough margin. The measured efciency versus output power
is shown in Fig. 21. It should be noted that the measured ef-
ciency at full load is well above 85%, which is the typical
requirement at full load. The maximum bulk-capacitor voltage,
obtained at V
IN
= 270 V
rms
, is V
B max
= 398 V, which is in
good agreement with the calculated value shown in Fig. 12 at
L
B
/L
M
= 0.6.
Measurements with an actual LED load were also performed.
Four LED strings each with 7 series-connected white LEDs
(Philips Lumileds, LXHL-LW3 C) were paralleled and directly
driven by the proposed PFC yback prototype with an output
voltage of 24 V. The measured waveform of the LED current at
nominal low line (120 V
rms
) and full load is shown in Fig. 22.
The peak-to-peak value of the ac ripple current is 4.6% of the
full load current (3.8 A). At nominal high line (230 V
rms
), the
measured peak-to-peak ac ripple current is 2.8% of the full load
current.
HU et al.: SINGLE-STAGE, UNIVERSAL-INPUT AC/DC LED DRIVER WITH CURRENT-CONTROLLED VARIABLE PFC BOOST INDUCTOR 1587
Fig. 21. Measured efciency versus output power.
Fig. 22. Measured waveform of LED current at nominal low line (120 V
rms
)
and full load. Top trace: I
O
[1 A/div, 2 ms/div]; bottom trace: I
O RIPPLE
[50 mA/div, 10 s/div].
V. SUMMARY
A single-stage PFC yback with a variable boost inductance
for HB LED applications for the universal input voltage is pre-
sented in this paper. The boost inductance has a constant high
value at high line, while at low line it is reduced proportionally
to the load current. Experimental results obtained on a 24-V/91-
W prototype show that the proposed PFC converter achieves an
efciency of 88%, a power factor of 0.985 and a THD of 15%
at nominal low line (120 V
rms
), and an efciency of 91%, a
power factor of 0.947 and a THD of 10.39% at nominal high
line (230 V
rms
). Line-current harmonics satisfy the IEC 61000-
3-2 and corresponding Japanese JIS C 61000-3-2 class C limits
with enough margin. The maximum bulk-capacitor voltage is
slightly less than 400 V.
Therefore, the proposed PFC yback circuit is suitable for
directly driving LED strings, and no post-regulators are nec-
essary, which is a signicant advantage over the conventional
PFC yback circuit without an energy-storage capacitor at the
primary side.
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Yuequan Hu received the Bachelors and Masters
degrees in mechanical engineering, and the Ph.D. de-
gree in electrical engineering from the University of
Science and Technology of China, Hefei, China, in
1989, 1992, and 1999, respectively.
From May 2003 to Oct. 2010, he was an R&D
member of the Power Electronics Laboratory, Delta
Products Corporation. Since November 2010, he has
been a Senior Design Engineer at Cree Inc., a market-
leading innovator and manufacturer of lighting-class
LEDs, indoor and outdoor lighting, and semiconduc-
tor solutions for wireless and power applications. His main research interests
focus on high-intensity discharge (HID) lamp ballasts and advanced LED light-
ing solutions.
1588 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 3, MARCH 2012
Laszlo Huber (M86) was born in Novi Sad, Yu-
goslavia, in 1953. He received the Dipl. Eng. de-
gree from the University of Novi Sad, Novi Sad, in
1977, the M.S. degree from the University of Ni s,
Ni s, Yugoslavia, in 1977, and the Ph.D. degree from
the University of Novi Sad in 1992, all in electrical
engineering.
From 1977 to 1992, he was an Instructor at the In-
stitute for Power and Electronics, University of Novi
Sad. In 1992, he joined the Virginia Power Electron-
ics Center, Virginia Tech, Blacksburg, as a Visiting
Professor. From1993 to 1994, he was a Research Scientist at the Virginia Power
Electronics Center. Since 1994, he has been a Senior Member of the R&D Staff,
Power Electronics Laboratory, Delta Products Corporation, Research Triangle
Park, NC, the Advanced R&D unit of Delta Electronics, Inc., Taiwan, one of
the worlds largest manufacturers of power supplies. His 33-year experience
includes the analysis, simulation, and design of high-frequency, high-power-
density, single-phase and three-phase power processors; modeling, simulation,
evaluation, and application of high-power semiconductor devices; and model-
ing, simulation, analysis, and design of analog and digital electronics circuits.
He has authored or coauthored 80 technical papers. He holds ve U.S. patents.
Dr. Huber is the recipient of the IEEE Power Electronics Society (PELS)
Transactions Prize Paper Award for the best paper published in 2009 and the
Yugoslav Conference on Electronics, Telecommunication, Automation, and Nu-
clear Technique (ETAN) Best Paper Award in 1990.
Milan M. Jovanovi c (S85M88SM89F01)
was born in Belgrade, Serbia. He received the Dipl.
Ing. degree in electrical engineering fromthe Univer-
sity of Belgrade, Belgrade.
He is currently the Chief Technology Ofcer of the
Power Systems Business Group, Delta Electronics,
Inc., Taiwan, one of the worlds largest manufactur-
ers of power supplies, and Vice President for R&D of
Delta Products Corporation, Research Triangle Park,
NC.