IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO.

6, JUNE 2005

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A 2.4-GHz RF Sampling Receiver Front-End

in 0.18-m CMOS
Darius Jakonis, Kalle Folkesson, Jerzy D browski, Patrik Eriksson, Member, IEEE, and
a
Christer Svensson, Fellow, IEEE

AbstractThis paper presents an integrable RF sampling receiver front-end architecture, based on a switched-capacitor (SC)
RF sampling downconversion (RFSD) lter, for WLAN applications in a 2.4-GHz band. The RFSD lter test chip is fabricated in
a 0.18- m CMOS technology and the measurement results show
a successful realization of RF sampling, quadrature downconversion, tunable anti-alias ltering, downconversion to baseband, and
decimation of the sampling rate. By changing the input sampling
rate, the RFSD lter can be tuned to different RF channels. A
maximum input sampling rate of 1072 MS/s has been achieved.
A single-phase clock is used for the quadrature downconversion
and the bandpass operation is realized by a 23-tap FIR lter. The
RFSD lter has an
3 of 5.5 dBm, a gain of 1 dB, and more
than 17 dB rejection of alias bands. The measured image rejection
is 59 dB and the sampling clock jitter is 0.64 ps. The test chip consumes 47 mW in the analog part and 40 mW in the digital part. It
occupies an area of 1 mm2 .

IIP +

Index TermsBandpass lters, CMOS analog integrated circuits, mixers, radio receivers, sample and hold circuits, switchedcapacitor lters.

I. INTRODUCTION

HE rapid growth of wireless communications and the

emergence of new standards increases the demand for low
cost multimode radio receivers. For portable battery-powered
receivers, a high level of integration, high exibility, and low
power dissipation are essential issues [1]. One approach to
achieve multimode operation in a receiver is to design hardware, which can be recongured by software. This approach is
known as software-dened radio [2].
In transition from traditional radio architectures to software-dened radio, most signal processing is shifted from
the analog to the digital domain. This imposes more stringent
performance requirements on the analog-to-digital (A/D) conversion, where a high dynamic range must be combined with a
high sampling rate [3]. A too tough requirement on dynamic
range leads to excessive power consumption, inhibiting the use
of software-dened radio in portable receivers [4]. To relax the
requirements for high dynamic range and high sampling rate,
discrete-time signal processing can be employed prior to the
A/D converter. Switched-capacitor (SC) circuits are often used

Manuscript received May 11, 2004; revised February 16, 2004. This work
was supported by Intel Corporation and the STRINGENT program.
D. Jakonis is with Acreo AB, S-60221 Norrkping, Sweden, and also with
the Department of Electrical Engineering, Linkping University, S-58183
Linkping, Sweden (e-mail: darja@isy.liu.se).
K. Folkesson, J. D browski, and C. Svensson are with the Department of
a
Electrical Engineering, Linkping University, S-58183 Linkping, Sweden.
P. Eriksson is with Wavebreaker AB, S-60186 Norrkping, Sweden.
Digital Object Identier 10.1109/JSSC.2005.848027

Fig. 1. RF sampling receiver front-end architecture with the corresponding

frequency partitioning.

to perform discrete-time operations in the analog domain [5].

Since the SC circuits sample a time-continuous input signal, no
additional sample-and-hold (S/H) circuit is needed in the A/D
converter. In radio receivers the SC circuits can be employed
for signal sampling, downconversion, ltering, and decimation
[6]. If an S/H mixer is used for signal downconversion, it
usually shows a high linearity at relatively low power dissipation. For a proper choice of sampling rate in the S/H mixer
and quadrature phase
components
[7], both in-phase
can be obtained by using a single-phase local oscillator [8].
The feasibility of signal sampling directly at radio frequency
(RF) has previously been demonstrated in CMOS technology
[9][11]. More recently, a direct RF sampling receiver with
discrete-time signal processing in CMOS technology has been
presented [12].
In this paper we propose a new radio receiver architecture,
which is based on an RF sampling downconversion (RFSD)
lter. This discrete-time multifunctional block combines RF
sampling, quadrature downconversion, tunable anti-alias ltering at intermediate frequency (IF), downconversion to baseband (BB), and decimation of the sampling rate. High-speed
operation and stability are achieved by avoiding closed-loop
structures. The IEEE 802.11b and 802.11g wireless local area
network (WLAN) standards in the 2.4-GHz band [13] are
chosen as a target for the radio front-end implementation. The
test chip is designed in a 0.18- m CMOS technology and does
not include the low-noise amplier (LNA) and A/D converters.
The organization of this paper is as follows. Section II reviews
the proposed receiver architecture. In Section III the RFSD lter
design is described. Section IV presents experimental results
with the test chip layout issues, performed measurement and
discussion on the achieved RFSD lter performance. Finally, in
Section V, the paper is summarized with conclusions.

0018-9200/$20.00 2005 IEEE

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Fig. 2. RF sampling receiver front-end frequency downconversion, anti-alias ltering, and decimation.

II. RF SAMPLING FRONT-END ARCHITECTURE

conversion to the baseband. Then the intermediate frequency

is derived as [8], [16]

A. Block Description
The proposed RF sampling receiver front-end architecture is
shown in Fig. 1. It comprises an RF lter, a tuned LNA, an S/H
mixer, downconversion lters, A/D converters, and a clock path.
is selected and
At the RF lter the whole frequency band
are suppressed (Fig. 2). The signal
the image frequencies
is then amplied and ltered by the tuned LNA to further improve RF selectivity and to provide sufcient protection against
aliasing in the subsampling process. It is important to note that
the LNA needs to be tuned to prevent aliasing of its amplied
input referred noise. If the LNA is not tuned, it must instead
be followed by an additional lter. The RF lter and tunable
LNA selectivity sets the requirements for the choice of IF. The
S/H mixer samples the output of the tuned LNA and thereby
downconverts the RF signal to IF. Since the signal is bandpass
should be higher than
sampled, the intermediate frequency
half of the RF band
or, equivalently, the sampling rate
should be higher than
to avoid in-band aliasing. By
choosing a high IF, the requirements on RF selectivity can hence
be relaxed. For RF signal downconversion to IF quadrature components and , the S/H mixer sampling rate should be selected
from the following expression [14]:

(3)
To reduce noise aliasing in RF signal subsampling, a high sampling rate is desirable. On the other hand, a too high sampling
rate is not suitable for the A/D converter due to excessive power
dissipation. One method to combine these requirements is to reduce the sampling rate by signal decimation. If the sampling rate
is decimated by , then the resulting sampling rate in the A/D
converter is given by
(4)
The decimation operation can also be employed for signal
downconversion to the baseband. In this case, the decimated
should be equal to
or its submultiple
sampling rate
in (4)
frequency. To satisfy this requirement, the ratio
should be an integer number. Due to the downconversion
operation in decimation, a number of frequencies can alias
into the baseband. Alias band center frequencies around IF are
expressed as

(1)

(5)

is the channel center frequency at RF. From (1) the

where
phase difference between adjacent samples at is

Therefore, these frequencies must be sufciently suppressed by

ltering prior to downconversion, as demonstrated in Fig. 2.
This imposes a requirement on the anti-alias lter bandwidth,
formulated as

(2)

(6)
Since the phase difference between S/H mixer output samples
is equivalent to 90 degrees, they can be sorted into even path
samples and odd path samples. Thus, a quadrature downconversion operation is accomplished by using one sampling clock.
In this context, quadrature downconversion is necessary to distinguish the wanted band and its image in the next step of down-

where
is the signal bandwidth. Here, the anti-alias lter
should be placed at the intermediate frequency
.
For anti-alias ltering and signal downconversion to baseband, the downconversion lter block is used in the and
output branches of the S/H mixer (Fig. 1). In this context, the

JAKONIS et al.: A 2.4-GHz RF SAMPLING RECEIVER FRONT-END IN 0.18- m CMOS

and paths are required to separate the wanted signal band

and its mirror image band in the downconversion to baseband
(Fig. 2). The unwanted image band can later be removed in the
digital domain [17].
at the downconversion lter output
The baseband signal
. For the signal
is digitized in the A/D converter at the rate
bandwidth digitization, the A/D converter sampling rate should
. If a number of channels is digitized,
be higher than
the desired channel selection can be done in the digital domain.
Clock phases for the S/H mixer, the downconversion lters, and
the A/D converter are generated in a clock path block from a
single local oscillator (LO) signal (Fig. 1).
The RF sampling receiver front-end architecture has a number
of benets. First, the quadrature downconversion operation can
be performed with a single clock phase [8]. Second, the A/D converter performance requirements are relaxed due to discrete-time
signal processing prior to digitization. Third, the downconversion lter passband is a function of the sampling frequency. As
a result, the anti-alias bandpass lter can be tuned to different
frequency bands by changing the sampling rate. This increases
the exibility to choose a wanted frequency band.
However, there are some drawbacks in the proposed architecture as well. One of them is the noise aliasing into the baseband
due to subsampling [14], [15]. Furthermore, in the employed
quadrature sampling a time misalignment error is introduced,
because the and samples are not taken at the same time [17].
This error represents an imbalance between and paths and,
thereby, degrades the image rejection. To reduce the time misalignment error, a large ratio between the sampling frequency
and the signal bandwidth should be used. In addition, signal
sampling at RF is sensitive to clock jitter [18], [19]. A variation
of the sampling instant results in a sampled voltage error [20].
To have a low sampling clock jitter, the clock generation blocks
should both be designed for low noise and not be susceptible to
power supply variation and substrate noise.
To prove the feasibility of the proposed architecture, we focus
on the design of an RF sampling downconversion lter (Fig. 1).
In this perspective, the RFSD lter, as a multifunctional block,
should show the possibilities of analog discrete-time signal processing for integrable receiver front-end applications.
B. Frequency Plan for WLAN
For the IEEE 802.11 b/g WLAN standards, the assigned frequency band
is from 2.4 to 2.484 GHz [13]. The maxis 22 MHz and the minimum
imum signal bandwidth
adjacent channel separation is 25 MHz. To derive a frequency
plan for the RF sampling receiver architecture, the rst channel
is selected at 2.412 GHz. The S/H mixer
center frequency
input sampling rate can be calculated from (1). If the closest
RF images
should be suppressed by 60 dB, a high input sampling rate is needed. An integer number , equal to 5, gives
an input sampling rate of 1072 MS/s. In this case, the closest RF
images are placed 536 MHz away from the RF lter center frequency 2.450 GHz. A commercially available off-chip RF lter
can suppress these images by 47 dB. The remaining suppression
of 13 dB is performed by an on-chip tunable LNA. The input
sampling rate 1072 MS/s results in an intermediate frequency of
268 MHz, which is obtained from (3). By choosing a sampling

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TABLE I
FREQUENCY PLAN FOR IEEE 802.11b/g RECEIVER FRONT-END

Fig. 3. S/H mixer schematic. The RF input signal is downconverted to the IF

output by sampling at a rate f .

frequency decimation factor equal to 12 in (4), the downconis derived

version lter and A/D converter sampling rate
to be 89.3 MS/s. By using (6), we arrive to a maximum downconversion lter anti-alias bandwidth of 157 MHz. If a lower
is chosen, this iminput sampling rate of 567.5 MS/s
poses higher requirements on RF lter and the tunable LNA
selectivity, because the closest RF images are only 284 MHz
away from the RF lter center frequency. In this context, the RF
lter can suppress images by 35 dB, leaving 25 dB to be suppressed by the tunable LNA. As a result, the input sampling rate
of 1072 MS/s is more attractive due to relaxed requirements on
the tunable LNA selectivity.
In general, the out-of-band frequencies should be rejected by
40 dB. This formulates the combined selectivity requirement for
the tunable LNA and the RFSD lter. The tunable LNA should
have a passband of 80 MHz, which is centered at 2.450 GHz
frequency.
The described RF sampling receiver front-end frequency plan
for the 2.4-GHz WLAN standards is summarized in Table I.
III. RF SAMPLING DOWNCONVERSION FILTER DESIGN
The RF sampling downconversion (RFSD) lter (Fig. 1) was
designed in a 0.18- m CMOS process. It consists of an S/H
mixer, downconversion lters, output buffers, and a clock path
block. In this section a detailed description of the RFSD lter
blocks is provided.
A. S/H Mixer
In the S/H mixer, shown in Fig. 3, the RF signal at the input
IN is quadrature downconverted to IF at the output OUT. This
passive type mixer is based on a track-and-hold circuit. The S/H
mixer comprises an nMOS transistor as a sampling switch, a
and , comsampling capacitor , and pMOS transistors
prising a source follower stage. The source follower isolates

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the sampling capacitor

from the following stages and drives
the downconversion lter input capacitive load. The transistor
width/length ratios in Fig. 3 are given in micrometers. The sampling capacitor size was chosen as a trade-off between the required analog input bandwidth and sampled noise. By evaluating the sampled and held noise voltage in the signal channel
band, we arrive at the following expression [21]:
(7)
where
is the hold time duty cycle in the track-and-hold
, which is a case when
circuit. Here, it is assumed that
the track time is equal to the hold time in the track-and-hold
circuit. In this context, is Boltzmanns constant and is the
absolute temperature. To reduce the sampled and held noise (7),
is needed or alternatively the sama large sampling capacitor
should be increased. In the source follower the
pling rate
transconductance.
thermal noise is related to the transistor
transistor makes the thermal noise in the
In this case a wide
source follower negligible in comparison to the sampled and
held noise originating from the sampling transistor . For that
reason, the source follower thermal noise is not included here.
Since the S/H mixer noise is dominated by the sampled and held
noise, it is compared to the noise at the LNA output. Here, we
assume a receiver sensitivity level of 80 dBm [22], a required
signal-to-noise ratio (SNR) of 10 dB and an LNA gain of 33 dB.
Then the resulting signal channel noise level at the LNA output
is 57 dBm. For a selected 1 pF sampling capacitor and input
sampling rate 1072 MS/s, the S/H mixer sampled and held noise
power is 91 dBm. This indicates a reasonable choice of the
sampling capacitor . A more detailed noise analysis is provided in the Appendix. The designed S/H mixer analog input
bandwidth is 4.55 GHz. The source follower stage has a power
gain of 0.65 dB and an output bandwidth of 1.58 GHz. In general, the S/H mixer performance can be signicantly affected by
clock jitter. Therefore, a low jitter clock path is needed to provide the clock for the S/H mixer. In comparison to a switching
mixer, the S/H mixer is not inferior in terms of jitter-induced
noise. It has been shown that jitter-induced SNR for a sampling
mixer is the same as for a typical switching mixer for a given
oscillator phase noise [19].
B. Downconversion Filter
The downconversion lter is illustrated in Fig. 4(a). Its singleended input
is applied to the sampled IF signal from the
S/H mixer. In the downconversion lter, the signal is bandpass
ltered, decimated, and downconverted to baseband. A similar
approach for signal ltering and decimation is described in [6]
and [23].
A nite input response (FIR) lter was employed to realize a
bandpass ltering operation. In -domain, a FIR lter discretetime transfer function is expressed as
(8)
where
is the lter coefcient and
is the number of lter
coefcients (taps). The FIR lter has been designed to suppress
alias frequencies given by (5). It has an anti-alias bandwidth,

Fig. 4. Downconversion lter. (a) Schematic. (b) 23-tap FIR lter nonzero
coefcient values and corresponding switched capacitors.

formulated in (6). The lter coefcients were obtained by using

function in Matlab [24]. To simplify the FIR lter imthe
plementation, an odd number of 23 taps was chosen. This satised the lter bandwidth requirement and resulted in every other
equal to zero, i.e.,
.
coefcient
The resulting 11 nonzero FIR lter coefcients are shown in
Fig. 4(b). Here, the coefcient values are rounded to integer
numbers for good matching in SC realization. Thus, the designed FIR lter transfer function is given by

(9)
where
corresponds to a time delay, equal to the sampling
period
. The FIR lter frequency response for the samMS/s is shown in Fig. 5. Since the antipling rate
alias bandpass lter frequency response depends on the sampling rate, it can easily be tuned to different frequency bands by
varying .
A unit capacitor corresponds to the lowest coefcient value.
This solution makes possible to reuse the same unit capacitor
for all coefcient values. In this approach every lter coefcient
is accomplished by a switched capacitor, which comprises a
number of parallel unit capacitors. Since the nonzero coefcient
values are symmetrical around the highest value, the lter implementation is additionally simplied. In this case only 6 different
capacitance values are needed to realize 11 lter coefcients.
In the downconversion lter, the IF signal is sequentially sam
and

by a set of
pled on weighted capacitors
switches, connected to the input. Next, the weighted capacitor
charges are added together by another set of switches. Unlike

JAKONIS et al.: A 2.4-GHz RF SAMPLING RECEIVER FRONT-END IN 0.18- m CMOS

Fig. 5. FIR bandpass lter frequency response for the sampling rate f
1072 MS/s. Dashed lines indicate the signal bandwidth BW .

[6] and [23], to accomplish negative coefcient values in the

transfer function (9), the switched capacitors were grouped into

and another array

one array of negative coefcients

[Fig. 4(a)]. The arrays of posof positive coefcients

itive and negative coefcients are connected to the differential
outputs OUTp and OUTn, respectively. As a result, the negative output OUTn voltage is subtracted from the positive output
OUTp voltage. By downconverting the single-ended IF signal
to a differential baseband signal, an extra power gain of 6 dB
is achieved without any additional circuitry. This explains the
coefcient 1/52 in the transfer function (9). Since every second
coefcient in the FIR lter is zero, two available sampling clock
periods are used for coefcient multiplication [Fig. 4(b)]. This
minimizes the settling error, because the available time to load
the switched capacitor is longer. The charge injection and clock
feedthrough errors in the downconversion lter are reduced by
choosing small size nMOS switches as shown in Fig. 4(a). Since
all switches in the downconversion lter are equal in size, the
capacitive load to the switch drivers is balanced.
To decimate and downconvert the IF signal to baseband, the
switched capacitor voltages are resampled at a lower clock rate
[Fig. 4(a)]. This is different from the traditional FIR lter implementation, where the output signal rate is usually equal to the
input rate. Due to a lower output rate, the amount of hardware
has to be
is considerably reduced, as only one sample out of
calculated. The decimation operation is equivalent to averaging
of the input samples [25]. If samples from coefcient capacitors are averaged, an equivalent sampled noise voltage is given
by [23]

(10)

where
is the total noise charge,
is the total coefis the th coefcient capacitance. As
cient capacitance and
a result, the noise voltage in (10) is equivalent to sampling on

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Fig. 6. RFSD lter output noise power spectral density versus unit capacitor
size. The smallest unit capacitor size represents actual test chip design.

. For this reason, the coefcient caone large capacitor

size can be reduced by the choice of a small unit capacitor
pacitor. Based on the noise analysis provided in the Appendix,
the RFSD lter output noise power spectral density versus unit
capacitor size is shown in Fig. 6. By choosing a large unit capacitor the output noise can be further reduced. However, large unit
capacitors require a large driver. In this design a unit capacitor
size of 11 fF was selected. This resulted in the total capacitance
, comparable to the S/H mixer sampling capacitance .
Since the FIR lter has negative and positive coefcient capacitor arrays, the resampled voltage is kept on the capacitors
and
, respectively. In addition, the downconversion lter is
less sensitive to clock jitter than the S/H mixer. This is because
the S/H mixer tracks an RF signal and then samples it, while
the downconversion lter only resamples the already held signal
voltage.
For the complete implementation of the RFSD lter, both
and path downconversion lter blocks are needed. The
path downconversion lter employs even samples from the S/H
mixer, whereas the
lter employs the odd samples. Since
the downconversion lter uses 24 clock samples for coefcient
operations, time-inmultiplication and charge summation
,
are required to get outterleaved parallel lters , ,
puts ready in 12 clock samples (Fig. 7). This corresponds to the
sampling frequency decimation by 12, which is equal to the
(Table I). In Fig. 7
planned A/D converter sampling rate
the time-interleaved parallel lters are sequentially connected
to the output buffers by the downconversion lter switches.
C. Clock Path
A block diagram of the clock path is shown in Fig. 8(a).
It consists of input amplier stages, inverter buffers (inv),
control logic, and double transmission gates (DTGs). The
,
for
clock path has differential analog inputs
the LO signal and single-ended digital outputs for the clock
, and
, illustrated
phases
in Fig. 8(b). Another set of phases
,
,
,
,
are used for the control logic block and double
and
transmission gates. In Fig. 8(a) the inverter pMOS and nMOS
transistor sizes are denoted above and below the block symbol,

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Fig. 7. RF sampling downconversion lter main blocks. (a) Block diagram. (b) Nonzero coefcient multiplication and summation
time-interleaved outputs are ready after 12 clock samples.

Fig. 8. Clock path. (a) Block diagram. (b) Clock phases to S/H mixer and downconversion lter.

sequence. The

JAKONIS et al.: A 2.4-GHz RF SAMPLING RECEIVER FRONT-END IN 0.18- m CMOS

respectively. As illustrated in Fig. 9, the clock path amplier

comprises a differential stage and an inverter. It has a differential input to suppress the common mode voltage variation. The
single-ended amplier output generates the clock phase . The
control logic block, shown in Fig. 10, consists of inverters, AND
gates, and ip-ops, which act as registers. This block generates
for the double transmisthe clock edge selection phases
sion gates. The clock edge selection phases are intended to capand
signals. These phases keep
ture the edges of the
the double transmission gates (Fig. 11) open to pass the selected
rising or falling edge to the downconversion lter. When the
double transmission gates are closed, the passed clock phase
voltage is held on the parasitic load capacitance until the next
phase captures a seclock edge arrives. As long as the
and
, there is no special relected edge of the signals
quirement on exact timing in the control logic block. By using
this scheme, any phase with transitions on the clock signal can
be generated. It is a very exible method since frequency division, phase shifting, and arbitrary duty cycles are easy to implement. Apart from the initial amplier stage, the only component between the LO clock signal and downconversion lter
is a double transmission gate. Due to the minimized number of
components in the clock signal path, the critical sampling clock
edges are affected very little. Hence, the clock jitter in the sampling clock is reduced. Furthermore, all phases are generated
from a single clock signal, which facilitates very accurate clock
edges. To reduce the load on the amplier stage output, buffered
signals are used for noncritical edges. In addition, the double
transmission gate outputs could be connected to an extra latch
to ensure a constant voltage level. However, this will degrade the
clock edges due to an additional component in the clock signal
path. Therefore, no additional latching of clock phases was included in the implemented clock path.

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Fig. 9. Clock path amplier. A sinewave signal at the differential input is

converted into a squarewave at the single-ended output.

Fig. 10.

Clock path control logic.

Fig. 11.

Clock path double transmission gate (DTG).

D. Output Buffer
The output buffer is illustrated in Fig. 12. It is a unity-gain
buffer [26] with an input
, which is connected to the downthe buffer is intended
conversion lter output. At the output
to drive an off-chip load of 50 impedance. The unity-gain
buffer consists of a differential pair with an active load and a
source follower in a local feedback loop. Transistors , ,
realize the differential pair, where
acts as a current
and
and
implement the active load. The
source. Transistors
source follower comprises of
and , where
is a current
source. Due to a triple well process with a deep n-well transistor, the substrate of is connected to the drain to increase the
source follower linearity. To improve the stability of the output
is added to the drain of tranunity-gain buffer, a capacitor
sistor . This minimizes the ringing effect in the step response
for a large load capacitance. The unity-gain buffer has a power
gain of 0.86 dB and the output bandwidth is 786 MHz.
IV. EXPERIMENTAL RESULTS
A. Chip Layout
The RFSD lter test chip, shown in Fig. 13, was implemented
and fabricated in 0.18- m CMOS technology. The active core
area is 0.36 mm and the total chip area is 1 mm . There are

24 I/O pads, of which the power supply and bias pads are ESD
protected. To reduce crosstalk between the noisy digital part and
the sensitive analog part, different power supply and ground
pads were used. Decoupling capacitors were connected to the
power supply and bias voltages for on-chip stabilization of these
voltages. Wide power supply wires were employed to decrease
the resistive voltage drop. A termination resistor of 50 was
added to the RFSD lter input for measurement purpose only.
In a monolithic S/H mixer implementation with an LNA on a
single chip such termination is not needed. For mismatch minimization the downconversion lter blocks were symmetrically
placed with respect to the test chip vertical axis and the FIR
lter coefcients were realized in the array of unit capacitors,
illustrated in Fig. 14. Dummy capacitors were added into the

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 6, JUNE 2005

Output unity-gain buffer schematic.

Fig. 14. FIR lter array of unit capacitors. An integer number on the unit
capacitor indicates a set for coefcient capacitor implementation. The dummy
capacitors are realized to reduce mismatch.

Fig. 13. Chip microphotograph. The total chip area including the pads is
1 mm .
Fig. 15.

Unit capacitor layout. (a) Top view. (b) Cross section.

unit capacitor array to improve the layout symmetry and also to

reduce the mismatch. All unit capacitors were designed as interdigitated metalmetal capacitors, demonstrated in Fig. 15. The
downconversion lter block was connected to the clock phase
generation block via a clock bus. This solution simplies the
overall interconnection of blocks and adds the same capacitive
load to all signal wires in the clock bus. In addition, to obtain
lower crosstalk between signal wires, they were shielded by a
ground wire.
B. Measurement
The test chip was directly glued and bonded onto a printed
circuit board (PCB), demonstrated in Fig. 16. In this way the
chip substrate has a reliable contact to the off-chip ground. Furthermore, shorter bonding wires reduce the effect of parasitic
inductance. Since the output buffers are designed to drive 50impedance load, they dissipate more power in comparison to the
other blocks on the test chip. As a result of higher power consumption, the power supply pad for the output buffers is double
bonded to the PCB with two parallel wires.
To evaluate the performance of the designed test chip, a
number of measurements were carried out. The measured

Fig. 16. Top view of the printed circuit board (70 mm

is bonded directly on the board.

2 48 mm). The test chip

RFSD lter test chip shows the correct frequency downconversion operation for the quadrature components, illustrated
in Fig. 17. If the input signal with a frequency of 2.413 GHz
MS/s, the resulting output
is sampled at a rate

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Fig. 17. Measured output quadrature waveforms for the sampling rate f =
1072 MS/s, the analog input frequency f = 2:413 GHz, and the input power
level of 4 dBm.

frequency is 1 MHz. For

in (1) that corresponds to the
difference between the WLAN channel center frequency of
2.412 GHz and the input frequency of 2.413 GHz. Here, the
input signal power level of 4 dBm is used. The RFSD lter
frequency response was measured for the proposed frequency
plan (Table I). In this measurement the input signal frequency
was varied and the corresponding output frequency power
level was estimated. As shown in Fig. 18(a), both single-ended
and differential path lter outputs were examined. The frequency bands, which are folded into the baseband after signal
. The
downconversion and decimation, are indicated as
input signal frequency conversion into the output frequency is
illustrated in Fig. 18(b). The RFSD lter frequency response
demonstrates the input signal frequency downconversion and
bandpass ltering. In this case the RFSD lter is tuned to the
GHz. The input
WLAN channel center frequency
sampling rate of 1072 MS/s is decimated by 12. Consequently,
the output sampling rate is 89.3 MS/s. The RFSD lter has
1 dB gain at 1 MHz output frequency. From the frequency
response [Fig. 18(a)] the alias bands are rejected by more than
17 dB, while the alias band center frequencies are suppressed
better than 18 dB.
The linearity of the RFSD lter was investigated by a twoGHz
tone test (Fig. 19). By applying frequencies
and
GHz at the input, the fundamental component and the intermodulation distortion product were measured at the output frequencies 1.4 MHz and 1.8 MHz, respecMS/s, the input referred
tively. When sampling at
third-order intercept point
was obtained to 5.5 dBm for
the differential path lter output. This is lower than a simuof 11 dBm.
lated
The image rejection was tested by applying the input frequencies 2.412 GHz 2 MHz. The RFSD lter quadrature outputs
were connected to the differential RC-CR phase shifter [27] to
accomplish a 90 degrees phase shift operation on the output frequency of 2 MHz. By combining the and path outputs, an
image rejection of 59 dB was achieved. To estimate the output
noise, the path differential output was connected to the spectrum analyzer. The output noise power spectral density, mea-

Fig. 18. (a) Measured RFSD lter baseband signal output power and (b) output
frequency versus the input signal frequency. The sampling rate f = 1072 MS/s
and the input signal power level is 4 dBm.

sured at 5 MHz output frequency, was at 131 dBm/Hz. This

noise level is in close agreement with the output noise power
spectral density of 135 dBm/Hz, which was derived from the
noise analysis given in the Appendix. The difference between
the measured and calculated noise can be explained by losses
in the RFSD lter blocks. These losses are not included in the
noise analysis. The sampling clock jitter was evaluated from the
SNR versus the input power level measurement [6]. In this context, the input power level was increased until the SNR at the
output reached a saturated value. Then a sampling clock jitter
of 0.64 ps was calculated from the measured value of the saturated SNR. Here, the clock jitter is assumed to limit the saturated
SNR. When using the input sampling frequency of 1072 MS/s,
the power consumption in the analog test chip part was 47 mW,
whereas the digital part dissipated 40 mW. To be more specic,
the digital test chip part included the digital clock path generation blocks.

1274

Fig. 19. RFSD lter linearity measurement. Two-tones with frequencies

f
= 2:413 GHz and f
= 2:4134 GHz were applied at the input. The
input sampling rate f = 1072 MS/s.

In the same way, the RFSD lter performance was also measured for an input sampling rate of 567.5 MS/s. For the WLAN
channel center frequency of 2.412 GHz this sampling rate corin (1). In this case the measured output
responds to
sampling rate was 47.3 MS/s, the corresponding gain was 1 dB
of 13.5 dBm was achieved. The alias bands were
and the
rejected by more than 24 dB, whereas the center frequencies
in these bands were attenuated better than 36 dB. Regarding the
image frequency, the rejection of 29 dB was obtained. An equivalent output noise level was measured to 130 dBm/Hz and the
evaluated sampling clock jitter was 0.54 ps. The overall test chip
power consumption was 70 mW, where the analog and digital
parts consumed 43 mW and 27 mW, respectively.
By changing the input sampling rate, the RFSD lter can be
tuned to different center frequencies of WLAN channels. As
shown in Fig. 20, the input sampling rate of 567.5 MS/s is related to the WLAN channel center frequency of 2.412 GHz. For
a sampling rate of 581.6 MS/s, the WLAN channel, located at
2.472 GHz, is downconverted to the baseband. These results are
in (1). The described RFSD
demonstrated for the case of
lter test chip measurement results are summarized in Table II.
To measure the RFSD lter constellation diagram, a
high-order IEEE 802.11g standard modulation scheme of 64
QAM was used with a maximum data rate of 54 Mb/s. For the
front-end input sampling rate 567.5 MS/s the resulting error
vector magnitude, measured with a vector signal analyzer, was
6.2%. The constellation diagram of the modulated 2.4-GHz
frequency band WLAN signal is shown in Fig. 21.
C. Discussion
As a complement to the measurements at the input sampling
rate 1072 MS/s, another measurements at 567.5 MS/s were
performed. At the lower sampling rate the RFSD lter shows
higher linearity and higher alias band rejection. This indicates
that 1072 MS/s is too close to the frequency limits of the actual
RFSD lter. One of the reasons for the decreased performance
is a speed limit of the clock path leading to degraded clock

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 6, JUNE 2005

Fig. 20. Measured RFSD lter frequency response for different sampling
frequencies. The input signal power level was 4 dBm. Here, a frequency plan
with K = 9 was used.

TABLE II
PERFORMANCE SUMMARY OF THE RFSD FILTER MEASUREMENT

signals to the various switches. A redesign of the clock path

should mitigate this limitation, and lead to full performance
also at 1072 MS/s.
The image rejection obtained by the proposed lter is not sufcient to meet realistic requirements. In order to reach a rejection of 40 dB, the number of lter taps or the output sampling
rate should be increased. In both cases this calls for increased
parallelism. For the present feasibility study the parallelism is
limited to two parallel lters.
Similarly, to limit the power consumption, relatively small
unit capacitors are chosen. This leads to a relatively large output
noise power, although still sufciently low to reach the required
receiver sensitivity with a proper LNA gain. By increasing the
unit capacitor, the output noise could be reduced considerably
(see Fig. 6). This will lead to larger sampling switches and therefore larger digital power consumption.

JAKONIS et al.: A 2.4-GHz RF SAMPLING RECEIVER FRONT-END IN 0.18- m CMOS

Fig. 21.

1275

Measured RFSD lter constellation diagram of a 64 QAM modulated WLAN signal.

By using an LNA with a gain of 33 dB, a receiver sensitivity of

80 dBm is achieved. The maximum input signal to the RFSD
lter is about 4 dBm (0.4 V peak-to-peak), corresponding to
a receiver input level of 37 dBm. This is a sufcient power
level for blocker signals. In order to accept the highest allowed
in-channel signal level of 10 dBm, the tunable LNA needs to
have a variable gain.
V. CONCLUSION
A exible and integrable RF receiver front-end architecture
is proposed in this paper. The front-end comprises a discrete
time multifunctional block performing RF sampling, quadrature downconversion, anti-alias IF ltering, downconversion to
baseband and sampling rate decimation. A test-chip aimed for
demonstrating the feasibility of the new architecture was designed in 0.18- m CMOS technology. IEEE 802.11a/g WLAN
standards were used as target.
Full functionality of the circuit was demonstrated, including
simple tunability and an experimental detection of a 64 QAM
modulated RF signal. Several performance parameters, as
thermal noise level, jitter-induced noise and nonlinearity were
shown to be sufcient for the chosen targets. Nevertheless, the
rejection of alias bands in the proposed RFSD lter needs to be
improved.

The one-sided power spectral density (PSD) of the noise, generated in the S/H mixer switch, has been derived from (7) and
is given by
(11)
. Since the FIR lter has a length of
where
clock samples, this noise is resampled by each section of
. Hence, the noise is folded
the FIR lter at a rate
with a factor
[21]. The averaging operation in the downcon
are
version lter is performed when the switches

are in the
in the off-state, whereas the switches
on-state. After averaging, the resulting voltage of the S/H mixer
noise at the output is expressed as

(12)

where the noise is assumed to be stationary. From (12) the S/H

mixer single-sided noise PSD at the RFSD lter output for baseband frequencies is

APPENDIX
This appendix presents a noise analysis for the RFSD lter.
An equivalent noise model, presented in Fig. 22(a), includes the
S/H mixer and the downconversion lter with one array of positive/negative coefcient capacitors [Fig. 4(a)]. To simplify the
noise analysis, the buffers
and
are assumed to be noiseis neless with a unity gain. Also, the impact of capacitor
glected. In the noise model, three components of thermal noise
sources can be encountered: the noise from the S/H mixer switch
, the noise from the FIR lter switches

,
and the noise from the averaging switches

. Assuming the described circuit is linear, the total output noise will
be calculated by the superposition principle.

(13)

where a factor of 2 has been added to include the positive and

negative coefcient capacitor arrays, connected to the differential output. In (13) the noise PSD is also multiplied by a
factor. For the downconversion lter hold phase duty
cycle
, this factor is close to unity for baseband
frequencies.
The output noise contribution from the FIR lter switches can
be estimated in a similar way. Due to the averaging operation,

1276

Fig. 22.

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 6, JUNE 2005

Noise model. (a) RFSD lter with one array of capacitors. (b) An equivalent circuit for the averaging switch noise contribution.

this noise is given by (10). As a result, the output one-sided noise

, is
PSD, originating from the FIR lter switches

The total one-sided noise PSD at the RFSD lter output is

then calculated by adding the described contributions as

(14)

(17)

where
. In (14) a factor of 2 is included for
positive and negative coefcient capacitor arrays.
Finally, the noise contribution from the averaging switches

should be evaluated. The noise from each switch

can be analyzed separately and then summed by using a superposition principle. An equivalent circuit to describe the avernoise contribution is shown in Fig. 22(b).
aging switch
By using the rst moment approximation, the transfer function
from the node to the node is included in the output noise
voltage expression for the switch

(15)
where
denotes the sum of
capacitors. The corresponding one-sided output noise PSD for the averaging
switches in positive and negative coefcient capacitor arrays is

(16)

This result corresponds to only one ( or

bution to the RFSD lter output.

) path noise contri-

ACKNOWLEDGMENT
The authors would like to thank S. Andersson and ACREO
AB for their help in the test chip design and fabrication.
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16

Darius Jakonis received the B.S. and M.S. degrees

in physics and electronics from Vilnius University,
Lithuania, in 1996 and 1998, respectively. During
19971998, he was a Telecommunication Engineer with State Radio Frequency Service, Vilnius,
Lithuania. In 2004, he received the Ph.D. degree in
electrical engineering from Linkping University,
Sweden.
His research was focused on analog CMOS integrated circuits for signal sampling, downconversion,
ltering, decimation, and A/D conversion. He was investigating new solutions for radio front-end applications, methods to reduce
nonidealities in high-speed sampling, and readout architectures for uncooled
infrared detector arrays. In 2004, he joined Acreo AB in Norrkping, Sweden,
as an RFIC Designer and Development Engineer.

1277

Kalle Folkesson was born in Uppsala, Sweden, in

1974. He received the M.S. and Ph.D. degrees from
Linkping University, Sweden, in 1998 and 2004,
respectively.
He is currently working in the Electronic Devices group, Department of Electrical Engineering,
Linkping University. His research interests include
A/D converter modeling from a system simulation
perspective and multiphase clock generation.

Jerzy D browski received the Ph.D. and D.S. dea

grees form Silesian University of Technology (SUT),
Gliwice, Poland, in 1987 and 2001, respectively.
He has specialized in macromodeling and simulation of analog and mixed-signal circuits. Currently,
he is an Associate Professor at Linkping University, Sweden, and at SUT, Gliwice. His recent
research interests are also in RF ICs design and
design-for-testability for analog/RF circuits. He has
authored or coauthored over 60 research papers in
international journals and conference proceedings.
He holds 12 patents (as a coauthor) in switched-mode power supplies and
measurement circuits.

Patrik Eriksson (M99) was born in Vsters,

Sweden, in 1967. He received the M.S. degree in
computer science from Lule University, Sweden, in
1992.
From 1993 to 2001, he was with Ericsson AB,
Stockholm, Sweden, working with radio technology
at circuit, transceiver architecture, and algorithmic
levels. From 1997 to 2001, he was also conducting
part-time research in RF-sampling receiver architectures at the Royal Institute of Technology,
Stockholm, Sweden. In 2001, he joined Acreo AB,
Norrkping, Sweden, as R&D Manager for the Acreo Socware Center to lead
the development of highly integrated multistandard radio systems. In 2004,
he founded Wavebreaker AB, Norrkping, Sweden, specializing in development of advanced radio transceiver technologies, and has since then been its
Managing Director. His technical interests include circuit and system design of
radio transceivers and signal processing for wireless communications.

Christer Svensson (M96SM01F04) was born

in Bors, Sweden, in 1941. He received the M.S.
and Ph.D. degrees from Chalmers University of
Technology, Sweden, in 1965 and 1970, respectively.
He was with Chalmers University from 1965 to
1978, where he performed research on MOS transistors, nonvolatile memories, and gas sensors. He
joined Linkping University in 1978, and since 1983
has been a Professor in Electronic Devices there. He
initiated a new research group on integrated circuit
design. Svenssons present interests are high-performance and low-power analog and digital CMOS circuit techniques for communication, computing, and sensors. He has published more than 160 papers
in international journals and conferences and holds eight patents. He is a cofounder of several companies, most recently Switchcore AB, Optotronics AB,
and Bluetronics AB.
Dr. Svensson was awarded the Solid-State Circuits Council 19881989 best
paper award. He is a member of the Royal Swedish Academy of Engineering
Sciences.