July 2006 19912007 Cadence Design Systems, Inc. All rights reserved. Portions Apache Software Foundation, Sun Microsystems, Free Software Foundation, Inc., Regents of the University of California, Massachusetts Institute of Technology, University of Florida. Used by permission. Printed in the United States of America. Cadence Design Systems, Inc. (Cadence), 2655 Seely Ave., San Jose, CA 95134, USA. Allegro PCB SI SigXplorer contains technology licensed from, and copyrighted by: Apache Software Foundation, 1901 Munsey Drive Forest Hill, MD 21050, USA 2000-2005, Apache Software Foundation. Sun Microsystems, 4150 Network Circle, Santa Clara, CA 95054 USA 1994-2007, Sun Microsystems, Inc. Free Software Foundation, 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 1989, 1991, Free Software Foundation, Inc. Regents of the University of California, Sun Microsystems, Inc., Scriptics Corporation, 2001, Regents of the University of California. Daniel Stenberg, 1996 - 2006, Daniel Stenberg. UMFPACK 2005, Timothy A. Davis, University of Florida, (davis@cise.ulf.edu). Ken Martin, Will Schroeder, Bill Lorensen 1993-2002, Ken Martin, Will Schroeder, Bill Lorensen. Massachusetts Institute of Technology, 77 Massachusetts Avenue, Cambridge, Massachusetts, USA 2003, the Board of Trustees of Massachusetts Institute of Technology. All rights reserved. Trademarks: Trademarks and service marks of Cadence Design Systems, Inc. contained in this document are attributed to Cadence with the appropriate symbol. For queries regarding Cadences trademarks, contact the corporate legal department at the address shown above or call 800.862.4522. Open SystemC, Open SystemC Initiative, OSCI, SystemC, and SystemC Initiative are trademarks or registered trademarks of Open SystemC Initiative, Inc. in the United States and other countries and are used with permission. All other trademarks are the property of their respective holders. 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Allegro PCB SI SigXplorer L Series Tutorial July 2006 3 Product Version 15.7 Lesson 1......................................................................................................................... 5 Welcome . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 About Online Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Working with Database Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Board databases used in this tutorial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Starting the Tutorial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Controlling your View of the design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Save the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 To Summarize What You Have Learned . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Lesson 2....................................................................................................................... 13 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Working with a Single Net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Extracting a Net Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 To Summarize What You Have Learned . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Lesson 3....................................................................................................................... 23 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Extracting a Net Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Exploring the Circuit Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Examine the circuit parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Examine the IOCell models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Setting Up for Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Specifying Stimulus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Specifying Reection Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Simulation and Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Taking a closer look . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Finishing Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Contents Allegro PCB SI SigXplorer L Series Tutorial July 2006 4 Product Version 15.7 To Summarize What You Have Learned . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Lesson 4....................................................................................................................... 35 Revising the Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Moving the clock driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Swapping Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Simulation and Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Making Signal-to-Signal Comparisons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Finishing Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 To Summarize What You Have Learned . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Lesson 5....................................................................................................................... 43 Routing the Clock Driver Net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Exploring the Extracted Circuit Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Simulation and Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Finishing Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 To Summarize What You Have Learned . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Allegro PCB SI SigXplorer L Series Tutorial July 2006 5 Product Version 15.7 Lesson 1 Welcome This tutorial is designed to familiarize you with basic functions in Allegro PCB SI SigXplorer series L. It does not cover Channel Analysis or higher-level S-Parameter generation functions available in PCB SI XL and GXL.This tutorial assumes that you already know how to use SigXplorer. You begin this tutorial from an Allegro PCB Design Series L editor. Important This tutorial covers basic functionality in Allegro PCB SI SigXplorer series L(and in the Allegro PCB Design Series L). If you are running other versions of SigXplorer or Allegro PCB, information described here may not apply. The terms SigXplorer and PCB Design used in the tutorial refer to the products comprising the Allegro PCB SI SigXplorer L Series and the Allegro PCB Design L Series respectively. Instances in which functionality is exclusive to one product offering is specied. Objectives In this lesson, you learn: I what comprises the SigXplorer information set I the board database les that are used in this tutorial I how to start the tutorial from the PCB Design I how to change your view of the board in the PCB Design Allegro PCB SI SigXplorer L Series Tutorial Lesson 1 July 2006 6 Product Version 15.7 About Online Documentation The SigXplorer documentation set consists of online help and an online books. All documentation is accessible from the SigXplorer help menu. Refer to . . . for this level of information Getting Started with Allegro PCB SI SigXplorer L Series This book is for users who know how to use PCB Design but are new to the signal integrity eld. A basic introduction to the major features of SigXplorer including net extraction, reection simulation, and analysis. Allegro PCB SI SigXplorer L Series Tutorial (this book) This book complements Getting Started by guiding you through a series of exercises that lead to optimized placement based on signal exploration and analysis. Allegro PCB SI SigXplorer User Guide and Allegro PCB SI SigXplorer Command Reference Online documentation provides a more in-depth look at SigXplorer and signal integrity concepts. Allegro PCB SI SigXplorer L Series Tutorial Lesson 1 July 2006 7 Product Version 15.7 Working with Database Files The SigXplorer tutorial uses ve board database les for use in each successive lesson. The prerequisite section of each lesson informs you which board le to use. To start the tutorial, you should rst make a writable folder (a working directory) on your hard drive. You should copy the board (.brd) les, and the devices.dml le, from the product CD (or from your network) to this local, working directory on your hard drive. The board les for the tutorial are on the product CD at the following location in your installation heirarchy. <install_dir>\doc\assetut\goldenboards We suggest that you complete each lesson in sequence. In this way, the state of the board le at the end of one lesson can be used as the starting point for the next lesson. You can, though, take a lesson out of sequence by loading the appropriate board le for that lesson. See Board databases used in this tutorial on page 8. Important You can also complete this tutorial by copying and renaming tutboard1.brd to any le name that you like: perhaps myboard1.brd. As you progress through each lesson, you would then save the board in succession (myboard2.brd, . . .) and use it to start the next lesson. In this way, your results are based on the placement decisions that you make; therefore, they may differ slightly with those in the text. This approach also promotes a feeling of continuity in the tutorial. Allegro PCB SI SigXplorer L Series Tutorial Lesson 1 July 2006 8 Product Version 15.7 Board databases used in this tutorial Note: Although the design databases tutboard1.brd and tutboard2.brd are identical, as are tutboard3.brd and tutboard4.brd,weve supplied each to maintain continuity between the board number and the lesson number. Also, to end this tutorial, you can optionally save the clock net that you routed in Lesson 5, as myboard6.brd. In this way, you can archive the entire tutorial for later reference. Lesson/ Board File Design State Lesson 1 tutboard1.brd I Board database contains netlist I Board shows full ratsnest display Lesson 2 tutboard2.brd I Clock net (cclock) in the PCB Design is not extractable for topology exploration and analysis in SigXplorer. I Board shows full ratsnest display Lesson 3 tutboard3.brd I Board shows full ratsnest display off (blank); cclock visible I Clock net (cclock) is nowextractable for topology exploration and analysis Lesson 4 tutboard4.brd I Critical high-speed components are not optimally placed resulting in excessive length of the clock driver signal that feed these components I Lesson 5 tutboard5.brd I Clock driver, U9, is relocated to a central location among the components that it drives I The clock net, cclock, is reduced in length from swapping component U93 with U70 and U85 with U16 Allegro PCB SI SigXplorer L Series Tutorial Lesson 1 July 2006 9 Product Version 15.7 Starting the Tutorial Now that you have set up a working directory as described in Board databases used in this tutorial on page 8, youre ready to start the rst lesson. The rst lesson explains how to navigate within the PCB Design using zoom and pan commands. These principles hold true for moving around in SigXplorer and SigWave, which you are asked do in later lessons. To open the board database le 1. From the PCB Design, choose File > Open. If a design is already open, you will be prompted to save it before continuing. The Open dialog box appears. 2. Click the change directory check box to ensure that your design is saved to the working directory that you set up. 3. Double-click tutboard1.brd. The board database is loaded into PCB Design with all ratsnest displayed. Allegro PCB SI SigXplorer L Series Tutorial Lesson 1 July 2006 10 Product Version 15.7 Controlling your View of the design This section discusses zoom and pan commands. You use these commands to refocus your view of the board layout (in PCB Design), topology canvas or spreadsheet (in SigXplorer), or waveform display (in SigWave). These commands can be accessed from the View menu in PCB Design and SigXplorer, or fromthe Zoom menu in SigWave. You can also access each of these commands from icons in the tool bar This section is only for reference. You do not perform any exercises. There are many zoom commands; however, in this tutorial, well limit our discussion In, Out, Points, Fit, and Pan. This zoom command . . . Is used to . . . In Display an enlarged view of the board, topology, or waveform. Out Display an reduced view of the board, topology, or waveform. Points Display an area of the board, topology, or waveform by selecting a starting and ending point. Click to anchor the starting point, drag across the area, and click to dene the end point. The view now focuses around this area. Fit Display the entire board, topology, or waveform. Pan Roam the board or topology. To pan the board or topology, hold down the SHIFT key, click-right, and drag (Up, Down, Left, Right) Allegro PCB SI SigXplorer L Series Tutorial Lesson 1 July 2006 11 Product Version 15.7 The following depicts zoom commands available from PCB Design. The equivalent menu commands from SigXplorer and SigWave are also shown. PCB Design SigWave SigXplorer Fit In Out Points To pan the drawing, hold down the SHIFT key, click-right, and drag (Up, Down, Left, Right) Allegro PCB SI SigXplorer L Series Tutorial Lesson 1 July 2006 12 Product Version 15.7 Save the Design You have not modied the board in this lesson, but to maintain continuity between the board number and the lesson number, if you are using your own board les choose File > Save As and specify myboard2.brd (or whatever naming convention you chose). Congratulations! You have completed Lesson 1. To Summarize What You Have Learned In this lesson, you learned: I what is contained in the information set. I about the board database les and their design state. I how to use the zoom and pan commands. Allegro PCB SI SigXplorer L Series Tutorial July 2006 13 Product Version 15.7 Lesson 2 Objectives In this lesson, you: I highlight a net in PCB Design for extraction into SigXplorer. I become familiar with the Topology Template dialog box. I attempt to extract a net from PCB Design for topology exploration in SigXplorer. I prepare a net for extraction by running the Database Setup Advisor. Allegro PCB SI SigXplorer L Series Tutorial Lesson 2 July 2006 14 Product Version 15.7 Working with a Single Net High-speed considerations do not necessarily involve the entire design; rather, they may just involve the placement and routing, one-by-one, of only a few critical nets. In this tutorial, you will analyze the clock net cclock for optimum placement and routing. In this exercise, you will isolate the clock net so that it is easier to work with. You accomplish this in two steps. To begin this lesson, you should have tutboard2.brd open in PCB Design. To hide all ratsnest From PCB Design, choose Display Blank Rats All. The drawing appears to be far less cluttered. To display a single ratsnest 1. From PCB Design, choose Display Show Rats Net. Rats Visible Rats Hidden Allegro PCB SI SigXplorer L Series Tutorial Lesson 2 July 2006 15 Product Version 15.7 2. Click the Find (nd lter) tab in the Control Panel. The Nets checkbox is active. 3. Enter cclock in the Find By Name eld. 4. Press Return The ratsnest connections for cclock are now highlighted in your drawing. Notice the net connects connector J7, the clock driver U9, and the processor chipset. Enter cclock here The color of the highlighted ratsnest in the tutorial boards is white. For illustration, the ratsnest lines in the screens of this tutorial have been overdrawn by an illustration program, resulting in a thicker line than is displayed in PCB Design. Allegro PCB SI SigXplorer L Series Tutorial Lesson 2 July 2006 16 Product Version 15.7 Extracting a Net Topology In this exercise, you attempt to extract cclock into SigXplorer for exploration and analysis. The device denition for connector J7, which is connected to cclock, has an incorrect CLASS property, rendering cclock unextractable. You will run the Database Setup Advisor to identify and correct this problem. To extract a net topology 1. From PCB Design, choose Tools Topology Extract. The Topology Template dialog box appears. 2. Select the clock driver net, cclock, using one of the following methods: Scroll through the list of nets, locate cclock, then click on it. Replace the * in the the Xnet filter eld with the net name cclock, then press Tab, then click on the net name. Click on the net in the design. Allegro PCB SI SigXplorer L Series Tutorial Lesson 2 July 2006 17 Product Version 15.7 The net extraction begins. The following message appears. 3. Click Yes. The Database Setup Advisor is invoked. The Database Setup Advisor guides you through the following ve steps that prepare a net for extraction into SigXplorer. I Cross-section I DC Nets I Devices I SI Models I SI Audit Important Consult Getting Started with Allegro PCB SI SigXplorer L Series for information on using the Database Setup Advisor. The Database Set Up Advisor is invoked automatically when a non-extractable net is encountered. You can also invoke the advisor with the Tools Setup Advisor command from PCB Design. As mentioned earlier, the device denition for connector J7, which is connected to cclock, has an incorrect CLASS property, rendering cclock unextractable. Therefore, you need only work in the Devices section of the Database Setup Advisor. To correct a device PINUSE with the Database Setup Advisor From the previous exercise, you should have the advisor displayed. Allegro PCB SI SigXplorer L Series Tutorial Lesson 2 July 2006 18 Product Version 15.7 1. Click Next three times to advance to the Device Setup form in the advisor. 2. Click Device Setup. The Device Setup dialog box appears with a brief explanation of how to set up device parameters. 3. Click the Device Setup button. Click here Allegro PCB SI SigXplorer L Series Tutorial Lesson 2 July 2006 19 Product Version 15.7 The following dialog box appears. 4. Accept J* in the Connectors eld (the default). The devices PINUSE information derives from the devices CLASS denition. 5. Click OK. The Device Setup Changes report appears. Note that connector J7 was changed fromclass IC to IO. Because J9 shares the same device denition, it was changed as well. Other connectors in the design remain unchanged with class IO. Caution Had you explicitly specified J7 (instead of J*), J7 and J9 would change to class IO because they share the same part type; however, all other connectors would change to class IC because it is the default value. Allegro PCB SI SigXplorer L Series Tutorial Lesson 2 July 2006 20 Product Version 15.7 6. Dismiss the report. 7. Click Finish to accept the database modications and dismiss the advisor. With the correct CLASS properties (IO) on Connectors J7 and J9, the clock net is now prepared for extraction. You repeat the net extraction process in the next lesson. If you are using your own board les, in PCB Design, choose File Save As and specify myboard3.brd (or whatever naming convention you chose). Congratulations! You have completed Lesson 2. Allegro PCB SI SigXplorer L Series Tutorial Lesson 2 July 2006 21 Product Version 15.7 To Summarize What You Have Learned In this lesson, you have learned to I isolate a single net among a sea of nets I use the Topology Template dialog box I prepare a net for extraction by running the Database Setup Advisor Allegro PCB SI SigXplorer L Series Tutorial Lesson 2 July 2006 22 Product Version 15.7 Allegro PCB SI SigXplorer L Series Tutorial July 2006 23 Product Version 15.7 Lesson 3 Objectives In this lesson, you: I extract a net from PCB Design for topology exploration in SigXplorer I explore the extracted circuit topology in SigXplorer I set up reection measurements in SigXplorer I simulate a net topology in SigXplorer I analyze the resulting spreadsheet- and waveform-data in SigXplorer Allegro PCB SI SigXplorer L Series Tutorial Lesson 3 July 2006 24 Product Version 15.7 Extracting a Net Topology In this exercise, you will extract a net topology for clock signal cclock. You begin with tutboard3.brd loaded in PCB Design. To extract a net topology 1. From PCB Design, choose Tools Topology Extract. The Topology Template dialog box appears. 2. Using the net selection techniques that you learned in the previous lesson, extract the clock driver netcclock. Note: The extraction checkboxes will be discussed in Lesson 4. The net extraction begins. 3. When the Extracting Net conrmer disappears, click View in the Topology Template dialog box. When a product selection dialog box appears, select either Allegro PCB SI L or Allegro PCB SI Board option L from the list and click OK. SigXplorer launches. Allegro PCB SI SigXplorer L Series Tutorial Lesson 3 July 2006 25 Product Version 15.7 Exploring the Circuit Topology Upon initial invocation, the editor displays only the canvas. The spreadsheet is sized out of view. Resize the canvas so that it occupies about three-quarters of the SigXplorer window. To resize the canvas area and zoom level 1. Click the horizontal border separating the canvas and the spreadsheet, then drag the border vertically. 2. Click in the canvas and click the zoom t icon. The circuit topology expands to accommodate the resized canvas view. With the topology extracted from your design in PCB Design and visible in SigXplorer, you should make the following observations. You may have to zoom and pan as appropriate. Notice that: I The off-board connector (J7) along with a single driver (U9, Pin 9) and many receivers I Transmission lines with delays based on length (derived from Manhattan distance estimates) Zoom Fit icon Drag to vertically to resize Allegro PCB SI SigXplorer L Series Tutorial Lesson 3 July 2006 26 Product Version 15.7 I The driver and all receivers default to Tristate on initial extraction. I Default IOCell models were assigned to drivers and receivers based on PINUSE Important When you select a circuit component in the spreadsheet at the bottomof the editor, it will highlight in the topology canvas, at the top of the editor. Examine the circuit parameters Click Parameters and expand all circuit parameters by clicking the + signs until the spreadsheet shows all - signs, indicating the lowest level. Note the characteristic impedances for the transmission lines in the circuit. You can click in the attribute Name eld and change any of these values. The topology element in the canvas will be updated with the new value. Expand/ Collapse Tline Parameters Allegro PCB SI SigXplorer L Series Tutorial Lesson 3 July 2006 27 Product Version 15.7 Examine the IOCell models Examine the attribute and value (IOCell buffer model) eld of receiver U69. You can select a different IOCell buffer model based on your requirements. Dismiss the Set Buffer Parameter dialog box. Note: Consult the SigXplorer online help for a thorough discussion of signal integrity models. Fully expand eld to examine buffer model attribute Click here to invoke the Set Buffer Parameters window Allegro PCB SI SigXplorer L Series Tutorial Lesson 3 July 2006 28 Product Version 15.7 Setting Up for Simulation Before you can simulate and analyze this circuit topology, you must set up for simulation. This involves specifying: I Stimulus for the driver (U9, Pin 9) I Reection measurements Each is discussed in the sections that follow. Specifying Stimulus The receivers are preset to their default tri-state condition. You must set the driver to either a Pulse, Rise, or Fall state. You can simulate with only one active driver at a time, which is not an issue with the cclock net as it has only a single driver (U9, Pin 9). To set the driver stimulus state 1. Zoom in on the driver. Note the label on the symbol indicating it is tri-stated. 2. Click the TRISTATE label on U9. Click Zoom Points Drag over U9 Your view now focuses on U9 Click label to change stimulus state Allegro PCB SI SigXplorer L Series Tutorial Lesson 3 July 2006 29 Product Version 15.7 The Stimulus Editor appears. 3. Click Pulse. 4. Click OK. The stimulate state of the driver changes to Pulse. Specifying Reection Measurements 1. Resize the spreadsheet view to occupy about two-thirds of the editor. 2. Click the Measurements tab. 3. Click the reflection button to expand the measurements view. 4. Click the circle adjacent to the reection label, and then right-click and choose All Off from the pop-up window. Stimulus State has changed on symbol in canvas Allegro PCB SI SigXplorer L Series Tutorial Lesson 3 July 2006 30 Product Version 15.7 5. Click on individual measurements as follows: You are ready to simulate. Simulation and Analysis Now that you have specied a stimulus for the driver, have veried that all receivers are tri- stated, and have set up measurements to sample, you are now ready to simulate. To simulate the topology Choose Analyze Simulate. Click to expand view Click here then right- click and select All Off Click to select individual measurements Invoke simulator by menu- pick or by icon click Allegro PCB SI SigXplorer L Series Tutorial Lesson 3 July 2006 31 Product Version 15.7 A pop-up window displays as the simulation progresses. The Command window also becomes active in the spreadsheet so you can monitor the simulation. Once simulation is complete, the Results View appears showing the spreadsheet data. Important You can click on a column header followed by a right-click to invoke a pop-up menu fromwhich you can specify an ordering scheme for the spreadsheet data. The gure below shows an ascending ordering of data. Notice in the Overshoot Low column, many of the receivers approach negative 900 millivolts. Allegro PCB SI SigXplorer L Series Tutorial Lesson 3 July 2006 32 Product Version 15.7 Next, SigWave appears showing the output waveforms from the simulation. Observations include: (1) skew at the clock input to the receivers; (2), a fair amount of ringing; (3), a noticeable negative overshoot of 900 mV below ground; and (4), some non-monotonic activity. Taking a closer look In SigWave, you are going to take a closer look at the problem areas of the waveforms. To zoom in on the bottom of the waveform 1. Click in the SigWave window. 2. Choose Zoom In Region. 3. Drag over the bottom of the waveforms. SigWave focuses on the selected area. Negative overshoot Ringing Non-monotonic deviation Notice that there is approximately a - 900 mV overshoot below ground Zoom over the lower-part of the waveform display Allegro PCB SI SigXplorer L Series Tutorial Lesson 3 July 2006 33 Product Version 15.7 The input protection diodes in the receivers are designed to re at -700 millivolts. You are going to measure the duration that the waveforms dip below this threshold. To mark off time measurements 1. Drag the horizontal markerverticallyto this point (-700 mV). 2. Click the differential vertical marker icon in the toolbar and size each marker to correspond to the beginning and ending points where the waveforms extend below the - 700 mV threshold. This should measure approximately 3 nanoseconds in duration. This much negative overshoot lasting for this duration will soon damage the receivers. You will need to take corrective actions to optimize the placement. -700 mv Drag each vertical marker to mark off the portion of the waveform below -700 mv. This should measure approximately 3 nanoseconds Differential Vertical Marker Allegro PCB SI SigXplorer L Series Tutorial Lesson 3 July 2006 34 Product Version 15.7 Finishing Up In SigWave, save the waveform as preplaced. A .sim le extension is automatically added to the base le name. In the next lesson, you will use this for making comparisons. If you are using your own board les, in PCB Design, choose File Save As and specify myboard4.brd (or whatever naming convention you chose). Congratulations! You have completed Lesson 3. To Summarize What You Have Learned In this lesson, you learned to: I extract a circuit topology I explore the circuit topology I set up simulation parameters (stimulus and measurements) I simulate and analyze a circuit topology Allegro PCB SI SigXplorer L Series Tutorial July 2006 35 Product Version 15.7 Lesson 4 Objectives In this lesson, you: I move the clock driver chip in PCBDesign to a location that is central to other components on the clock circuit I swap components in PCB Design to reduce the length of the clock circuit I simulate this revised circuit topology in Allegro PCB SigXplorer I analyze the resulting spreadsheet- and waveform-data in Allegro PCB SigXplorer Allegro PCB SI SigXplorer L Series Tutorial Lesson 4 July 2006 36 Product Version 15.7 Revising the Board Layout In Lesson 3, you extracted the clock circuit from PCB Design based on its initial placement. You performed a reection simulation in SigXplorer and analyzed results that were unacceptable. In this lesson, you modify the placement of the clock circuit and repeat the analysis process. To begin this lesson, you should have tutboard4.brd open in PCB Design. Moving the clock driver The clock driver (U9) is located in the lower-left quadrant of the board, which is some distance from many of the chips (receivers) that it controls. To minimize delays at the receivers, it is best to centralize the placement of this driver. To move the clock chip 1. From PCB Design, choose Edit Move. 2. Drag the cursor (crosshair) across U9 and select it to move. 3. Move U9 by dragging to the location shown below. The ratsnest connections follow the movement of the chip. 4. Click to anchor the placement. 5. Right-click and choose Done from the pop-up menu. Before Move After Move Allegro PCB SI SigXplorer L Series Tutorial Lesson 4 July 2006 37 Product Version 15.7 Swapping Components Although the clock driver is now closer to the receivers, you can shorten the length of the clock net even more by swapping some of the receivers, with chips of the same type, that are even closer to the driver. In this exercise, you will swap U93 with U70, and U85 with U16. To swap components 1. From PCB Design, choose View Zoom by Points. 2. Drag across the lower-right quadrant of the board. The view now focuses on the chips that you will swap. 3. Choose Place Swap Components. Click U93 (the source component), then click U70 (the target component) The components exchange places on the board. Click U85 (the source component), then click U16 (the target component) The components exchange places on the board. Right-click and choose Done from the pop-up menu. This ends the swap component mode. Graphic depicts layout before swapping Allegro PCB SI SigXplorer L Series Tutorial Lesson 4 July 2006 38 Product Version 15.7 Simulation and Analysis Now that you modied the placement in your design by moving the clock chip and some of the receivers, resimulate the clock net to see if you have reduced the noise margin. In Lesson 3, you learned how to do the following. I extract a Net Topology I examine Circuit Parameters I specify Stimulus (Pulse) I specify Measurements I simulate Put these skills to work and simulate the revised circuit topology. The measurements that you previously specied are still in effect. You do not have to reselect them. If SigXplorer is still open, conrm that you want to overwrite the old topology. Allegro PCB SI SigXplorer L Series Tutorial Lesson 4 July 2006 39 Product Version 15.7 Making Signal-to-Signal Comparisons To go a step further, you superimpose the pre-placed waveform (preplace.sim) that you saved in the previous lesson onto the placed waveform which currently displays in SigWave. You then examine pre- and post-placement waveforms with all signals displayed, followed by a signal-to-signal comparison. To superimpose simulation waveforms 1. From SigWave, choose File Import SigWave.sim le. The File Open dialog box appears. 2. Double click preplaced.sim. The pre-placed waveform (preplaced.sim) is superimposed over the placed waveform which remains in memory. 3. Expand the signals (as shown) in the waveform libraries folder by clicking the + signs. 4. Size the SigWave window (as shown) so that you can view the signal names. You should observe that all signals from both waveforms display with minimal deviation. Expand waveforms Resize window Allegro PCB SI SigXplorer L Series Tutorial Lesson 4 July 2006 40 Product Version 15.7 To examine both waveforms (signal-by-signal) 1. Click on each waveform sub-folder in the waveform library folder, then right-click and choose hide all subitems from the pop-up menu. Each signal in SigWave is nowidentied with a slashed-circle in the left pane; waveforms are suppressed in the right pane. Important When manipulating a signal in the left pane of SigWave, you may have to click in the right pane to refresh the waveform display. 2. One at a time, compare each pin of the pre-placed waveformwith the corresponding pin of the placed waveform by selecting the net, and then right-click and choose Display from the pop-up menu. All Signals On All Signals Off Comparing U9, Pin 9 of pre-placed waveformagainst U9, Pin 9 of placed waveform. Click on signal, then right-click and choose Display. Allegro PCB SI SigXplorer L Series Tutorial Lesson 4 July 2006 41 Product Version 15.7 You should observe results similar to the following. Note: The composite drawing below captures the resulting waveform and spreadsheet data from pre-placed and placed simulations. You should observe a marked improvement in the waveforms and in the numbers. The negative overshoot is approximately -150 mV. Well within the -700 mV margin where the input protection diodes turn on. There is also far less ringing and skew among the receivers. Finishing Up From SigWave, choose File Save and enter placed. In the next lesson, you compare this pre-route waveform (placed.sim) against the post-route waveform. If you are using your own board les, in PCB Design, choose File Save As and specify myboard5.brd (or whatever naming convention you chose). Congratulations! You have completed Lesson 4. Waveform analysis after initial placement. Waveform analysis after moving clock driver and swapping components to minimize length of clock signal. Spreadsheet comparison of results from the initial placement (left) to the revised placement (right). Allegro PCB SI SigXplorer L Series Tutorial Lesson 4 July 2006 42 Product Version 15.7 To Summarize What You Have Learned In this lesson, you have learned to: I modify placement by moving and swapping components I compare current simulation waveforms (based on revised placement) against previously saved waveforms (based on initial placement) Allegro PCB SI SigXplorer L Series Tutorial July 2006 43 Product Version 15.7 Lesson 5 Objectives In this lesson, you: I route the clock net I simulate the clock net using actual trace models instead of Manhattan distance estimates I compare simulation waveforms (routed) against previously saved waveforms (unrouted) Allegro PCB SI SigXplorer L Series Tutorial Lesson 5 July 2006 44 Product Version 15.7 Routing the Clock Driver Net In Lesson 4, you extracted the clock circuit fromPCB Design based on the revised placement. You performed a reection simulation in SigXplorer and analyzed the results that are now acceptable. In this lesson, you route the clock net and repeat the simulation and analysis process to verify that you still meet the noise budget. To begin this lesson, you should have tutboard5.brd open in PCB Design. To route the clock net 1. From PCB Design, choose Route Route Net(s) By Pick. 2. Click on the visible ratsnest cclock. The PCB Router routes your board in the background. For illustration, the routed trace lines in the screens of this tutorial have been overdrawn by an illustration program, resulting in a thicker trace width than is displayed in PCB Design. Allegro PCB SI SigXplorer L Series Tutorial Lesson 5 July 2006 45 Product Version 15.7 Exploring the Extracted Circuit Topology Using the skills that you learned in previous lessons, do the following. I Resize the canvas and the spreadsheet equally. I Zoom in on transmission line symbol TL1. I Click the parameters tab in the spreadsheet and expand the parameter view to examine the attribute values of TL1. The extracted interconnect model describes the connection relative to the reference planes. Transmission line symbol: canvas view Transmission line symbol: spreadsheet view Allegro PCB SI SigXplorer L Series Tutorial Lesson 5 July 2006 46 Product Version 15.7 Simulation and Analysis Now that you have routed the clock net in your design, you resimulate to verify that you have maintained the revised placement noise margin. In previous lessons, you learned how to do the following: I Specify Stimulus I Specify Measurements I Simulate I Compare resulting simulation waveforms Put these skills to work and simulate the routed circuit topology. Caution The pre-routed topology that you extracted in the previous lesson was based on a virtual representation. The routed topology that you are about to extract is based on a physical layout with layer and via information; therefore, before you simulate from SigXplorer, you must choose Analyze Reset Sim Data to reload the interconnect library that contains the electrical model for the extracted via. If SigXplorer is still open, conrm that you want to overwrite the old topology. You should observe results similar to the following. Allegro PCB SI SigXplorer L Series Tutorial Lesson 5 July 2006 47 Product Version 15.7 Note: The composite drawing below captures the resulting waveform and spreadsheet data from pre-route and post-route simulations. Notice that the post-route waveforms are even more ideal than the waveforms from the modied placement. There is less skew among the receivers, the negative overshoot was reduced from -148.9 mV to -95.5 mV. Finishing Up If you are using your own board les, in PCB Design, choose File Save As and specify myboard6.brd (or whatever naming convention you chose). Congratulations! You have completed Lesson 5 and the tutorial. Waveform analysis after moving clock driver and swapping components to minimize the length of the clock signal. Waveform analysis verified after extracting routed clock signal. Allegro PCB SI SigXplorer L Series Tutorial Lesson 5 July 2006 48 Product Version 15.7 To Summarize What You Have Learned In this lesson, you learned to: I extract a net topology from PCB Design into SigXplorer I compare current simulation waveforms against previously generated waveforms (based on revised placement) In this tutorial, you learned to: I prepare a net for extraction from PCB Design into SigXplorer I Extract a net based on the initial placement in PCBDesign, simulate the net in SigXplorer , and examine the resulting data in the results view of the spreadsheet as well as the resulting waveforms in SigWave I Modify the placement in PCB Design, resimulate and analyze the waveforms, and observe more ideal (less ringing among the receivers, less skew, and less negative overshoot) waveforms I Route the net, resimulate and analyze to verify that the net remains within the noise budget