Questa ADMS Quick Guide

Installation/Environment/Licensing
Documentation
mgcdocs Opens the Analog/Mixed-Signal Infohub
Environment Variables
LM_LICENSE_FILE Pathname of AMS license
Setup AMS License
Copy AMS.license to /<install_dir>/$MGC_AMS_HOME/$AMS_VCO
Setup the variable LM_LICENSE_FILE to point to the license file
Key Commands
Shell/GUI Commands
vlib Creates a design library
varefresh Updates a design library for use in this release
vmap Defines or displays library mapping
vdir Lists the contents of a design library
vdel Deletes a design library
vacom Compiles VHDL-AMS sources
valog Compiles Verilog-AMS sources
vaspi Compiles a SPICE subcircuit to the working library
vasim Invokes the Questa ADMS simulator
GUI Commands
add log Logs the data for analysis
add log -delta Simulator solves analog data when it has changed
more than the delta value
add wave Adds the net to the Wave window
add wave -delta Simulator solves analog data when it has changed
more than the delta value
add list Adds the net to the List window
batch_mode Used as a condition in an if statement
bp Sets a file-line breakpoint or returns a list of currently
set breakpoints
change Modifies the value of the VHDL-AMS constant or
variable
checkpoint Saves the state of the simulation in a checkpoint file
drivers Displays the value of the digital drivers linked with
the digital net
examine Displays the value of a VHDL-AMS/Verilog-AMS
item in the transcript window
find nets Displays the full pathnames of analog and digital
objects including signals, quantities and terminals
force Forces interactive stimulus on a net
log An alternative to add log
ms Prefixes a list of QuestaSim commands
noforce Removes the effect of a force on a net
quit Quits Questa ADMS
restart Restarts the simulator
restore Restores the simulation using a checkpoint file
run Runs a simulation
stat dump Creates a statistics file during the simulation
stat enable Starts collection of statistics
stop Stops a log or wave from being produced
view Opens a Questa ADMS or QuestaSim window
watch Adds a watch point to the specified signal
wave show Allows you to set up default representations when
waving terminals
Key Simulation Control Commands
Commands used in .cmd files
.ac AC analysis; start and stop frequencies can be set
.alter Re-run simulation with a modified netlist
.analog_start Delays the analog solver computations
.dc DC analysis
.data Parameter sweep
.defmac Macro definition with written arguments
.defwave Waveform definition
.extract Extract waveform characteristics
.four FFT select waveform
.ic Initial transient analysis conditions
.include Include a filename in an input netlist
.modsst Eldo RF Modulated Steady-State analysis
.mprun Multi-processor simulation
.nodeset DC analysis conditions
.noise Noise Analysis
.noisetran Transient Noise Analysis
.op DC Operating Point calculation
.option Simulator conguration
.param Global parameter declarations
.plot Plot simulation results
.print Printing of results
.probe Writes values across the nodes to a binary output
file
.restart Restarts a simulation using the file created with
.save
.save Writes data to a file at specific times during the
simulation
.setbus Creates a bus
.sigbus Sets signal on a bus
.sst Eldo RF Steady-State analysis
.step Parameter sweep
.temp Set circuit temperature
.tran Activates transient analysis
.use Use previously simulated results
Key Command Arguments
vacom
[-analogdebug] Checks for mathematical out-of-range errors
[-work <library>] Specifies the library into which the DU is compiled
[-nocheck] Disables run time range checking
[-nodebug] Compiles without generating debug information
[-noexplim] Compiles without truncating exponential
[-constants] Compiles without optimizing constants
[-gccopt] Enables maximum optimization performed by gcc
[-f[orce]] Disables warnings when overwriting a design unit
[fi|-file <option_file>]
Specifies a file containing additional arguments.
[-ams] Provides a digital interface for a VHDL-AMS entity.
Used with the following interface definition options:
[-target_entity] Replaces a Questa ADMS entity with a
QuestaSim entity
[-target_type <full_type_name>]
Replaces terminal/quantity with a signal of type
full_type_name
[-target_mode <mode_name>]
Replaces terminal/quantity with a signal of
mode mode_name
[-output_path <path_name>]
Generates a VHDL-AMS entity
[-steppredict] and [-nosteppredict]
Enables/disables prediction of analog time-step
for optimized quantities of VHDL-AMS models
valog
[-work <library>] Specifies the library into which the DU is compiled
+define+<macro_name>[=<macro_text>]
Compiles a Verilog-AMS module
+incdir +<directory>]
Compiles a Verilog-AMS module
[-analog] Compiles pure analog modules
[-lrm10 | -1.0] Backward compatibility with Verilog-A LRM 1.0
[-syntax_only] Only checks the syntax
[-digital [<ms_options>]]
Only compiles in QuestaSim
[-nocheck] Disables mathematical checks when computing
expressions such as / and log
[-nooptbr <model_name:branch_name>]
Disables optimizations on the named branch
[-gccopt] Enables maximum optimization performed by gcc
[-target_type wire | real]
Defines the digital net that corresponds to all the
data ports of a Verilog-AMS unit
[-target_entity <unit_name>]
Provides a digital unit representing the Verilog-AMS
unit
[-fi|-file <option_file>]
Specifies a file containing additional arguments.
[-sv] Enables SystemVerilog keywords
vasim
[-c] Run in command line mode
[-lib <path>] Specifies the name of the work library
[-cmd <file>] Specifies the name of the command file for top
VHDL-AMS, or Eldo SPICE file for top Eldo SPICE
[-do <file>] Name of the startup file
[-nature <whole_nature_name>]
Nature of the Eldo nodes
[-eldoopt] Allows Eldo options to be specified
[-aditopt] Allows ADiT options to be specified
[-g<Name>=<Value> ... ]
Overrides mixed-signal (VHDL-AMS, Verilog-AMS)
parameters or SPICE subcircuit parameters
[-G<Name>=<Value> ... ]
Same as -g except that it will also override generics/
parameters that received explicit values in generic
maps, instantiations, or via defparam statements
[-cou] Generates .cou and .dou output files
[-linkx] Allow X values for Std_Logic Eldo converters at DC
[-iteration_limit <nb>]
Maximum number of simulation iterations
[-l <file_name>] Saves the contents of the Trasncript window to
file_name
[-L <lib_name>] Specifies the library to search for design units
instantiated from Verilog, Verilog-AMS, and VHDL,
and VHDL-AMS default component binding
[-queue] Adds license request in queue
[-sharedlib <lib_path>]
Sets the default path for Eldo dynamic libraries
[-stver] Enables the use of STMicroelectronics models
[-extended] Enables extended identifiers to be used with Eldo
inside Questa ADMS
[-noextended] Prevents extended identifiers to be used with Eldo
inside Questa ADMS
[-nodisplay] Requests not to load Tk in batch mode
[-vcdread <file>] Simulates using the specified four-state VCD file
[-vcdstim <file>] Simulates using the specified VCD file
[-isaving] and [-noisaving]
Enables/disables incremental saving mode
[-outpath <path>] Writes the output files to path
[-verbosedisplay] Displays instance name with message when file
display functions are used
[-jwdb_norffolder] Puts RF analysis results into a folder called AC or
TRAN, accessed from the EZwave window
[-stat] Writes design, elaboration, and simulation
information to a statistics file (.stat)
[-statfile <file_name>]
Writes design, elaboration, and simulation
information to a statistics file called <file_name>.stat
[-debuginfo] Writes design, elaboration, and simulation
information to a debuginfo file (.dbg)
[-struct <level>] Writes the design hierarchy to the statistics (.stat) file
[-outname [[<path>]basename]]
Specifies the base name of the simulation waveform
output files (.swd, .ez.do, .wdb...)
[-t [<multiplier>}<time_unit>]
Specifies the simulator time resolution
[-coverage] Enables code coverage statistics collection
[-viewcov [<dataset_name>=]<UCDB_filename>]
Invokes coverage view mode to display UCDB data
[-a2dopt] Enables A2D converter optimization
[-nod2aopt] Disables D2A converter optimization
[-title <main_window_title>]
Optional title for the Main GUI window
[-nodisccompchk]
Disables Verilog-AMS compatibility checks
[-jwdb_checkpoint [enable | disable | warnings_only | errors_only]]
Specifies the behavior of the tool in case of memory
shortage
[-wreal_resolution <resolver>]
Indicates which resolution function to use for wreal
when multiple drivers are connected to the same net
[-cvupf [strict | relaxed]]
Specifies the mode that determines whether power
is expected to come from the digital or analog side
when using the auto calibrate converter
[-steppredict] and [-nosteppredict]
Enables/disables prediction of analog time-step for
optimized quantities of VHDL-AMS models
[[-premier | -adit]] Selects the simulation kernel for either Questa
ADMS Premier, or ADiT
[<library>.design_unit]
Name of the library
<design_unit> Name of the design unit
[-ms {ms_option}] Passes ms_option to QuestaSim
varefresh
[library_name] Name of the library to update for use in this release
vaspi
[-f] Overwrites existing units of the same name
[-arch] A SPICE subcircuit is registered in the library as a
VHDL-AMS architecture
[-noarch] A SPICE subcircuit is registered in the library as a
SPICE SUBCKT primary design unit
[-srclib <src_lib>] Logical library containing the compiled design unit
[-work <worklib>] Specifies the work library
[-interface <file>] Specifies the association file name
[-by_name] Generates an association mapping table using
default pin/port names
[-by_position] Generates an association mapping table using
default pin/port positions
[-interactive] Invokes the Interface Matcher
<digital_unit> Digital unit name
<subckt_name> SPICE subcircuit name
[@<file_name>] Name of the SPICE file that contains the subcircuit
.BIND
.BIND instance_part | from_part to_part [ assoc_part ]
.BIND instance_part from_part to_part [ assoc_part ]
Replaces an instance or subckt/model with another subckt/model:
instance_part ::=
inst '=' inst_name
from_part ::=
from_subckt '=' Eldo_subckt_name
| from_model '=' HDL_model_name
to_part ::=
to_subckt '=' new_Eldo_subckt_name
| to_model '=' new_HDL_model_name
assoc_part ::=
mapping '=' assoc_file_name
Boundary Elements
.model model_name a2d|d2a mode= type parameters
Specifies a built-in SPICE boundary element
.model boundary_model hook design_entity
Specifies a user-defined boundary element
.defhook model_name {model_name}
Boundary elements are inserted where applicable
Instantiation
Instantiating Behavioral Models from Eldo
Behavioral models are declared with the .model command:
.MODEL eldo_model_name macro lang=language
+ [ lib=logical_lib_name ] [ mod=behavioral_model_name ]
+ [ generic|param ':' generic_name=value {generic_name=value}]
Behavioral models are instantiated from Eldo in the following way:
Y<instance_name> behavioral_model_name
+ GENERIC: param=value {param=value}
+ PORT: actual_port_name {actual_port_name}
Instantiating VHDL-AMS from Verilog-AMS
[mylib.]entityname[(arch)] instancename (port1, port2);
Instantiating Eldo from Verilog-AMS
modelname instancename (port1, port2, ...);
subcktname instancename (port1, port2, ...);
primitive #(parameter) instancename (port1, port2, ...);
Instantiating Eldo from VHDL(-AMS) or
Verilog(-AMS)
vaspi <target_entity> <subckt_name>@<subckt_file_name>
Files
modelsim.ini System initialization file
.modelsim GUI preferences file
<CmdFileName>.conv
Boundary Elements log file
transcript Default file name that part of the Transcript window
activity is saved to
<CmdFileName>.errm.log
Default file name that all information written to the
Transcript window is saved to
.cmd File containing simulation control commands
.do File containing simulator commands
.stat Statistics output file
Standards Supported
VHDL IEEE 1076-1993
IEEE 1076-2002
IEEE 1076.1-1999 (VHDL-AMS)
VITAL 2.2b,
VITAL95 - IEEE 1076.4-1995
VITAL 2000 - IEEE 1076.4-2000
Timing SDF 1.0 to 4.0
Verilog IEEE Std 1364-1995
IEEE Std 1364-2005
Verilog-AMS v2.2
Compilation Table for the Child Design Unit
Parent
VHDL
System Verilog
Verilog
VHDL-AMS Verilog-AMS
SPICE
C
h
i
l
d
VHDL vcom vcom vcom
System Verilog vlog -sv vlog -sv vlog -sv
Verilog vlog vlog vlog
VHDL-AMS vacom -ams vacom vacom
Verilog-AMS valog valog valog
SPICE vaspi vaspi direct or vaspi
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