ECE 612

Design of Digital Integrated Circuits

Spring 2014

Lecture 2
CMOS Inverter

S. A. Ibrahim
Ain Shams University
ICL


Outline
The CMOS Inverter Noise Margin and Threshold
Voltage
The CMOS Inverter Propagation Delay and Switching
Speed
The CMOS Inverter Power Consumption
Sizing of the CMOS Inverter
FinFET Inverter
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Transfer Function
Switching waveforms
The Ideal Inverter
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Gain = 0
Gain = 0
Gain =

Noise in Digital Circuits
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Inductive Coupling Capacitive Coupling
Power and Ground
Noise

NM
L
NM
H
V
M
= gate threshold voltage (mid-swing)
Noise margins = NM
L
and NM
H
The Real Inverter Transfer Function
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V
OH
V
IH
V
IL
V
OL
V
OH

t
PLH
, t
PHL
, t
P
, t
r
, t
f
Propagation time (or propagation delay time or simply delay time):
t
P
= (t
PLH
+ t
PHL
)/2
VSS = 0 V =
VDD =
VSS = 0 V =
VDD =
The Real Inverter Switching Waveforms
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The CMOS Inverter
Polysilicon
In
Out
V
DD
GND
PMOS
2
Metal 1
NMOS
Out In
V
DD
PMOS
NMOS
Contacts
N Well
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Notice:
Transistor threshold = V
tn
or V
tp

Inverter threshold = V
M

Normally V
M
= V
DD
/2 for symmetric NMs

ON OFF
LIN SAT
SAT SAT
SAT LIN
OFF ON
CMOS Inverter Static Operation
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MOSFET Equations
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Long channel or small V
DD
Short channel and normal V
DD

Inverter Threshold V
M
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If V
DD
>>V
DSAT
and V
T
p n
tn p n tp DD
M
k k
V k k V V
V
/ 1
/
+
+
= For non-velocity-saturated devices


Inverter Threshold Variation
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MOSFET Switch Model
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How is a MOS transistor different from an ideal switch ?

Non-zero switch ON resistance

Parasitic capacitances
S D
C
G

G
C
S

S D
G
C
D

Ideal switch One possible model of the
MOS transistor as a switch
R
ON

MOS ON Resistance
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S
D
G
The switch ON resistance R
ON
0
R
ON
is a non-linear resistor
it changes with V
DS

region of MOS operation matters
Suppose switch turns ON suddenly
i.e. V
GS
jumps from 0 to V
DD

R
ON
varies (as slope
1
of the red curve)

A simple estimate of average R
ON
R
ON
slope
1
of blue line
V
o
=2.5
0 0 . 5 1 1 . 5 2 2 . 5
0
1 0 0
2 0 0
3 0 0
4 0 0
5 0 0
6 0 0
I
ds
(A)
V
ds

The R

of a MOSFET is inversely
proportional to the gate overdrive, V
GS
-V
T


R
ON
During Transition
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MOS Capacitance
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Parasitic (undesirable) elements are everywhere
Devices are small enough such that inductive effects are negligible.
Capacitances dominate; and there are MANY
1. C
channel
since channel connects S/D, it is split
2. C
overlap
gate overlaps S/D, and there is fringe cap from Gate
3. C
junction
S/D form reverse-biased PN junctions with the body
4. C
j_sidewall
S/D different doping to the bottom and side
5. C
body
from channel to body, quite small b/c of small L
Gate
Source Drain
C
1
C
2
C
2
C
3
C
4
C
5
C
3
C
4

Gate Capacitance
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Channel cap characteristics
Split between S/D
Varies with region of operation


Off MOSFET
C
ch
= C
GB



On MOSFET
C
ch
= W*L
ch
*c
ox
/t
ox
Triode region
C
1A
= C
1B
= C
ch
/2
Saturated region
C
1A
= 2/3C
ch
, C
1B
= 0
C
ov
= C
ox
*W*L
ov
*k, where k is a
constant accounting for fringing
Removing technology dependence
and assuming minimum channel
length
C
gate
= C
G
* W
Gate
Source Drain
C
1A
C
1B

Self-Loading Capacitance
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A transistor pulls current from its S/D,
so the S/D junction is often called the
Self-Loading Capacitance.
C
S/D
= C
j_area
+ C
j_sidewall
C
j_area
= W*L
diff
*C
J
(V
S/D
)
C
j_sidewall
= (W+2L
diff
)*C
JSW
(V
S/D
)
Note that C
J
and C
JSW
are

layout dependent
voltage dependent
L
diff
is typically 5 (unshared and
contacted)
L
diff
W

M
O RB O J
V V C C ) / 1 /( + =
Where C
O
, V
O
, and M are
junction dependent constants
Can also be simplified as
C
junction
= C
D,S
* W

CMOS Inverter: Transient Response
t
pHL
= f(R
on
.C
L
)
= 0.69 R
on
C
L
V
out
R
p
V
DD
(a) Low-to-high (b) High-to-low
V
out
R
n
V
DD
C
L
C
L
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V
DD
V
out
V
in
= V
DD
R
on
C
L
t
pHL
= f(R
on
.C
L
)
= 0.69 R
on
C
L
t
V
out
V
DD
R
on
C
L
1
0.5
ln(0.5)
0.36

0 0.5 1 1.5 2 2.5
x 10
-10
-0.5
0
0.5
1
1.5
2
2.5
3
t (sec)
V
o
u
t
(
V
)
CMOS Inverter: Propagation Delay
t
p
= 0.69 C
L
(R
n
+R
p
)/2
t
pHL

t
pLH

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3
4

(neglecting
Channel length mod.)

Choosing W
p
/W
n
Ratio
For symmetric inverter V
M
= V
DD
/2 and t
PHL
= t
PLH
,
=W
p
/W
n
=
n
/
p
=R
eqp
/R
eqn
=r.
However, this does not guarantee minimum delay.
t
PLH
decreases with whereas t
PHL
increases with .

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20

Power Consumption
Static (leakage) (low for low transistor count and perfected technology)
Dynamic (to charge and discharge C
L
at a certain frequency: appreciable)
Short-Circuit (when both PMOS and NMOS are ON: reduced in fast transitions)

circuit short dynamic static total
P P P P

+ + =
may be the most important
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Static Power
leakage DD static
I V P =
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Leakage power increases exponentially with temperature.
Leakage power affects stand-by time heavily.

Techniques to Reduce Static Power
Using transistors with higher
threshold voltages (HVT). Difficult
at low supplies.
Using technologies that contain
devices with sharper turn-off
characteristic for example SOI.
Using body biasing to increase
threshold voltage when off
(dynamic biasing used especially
in memories).
Increasing length and/or stacking
devices.
Power gating of different blocks
when not used (supply off or
reduced).
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>0

Dynamic Power
* An equal energy is needed to discharge C
L
(in the next half cycle)
* Therefore in one switching cycle we need an energy of C
L
V
DD
2
activity DD L
DD L
dynamic
f V C
T
V C
P
2
2
= =
During
output
transition
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24

Techniques to Reduce Dynamic Power
Reducing the supply reduces
power substantially (quadratic) as
long as we can keep f
clk
(V
DD
>2V
T
).
Reducing the activity factor by
revisiting the Boolean functions on
top level. Reduce Glitches too.
Reducing capacitance by reducing
sizes of transistors and
interconnects whenever possible.
Dynamic voltage scaling (DVS).
Clock gating.
Parallel hardware may be used to
reduce global interconnect and
allow a reduction in supply voltage
without degrading system
throughput.
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25
[Burd, JSSC00]

Short-Circuit Power
This average short-circuit current drawn from V
DD
results in P
short-circuit

Fast rise and fall times of input waveform reduce short-circuit power
During
input
transition
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26
activity DD SC DD peak SC SC
f V C fV I t P
2
= =

Techniques to Reduce Short Circuit Power
Short-circuit current is reduced when we lower the
supply voltage. In the extreme case, when VDD < V
Tn
+
|V
Tp
|, short-circuit dissipation is completely eliminated.
With threshold voltages scaling at a slower rate than
the supply voltage, short-circuit power dissipation is
becoming of a lesser importance in deep-submicron
technologies.
Short-circuit power is consumed by each transition
(increases with input transition time). Reduction
requires that gate output transition should not be faster
than the input transition (faster gates can consume
more short-circuit power). Increasing the output load
capacitance reduces short-circuit power.
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27

Power-Delay & Energy-Delay Product
Used as quality measure of logic gates.

PDP is energy, so not so useful.

Assuming that NMOS and PMOS
transistors have comparable threshold
and saturation voltages,
where


This equation is only accurate as long as
the devices remain in velocity saturation,
which is probably not the case for the
lower supply voltages.
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Outline
The CMOS Inverter Noise Margin and Threshold
Voltage
The CMOS Inverter Propagation Delay and Switching
Speed
The CMOS Inverter Power Consumption
Sizing of the CMOS Inverter
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29

Inverter with Load
Load (C
L
)
Delay
Assumptions: no load -> zero delay
C
L
t
p
= k R
eq
C
L
R
eq
k is a constant, equal to 0.69 (note ln (2) =0.69)
R
eq
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Layout-Aware Inverter with Load
C
int
C
L
Delay = kR
eq
(C
int
+ C
L
) = kR
eq
C
int
+ kR
eq
C
L
= kR
eq
C
int
(1+ C
L
/C
int
)

= Delay (Internal) + Delay (Load)
2W
W
Intrinsic or internal or self-loading cap
External loading cap
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Load
Delay
kR
EQ
C
int

Load
Delay = t
p

C
int
C
L
Delay = t
p
= kR
eq
C
int
(1+ C
L
/C
int
) = t
po
(1+ C
L
/C
gin
)
C
gn
C
gp
= 2C
cgn
2W
W
t
po

C
L

C
g
C
int
~ C
g
= C
g
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C
g
vs. C
int

C
int
= C
g
( for simplicity one assumes ~ 1, it is indeed close
to 1 for most submicron processes)

f = C
L
/C
g
= effective fanout (also called electrical effort)

t
po
= 0.69R
eq
C
int
(zero-load delay or intrinsic delay)

Delay = t
p
= kR
eq
C
int
(1+ C
L
/C
int
) = t
po
(1+ C
L
/C
g
)

= t
po
(1+ f /)
Relative (Normalized) Delay d = t
p
/t
po
= (1+ f /)
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Delay Formula

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Delay = t
p
= kR
eq
C
int
(1+ C
L
/C
int
) = t
po
(1+ C
L
/SC
g
)
t
po
= k(R
eq
/S) (SC
int
) = f(S) = kR
eq
C
int
Scaling W by a factor S: R
eq
R
eq
/S and C
int
SC
int
SC
int
R
eq
/S
R
eq
/S
Size of a Single Inverter for a Given C
L
(1)

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35
Size of a Single Inverter for a Given C
L
(2)
large area and
wasted effort
SC
int
>>C
L

Sizing an Inverter Chain
C
L
In Out
1 2 N
t
p
= t
p1
+ t
p2
+ + t
pN
|
|
.
|

\
|
+ =
+
j g
j g
po pj
C
C
t t
,
1 ,
1

L N g
N
i
j g
j g
p
N
j
j p p
C C
C
C
t t t =
|
|
.
|

\
|
+ = =
+
=
+
=
1 ,
1
,
1 ,
0
1
,
, 1

Load cap
as if a gate N+1 exists
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The Tapered Buffer

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37
C
int
fC
int
f
2
C
int
f
N-1
C
int

Optimum Delay and Number of Stages
1
/
g L
N
C C F f = =
When each stage is sized by f and has same eff. fanout f:
N
F f =
( ) / 1
0
N
p p
F Nt t + =
Path (N-stages) delay
Effective fanout of each stage:
f
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Optimum Number of Stages
For a given load, C
L
and given input capacitance C
in

Find optimal sizing f
( )
|
|
.
|

\
|
+ = + =
f f
f
F t
F Nt t
p
N
p p
ln ln
ln
1 /
0
/ 1
0

0
ln
1 ln
ln
2
0
=

=
c
c
f
f f
F t
f
t
p p

f
F
N C f C F C
g
N
g L
ln
ln
with
1 1
= = =
( ) f f + = 1 exp For = 0, f = e, N = ln F Special case: no self loading:
Exponential Buffer
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Optimum vs. in Tapered Buffers
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Exponential buff
(no self-loading)
tapered buff
(self-loading at = 1)
C
int
= C
g
3.6 (~ 4)

Buffer Design
1
1
1
1
8
64
64
64
64
4
2.8
8
16
22.6
N f t
p


1 64 65


2 8 18



3 4 15



4 2.8 15.3
( exponential)
(Typical instead of 3.6)
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FO4 Delay
Want a way to characterize the delay of a circuit
(roughly) independent of technology
Most common metric:
Delay of an inverter driving four copies of itself (t
FO4
)
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UTB=ultra-thin body

FinFET Key Benefits
L
g
Scaling: Supports smaller L
eff
at same I
off
Faster
V
g
-V
t
Scaling: Supports smaller V
t
at at same I
off
lower supply
Lower power
Smaller I
off
lower sub-threshold leakage

A versatile model for double-gate, triple gate, even cylindrical gate
FET is available now from BSIM group at Berkeley. Passed
Industry FinFET standard balloting in Jan. 2012. (BSIM-CMG)
Fabs: Intel, Global, IBM, Samsung, TSMC

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FinFET vs. Planar MOSFET
Increase effective width for a given footprint: increase
H
fin
and/or reduce fin pitch
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FinFET Inverter Layout
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Reading
Rabaey: Sections 1.3 and 3.3 and chapter 5.
Weste: Chapters 2 and 5 and Sections 2.1 and 2.2.
K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand,
Leakage current mechanisms and leakage reduction
techniques in deep-submicrometer cmos circuits,
Proceedings of the IEEE, vol 91, no. 2, pp. 305327, Feb
2003.

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