Thesis Submitted

Space Vector Modulation of a
4-Leg Matrix Converter

Nicholas J. Mason, BEng. MSc.
Thesis submitted to
The University of Nottingham
for the degree of Doctor of Philosophy
November 2011
Id like to dedicate this work to my father, David Mason,

who passed away before he was able to see its completion,
and whose memory is, and will always be, an inspiration to
me.
Abstract
T HIS thesis covers the investigation into the use of Space Vector Modulation for the control of a 4-leg matrix converter, which is capable of
providing a 3-phase plus neutral supply from a standard balanced 3phase source. Traditional 3x3 matrix converters have limited use in this
application as they are only capable of supplying a balanced three-phase
load. It would be desirable to be able to power unbalanced and nonlinear loads, requiring that the converter provides a neutral connection.
As with voltage source inverters, this goal can be achieved by extending
the number of output legs in the matrix converter to four. In this thesis,
a new Space Vector Modulation technique is proposed for this 4-leg,
or 3x4, matrix converter. This technique is an extension of the method
currently in use on 3x3 matrix converters, and so it allows the de-coupled
control of both the input and output. The thesis then goes onto cover
the build of a demonstration converter, looking at the different aspects
which make up a converter, to nally go on to prove the theory, and a
set of results are presented to validate this.
ii
Acknowledgements
I would like to express my utmost thanks for my supervisors, Prof. P.
Wheeler and Prof. J. Clare, for both of their guidance and support, and
most importantly, for their utmost patience in me. I am sure there were
times when they, like me, gave up hope that this work would ever be
completed, but their willingness to help always meant that I could get
going going again.
Id do also like to thank all of the staff within the PEMC group at the
University of Nottingham who have helped me over the now many
years that this work has been in progress. Alongside this I would like
to specically thank Dr Lee Empringham and Dr Alan Watson for there
help at times with the build of the converter, who, along with the workshop technicians were always happy to help when I needed it and whose
help is much appreciated.
Id then like to thank my family and friends, they have been such a
immense support to me, more so than I think many of them know. They
have often picked me up and brushed me off when times were bad, and
so to them I owe a debt of gratitude. In particular though I would like to
say so many thanks to my wonderful partner Elizabeth Heslop, without
her help and support over the months and years that this has taken,
through the sad times and the happy, I am sure it would never have
been nished, and so for that I am eternally thankful. Id also like to say
thank you to my mother, whos always been a support to me, and has
really helped so many times.
And nally like to thank my sponsor, the Engineering and Physical Science Research Council(EPSRC), without whose support I would not have
been able to embark on this course of study, and I am sure they, as much
as anyone will be happy for me to complete.
iii
Contents
Acronyms
1
xvii
1
1.1
The Matrix Converter . . . . . . . . . . . . . . . . . . . . . .
1.2
The 4-leg Inverter . . . . . . . . . . . . . . . . . . . . . . . .
1.3
The 4-leg Matrix Converter . . . . . . . . . . . . . . . . . .
1.4
Applications and Limitations . . . . . . . . . . . . . . . . .
1.5
Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6
2
Introduction
Thesis Overview . . . . . . . . . . . . . . . . . . . . . . . .
Four-Leg Inverter Modulation
11
2.1
2.2
Space Vector Modulation of the 4-Leg 4-Wire Inverter . . . 13

Carrier Based Pule-Width Modulation of the 4-Leg 4-Wire
Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Matrix Converter Modulation
23
3.1
3.2
Alesina/Venturini Method . . . . . . . . . . . . . . . . . . . 26
3.3
Alesina/Venturini Optimum Method . . . . . . . . . . . . 27
3.4
4
Basic theory . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Space Vector Modulation . . . . . . . . . . . . . . . . . . . . 29
Commutation Methods
36
4.1
Overlap Commutation . . . . . . . . . . . . . . . . . . . . . 37
4.2
Dead-time Commutation . . . . . . . . . . . . . . . . . . . . 38
4.3
4-Step Commutation . . . . . . . . . . . . . . . . . . . . . . 39
4.4
Threshold 2-Step Current Commutation . . . . . . . . . . . 40

iv
C ONTENTS
4.5
5
Voltage Sensed Current Commutation . . . . . . . . . . . . 42
Derivation of the Space Vector Modulation technique for the

4-leg Matrix Converter
45
5.1
The Input Voltage Plane . . . . . . . . . . . . . . . . . . . . 46
5.2
The Input Current Plane . . . . . . . . . . . . . . . . . . . . 48
5.3
The Output Voltage Space . . . . . . . . . . . . . . . . . . . 49
5.4
The Switching States . . . . . . . . . . . . . . . . . . . . . . 52

5.4.1
Output Voltage and Switching States . . . . . . . . 57
5.4.2
Input Current and Switching States . . . . . . . . . 60
5.5
Determining the output sector . . . . . . . . . . . . . . . . . 62
5.6
Determining the input sector . . . . . . . . . . . . . . . . . 66
5.7
Selecting the Switching States . . . . . . . . . . . . . . . . . 68
5.8
Combining the Input and Output Spaces . . . . . . . . . . 70
5.9
Calculating the Duty Cycles . . . . . . . . . . . . . . . . . . 74
5.10 Voltage Transfer Ratio . . . . . . . . . . . . . . . . . . . . . 80

5.11 Other Four-Leg Matrix Converter Modulation Methods . . 88
6
Simulation of the 4-leg Matrix Converter

6.1
90
Simulation using Matlab . . . . . . . . . . . . . . . . . . . . 91

6.1.1
6.1.2
6.2
4-Leg Inverter . . . . . . . . . . . . . . . . . . . . . . 91
4-Leg Matrix Converter . . . . . . . . . . . . . . . . 110
Simulation using Saber . . . . . . . . . . . . . . . . . . . . . 126

6.2.1
6.2.2
Saber Simulation Results . . . . . . . . . . . . . . . 136

Further Saber Simulation Work . . . . . . . . . . . . 144
Matrix converter design and construction
201
7.1
Introduction and overview . . . . . . . . . . . . . . . . . . . 201
7.2
Matrix Converter Power Circuit . . . . . . . . . . . . . . . . 203

7.2.1
Devices . . . . . . . . . . . . . . . . . . . . . . . . . . 204
7.2.2
Gate Drive Circuit . . . . . . . . . . . . . . . . . . . 205
7.2.3
Output Current Sensing . . . . . . . . . . . . . . . . 207
7.2.4
Input Voltage Sensing . . . . . . . . . . . . . . . . . 208

v
C ONTENTS
7.2.5
7.2.6
PCB Design and implementation . . . . . . . . . . . 210
7.2.7
Input Filter . . . . . . . . . . . . . . . . . . . . . . . 211
7.2.8
7.3
Clamp Circuit . . . . . . . . . . . . . . . . . . . . . . 210
Output Inductors and Load . . . . . . . . . . . . . . 212
Matrix Converter Control . . . . . . . . . . . . . . . . . . . 213

7.3.1
7.3.2
Field Programmable Gate Array . . . . . . . . . . . 217
7.3.3
Host Port Interface . . . . . . . . . . . . . . . . . . . 220
7.3.4
8
Digital Signal Processor . . . . . . . . . . . . . . . . 213
Matlab/PC . . . . . . . . . . . . . . . . . . . . . . . 221
Experimental Results
224
8.1
8.2
Balanced Load . . . . . . . . . . . . . . . . . . . . . . . . . . 225
8.3
Unbalanced Load . . . . . . . . . . . . . . . . . . . . . . . . 233
8.4
9
Initial Testing . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Conclusions
238
A Papers published as a result of this work
240
B IGBT Datasheet
241
C FPGA Memory Locations within the DSP Memory Space
247
References
253
vi
List of Figures
1.1
An Example of a Standalone Power Supply System using

a variable speed generator . . . . . . . . . . . . . . . . . . .
A 4-Leg Matrix Converter as part of a Standalone Power

Generation System . . . . . . . . . . . . . . . . . . . . . . .
1.3
A 3-phase Cycloconverter . . . . . . . . . . . . . . . . . . .
1.4
A 3-Leg Matrix Converter . . . . . . . . . . . . . . . . . . .
1.5
A 4-Leg Inverter . . . . . . . . . . . . . . . . . . . . . . . . .
1.6
A 4-Leg Matrix Converter . . . . . . . . . . . . . . . . . . .
2.1
3-Leg 4-Wire Inverter with a Split dc Neutral Connection . 11
2.2
3-Leg 4-Wire Inverter PWM . . . . . . . . . . . . . . . . . . 12
2.3
4-Leg 4-Wire Inverter . . . . . . . . . . . . . . . . . . . . . . 13
2.4
3-Leg Inverter Demand Vector . . . . . . . . . . . . . . . . . 15
2.5
4-Leg Inverter Switching Vectors . . . . . . . . . . . . . . . 17
2.6
4-Leg Inverter Demand Vector . . . . . . . . . . . . . . . . . 18
2.7
4-Leg Inverter Demand Vector Tetrahedron . . . . . . . . . 19
2.8
4-Leg Inverter Space Vector Modulation PWM Output . . . 19
2.9
4-Leg 4-Wire Inverter . . . . . . . . . . . . . . . . . . . . . . 20
1.2
2.10 4-Leg 4-Wire Inverter Carrier-based PWM . . . . . . . . . . 22

3.1
Base set of SVM Vectors for a Balanced 3-Phase Set plotted

in the plane . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.2
Output Voltage Vectors plotted in the plane . . . . . . . 33
3.3
Input Current Vectors plotted in the plane . . . . . . . . 34
3.4
Input Current and Output Voltage Sectors, showing the

required switching states . . . . . . . . . . . . . . . . . . . . 34
vii
L IST OF F IGURES
4.1
Segment from a Matrix Converter Circuit . . . . . . . . . . 36
4.2
Overlap Current Commutation . . . . . . . . . . . . . . . . 37
4.3
Deadtime Current Commutation . . . . . . . . . . . . . . . 38
4.4
Four-Step Current Commutation . . . . . . . . . . . . . . . 40
4.5
Threshold 2-Step Current Commutation . . . . . . . . . . . 41
4.6
Threshold 2-Step with Low Current Deadtime Commutation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.7
Current Direction Detection using Voltage drops in a bidirectional Switch . . . . . . . . . . . . . . . . . . . . . . . . 43
4.8
Voltage Sensed Current Commutation . . . . . . . . . . . . 44
5.1
Input space showing the 3 primary input voltage vectors 47
5.2
Input space showing the 3 primary input current vectors 49
5.3
Output space showing the 4 primary output voltage

vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.4
3x3 Matrix Converter stationary vectors . . . . . . . . . . . 53
5.5
Stationary vectors plotted in space . . . . . . . . . . . 57
5.6
Stationary vectors plotted in space . . . . . . . . . . . 60
5.7
Stationary Current vectors plotted in space . . . . . . . 61
5.8
Projection of the Vector Space onto the plane . . . . 62
5.9
Exploded Diagram of how the Tetrahedrons make up a

Prism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.10 Input Current Plane showing input current vector ii . . . . 67

5.11 Line and Phase Voltage plots showing current sector . . . . 69
5.12 Demand Vector generation from the 3 Space Vectors . . . . 70
5.13 Input Current Vector generation from the 2 Space Vectors . 72
5.14 Distance of the vector vd from the plane Ov2 v3 . . . . . . . 75
5.15 Input Phase Voltage waveforms with the Output Voltage
Waveforms contained with the envelope . . . . . . . . . . . 81
5.16 Line-Line Input Voltage waveforms, showing the envelope of the rectied waveforms . . . . . . . . . . . . . . . . 84
5.17 Circuit Diagram of the 4-Leg Matrix Converter using the
Fictitious DC Link . . . . . . . . . . . . . . . . . . . . . . . 89
viii
L IST OF F IGURES
6.1
Block Diagram for the Matlab simulation for the 4-Leg

Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.2
Exploded view of a single prism, showing the 4 tetrahedrons 95
6.3
Closeup view of a single prism, showing the Demand Vector 96
6.4
Output from the 4-Leg Inverter Simulation, showing the

Calculated and Demand Output Voltages . . . . . . . . . . 99
6.5
Output Voltage Vector angle, Tetrahedron and Prism for

the 4-Leg Inverter Simulation . . . . . . . . . . . . . . . . . 100
6.6
Line and Phase Output Voltages from the 4-Leg Inverter

Simulation, showing the results from the Lookup and General Method . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.7
Duty cycle plots for the Lookup and General methods of

4-Leg Inverter Simulation . . . . . . . . . . . . . . . . . . . 106
6.8
Output Phase Voltage for a 4-leg Inverter when following

a complex set of demand voltages . . . . . . . . . . . . . . 109
6.9
Block Diagram of the 4-Leg Matrix Converter Matlab Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
6.10 4-Leg Matrix Converter output voltages for the original

derived duty cycle equations . . . . . . . . . . . . . . . . . 121
6.11 4-Leg Matrix Converter output voltages for the simplied
duty cycle equations . . . . . . . . . . . . . . . . . . . . . . 121
6.12 4-Leg Matrix Converter Simulation Internal Variables . . . 122
6.13 4-Leg Matrix Converter Output Voltages when operating
with q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
6.14 4-Leg Matrix Converter Simulation Results when operating with q and voltages synchronised . . . . . . . . . . . . 124
6.15 4-Leg Matrix Converter Simulation Results when operating with q and voltages unsynchronised . . . . . . . . . . . 125
6.16 Bi-directional Switch Circuit . . . . . . . . . . . . . . . . . . 127
6.17 Circuit Diagram used for the Bi-Directional Switch block
in the Saber simulations . . . . . . . . . . . . . . . . . . . . 128
6.18 Circuit Diagram used for the Saber simulations . . . . . . . 129
6.19 Control Block for Saber simulation . . . . . . . . . . . . . . 130
6.20 A Basic Switching Sequence . . . . . . . . . . . . . . . . . . 132
6.21 4-Leg Matrix Converter Switching Sequences . . . . . . . . 135
ix
L IST OF F IGURES
6.22 Block Diagram of the MAST template for the Control Block 137
6.23 Circuit Diagram of the 4-Leg Matrix Converter for simulating the effects of the Input Filter . . . . . . . . . . . . . . 152
6.24 Plot of Control Block Internal Input Variables . . . . . . . . 156
6.25 Plot of Control Block Internal Output Variables . . . . . . . 157
6.26 Plot of Control Block Switching State Duty Cycles . . . . . 158
6.27 Plot of Demand and Output Phase-neutral Voltage for Leg a159
6.28 Plot of Output Phase-neutral Voltage for Leg a . . . . . . . 160
6.29 Plot of the FFT of the Output Phase-neutral Voltage on Leg a161
6.30 Plot of the 3 Output Phase-neutral Voltages at the load . . 162
6.31 Plot of the FFT of the Output Phase-neutral Voltage on Leg
a at the load . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
6.32 Plot of the Gate Control Signals . . . . . . . . . . . . . . . . 164
6.33 Plot showing the Switching of the Voltage on Leg a . . . . 165
6.34 Plot of Output Phase Voltages for Leg a . . . . . . . . . . . 166
6.35 Plot of the Input Current and Voltage for Supply Phase A . 167
6.36 Plot of the FFT of Input Current for Supply Phase A . . . . 168
6.37 Plot of the FFT of Input Current for Supply Phase A scaled
as a % of the fundamental . . . . . . . . . . . . . . . . . . . 169
6.38 Plot of the Output Currents showing an Unbalanced Load 170
6.39 Plot of the FFT of Output Phase-neutral Voltages with an
Unbalanced Load . . . . . . . . . . . . . . . . . . . . . . . . 171
6.40 Plot of the Input Current and Voltage for Supply Phase A
with an Unbalanced Load . . . . . . . . . . . . . . . . . . . 172
6.41 Plot of the FFT of Input Current for Supply Phase A with
an Unbalanced Supply . . . . . . . . . . . . . . . . . . . . . 173
6.42 Plot of FFT of the 3 Output Phase-neutral Voltages for
Unbalanced Demands . . . . . . . . . . . . . . . . . . . . . 174
a using Two Zero . . . . . . . . . . . . . . . . . . . . . . . . 175
a using Three Zero . . . . . . . . . . . . . . . . . . . . . . . 176
6.45 Plot of the Supply Voltage alongside the Sampled Voltage
showing the Processing Delay within the Converter . . . . 177
x
L IST OF F IGURES
6.46 Plot of the Supply Voltage alongside the Sampled Voltage
showing the Processing Delay Compensation . . . . . . . . 178
6.47 Plot of the FFT of the Output Voltage, Van, with and and
without compensation for the processing delay using the
Delta method . . . . . . . . . . . . . . . . . . . . . . . . . . 179
6.48 Plot of the noisy Input Voltage, VA, alongside the PLL
tracked fundamental frequency output used by the converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
6.49 Plot of the Output Voltage, Van, and its Spectra showing
the effect of Noise when using the Delta method . . . . . . 181
6.50 Plot of the Output Voltage, Van, and its Spectra showing
the effect of Noise when using the PLL . . . . . . . . . . . . 182
6.51 Plot of the FFT of the Output Voltage, Van, with and without the truncation effect of the FPGA minimum step size . 183
6.52 Plot of the FFT of the Output Voltage, Van, showing the
original along with the output which is compensated for
the truncation effect of the FPGA minimum step size . . . 184
6.53 Plot of the Output Voltage, Van, and its Spectra, showing
the combined effect of the different types of compensation 185
6.54 Plot showing the switching sequence used for commutation going from a lower to a higher voltage input phase . . 186
6.55 Plot showing the switching sequence used for commutation going from a higher to a lower voltage input phase . . 187
6.56 Plot of the FFT of the Output Voltage, Van, comparing the
commutated output to the ideal . . . . . . . . . . . . . . . . 188
6.57 Plot of Input Phase A Supply Voltage and Current, along
with the voltage seen at the converter, when using a 1mH/33F
Input Filter with no PLL . . . . . . . . . . . . . . . . . . . . 189
Input Filter with no PLL . . . . . . . . . . . . . . . . . . . . 190
Input Filter using a PLL . . . . . . . . . . . . . . . . . . . . 191
6.60 Plot of Output Voltage, Van, along with its Spectra, when
using a 1mH/33F Input Filter using a PLL . . . . . . . . . 192
xi
L IST OF F IGURES
with the voltage seen at the converter, with a changing
input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
6.62 Plot of Output Voltage, Van, along with its Spectra, with a
changing input voltage . . . . . . . . . . . . . . . . . . . . . 194
input frequency . . . . . . . . . . . . . . . . . . . . . . . . . 195
changing input frequency . . . . . . . . . . . . . . . . . . . 196
input voltage and frequency . . . . . . . . . . . . . . . . . . 197
changing input voltage and frequency . . . . . . . . . . . . 198
input voltage and frequency, driving an unbalanced load . 199
changing input voltage and frequency, driving an unbalanced load . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
7.1
Broad Overview of the different areas in a Matrix Converter202
7.2
Block Diagram of the Matrix Converter Power Circuit . . . 203
7.3
A Single Bi-directional Switch . . . . . . . . . . . . . . . . . 204
7.4
Circuit Diagram of the Gate Drive Circuit for a single Bidirectional Switch . . . . . . . . . . . . . . . . . . . . . . . . 206
7.5
Circuit Diagram of the Current Sense Circuit . . . . . . . . 208
7.6
Circuit Diagram of the Voltage Sensing Circuit . . . . . . . 209
7.7
Circuit Diagram of the Voltage Clamp used for Converter

Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
7.8
Circuit Diagram of the Supply and Input Filter for the 4Leg Matrix Converter . . . . . . . . . . . . . . . . . . . . . . 212
7.9
Block Diagram for the DSP Software for the 4-Leg Matrix
Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
7.10 Block Diagram showing the main components of the FPGA 218
xii
L IST OF F IGURES
7.11 The Main Control Interface for the 4-Leg Matrix Converter 222
7.12 The FGPA Registers Display Window . . . . . . . . . . . . 223
8.1
Plot of the 4-Leg Matrix Converter Output Phase-neutral

Voltages at the Load . . . . . . . . . . . . . . . . . . . . . . 225
8.2
Plot of the 4-Leg Matrix Converter Output Phase-neutral

Voltages at the Load . . . . . . . . . . . . . . . . . . . . . . 226
8.3
Plot of the FFT of the Output Phase-neutral Voltage on Leg

a at the Load . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
8.4
Closeup of the FFT of the Output Phase-neutral Voltage

on Leg a at the Load . . . . . . . . . . . . . . . . . . . . . . 227
8.5
Plot of the FFT of the Output Phase-neutral Voltage on Leg

a at the Converter . . . . . . . . . . . . . . . . . . . . . . . . 228
8.6
Plot of the 4-Leg Matrix Converter Input Currents . . . . . 228
8.7
Plot of the FFT of the Input Current of Phase A . . . . . . . 229
8.8
Closeup of the FFT of the Input Current of Phase A . . . . 229
8.9
Plot of the 4-Leg Matrix Converter Input Current and Voltage for Phase A . . . . . . . . . . . . . . . . . . . . . . . . . 230
8.10 Plot of the 4-Leg Matrix Converter Output Leg Currents

for Balanced Operation . . . . . . . . . . . . . . . . . . . . . 231
8.11 Plot of the 4-Leg Matrix Converter Duty Cycles during
Balanced Operation . . . . . . . . . . . . . . . . . . . . . . . 231
8.12 Plot showing Ti , the time taken to process the DSP interrupt routine, alongside the SVM Period, Ts . . . . . . . . . 232
8.13 Plot of the Input Current of Phase A with an Unbalanced
Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
8.14 Plot of the FFT of the Input Current of Phase A with an
Unbalanced Load . . . . . . . . . . . . . . . . . . . . . . . . 234
8.15 Close-up of the FFT of the Input Current of Phase A with
an Unbalanced Load . . . . . . . . . . . . . . . . . . . . . . 234
8.16 Plot of the FFT of the Output Phase-neutral Voltage for
Leg c at the Converter for an Unbalanced Load . . . . . . . 235
8.17 Plot of the FFT of the Output Phase-neutral Voltage for
Leg c across the Load for an Unbalanced Load . . . . . . . 235
xiii
L IST OF F IGURES
8.18 Close-up of the FFT of the Output Phase-neutral Voltage
for Leg c across the Load for an Unbalanced Load . . . . . 236
8.19 Plot of the 4-Leg Matrix Converter Output Leg Currents
for an Unbalanced Load . . . . . . . . . . . . . . . . . . . . 236
xiv
List of Tables
2.1
3-Leg Inverter Switching Combinations . . . . . . . . . . . 14
2.2
3-Leg Inverter Switching Combinations in Space . . . . 14
2.3
4-Leg Inverter Switching Combinations . . . . . . . . . . . 16
2.4
4-Leg Inverter Switching Combinations in Space . . . 16
3.1
3x3 Matrix Converter Stationary and Zero Switching Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.2
3x3 Matrix Converter Stationary and Zero Switching Combinations transformed in the Plane . . . . . . . . . . . . 32
5.1
Rotating Switching States for the 4-Leg Matrix Converter . 54
5.2
Stationary and Zero Switching States for the 4-Leg Matrix

Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.3
Tetrahedron Lookup Table . . . . . . . . . . . . . . . . . . . 65
5.4
Switching state selection example . . . . . . . . . . . . . . . 69
5.5
The Base Vectors for the stationary space vectors . . . . . . 71
6.1
Switching state and Duty-Cycle selection for the 4-Leg Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.2
Switching States for a 4-Leg Inverter . . . . . . . . . . . . . 98
6.3
Switching state and Duty-Cycle selection for the 4-Leg Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.4
6.5
Tetrahedron Lookup . . . . . . . . . . . . . . . . . . . . . . 115
6.6
6.7
xv
L IST OF TABLES
6.8
6.9
Switching state output leg input phase . . . . . . . . . . . . 131
6.10 Modied switching state order to minimise the number of

switching transitions . . . . . . . . . . . . . . . . . . . . . . 131
6.11 Two Zero Switching State Sequence . . . . . . . . . . . . . 133
6.12 Three Zero Switching State Sequence . . . . . . . . . . . . . 134
xvi
Acronyms
DSP digital signal processor.
FCC force-commutated cycloconverter.
FET eld effect transistor.
FFT fast Fourier transform.
FIFO First-In First-Out.
FPGA eld programmable gate array.
GPU ground power supply unit.
GTO gate turn-off thyristor.
GUI graphical user interface.
HPI Host Port Interface.
IGBT insulated gate bipolar transistor.
MEX Matlab executable.
NCC naturally commutated cycloconverter.
PCB printed circuit board.
PEMC Power Electronic and Machine Control.
PLL phase-locked loop.
PWM pulse-width modulation.
SCR silicon controlled rectier.
SVM space vector modulation.
xvii
A CRONYMS
UPS uninterruptible power supply.
USB Universal Serial Bus.
xviii
C HAPTER 1
Introduction
Over recent years there has been an increased interest in static power
converters, and this has led to a rapid improvement in their technology.
The use of such converters in various AC power supply applications has
also grown, and still continues to do so, with static power converters
now being a common part in many different systems, from uninterruptible power supplies (UPSs), power converters in submarines through to
ground power supply units (GPUs) for aircraft. One other typical application is for mobile power generation, and such a system is shown in Figure 1.1. This is an outline of a complete standalone system for providing
a three-phase power supply wherever it is needed using a variable speed
generator. The particular setup shown, uses the variable speed generator
connected to a power converter, which allows the engine driving the
generator to operate over a wide range of engines speeds and loads,
with the power converter then providing a xed frequency xed voltage
supply[1].
The power converter used in the scheme shown in Figure 1.1 could be a
standard 3-phase rectier/inverter setup, although this is a good setup
where a matrix converter could be used. There is a problem with both
of these types of converter, and it is that, while capable of generating
a balanced three-phase supply, they are not able to operate with unbalanced, non-linear, or single-phase loads. To enable the system to
generate an AC supply capable of supplying single-phase or unbalanced
three-phase loads the converter needs to be able to deal with the unbalanced neutral,or zero-sequence, current. One method for doing this
with an inverter is to increase the number of converter output legs to
include a neutral connection[2]. Extending this in the case of the matrix
converter would result in a 3x4, or four-leg, matrix converter as shown in
Figure 1.2. This shows a simplied version of Figure 1.1 with a four-leg
matrix converter attached to the generator.
1
C HAPTER 1: I NTRODUCTION
Figure 1.1: An Example of a Standalone Power Supply System using a

variable speed generator
3-Phase
Generator
Bi-directional
Switch
Variable frequency
Variable output voltage
3-Phase plus neutral
Figure 1.2: A 4-Leg Matrix Converter as part of a Standalone Power

Generation System
With the introduction of the fourth leg, this adds another output variable that needs to be controlled, and so the modulation techniques why
apply to the 3x3 matrix converter[36] are no longer valid, and so a new
modulation strategy needs to be formulated for this new arrangement.
After the work by Huber and Borojevic [710] and later Casadei[3, 4]
on adapting space vector modulation (SVM) for use with the 3x3 matrix
converter, and then Ryan and De Doncker [11, 12] along with Zhang
at al[2, 13, 14] for the work on 3-dimensional SVM for the 4-leg inverter,
these both proved as useful pointers towards how a successful technique
could be derived for the 4-leg Matrix Converter. Therefore, this work
sets out to explore the design of a Space Vector Modulation technique
that is capable of controlling a 4-leg matrix converter, and then goes on
to detail the building and testing of such a converter.
The basis of the space vector modulation strategy for the 3x3 matrix
converter[3, 7] was derived from the techniques for both the controlled
rectier, and the inverter. This new technique will mirror this, and so
be derived from the modulation method used for a 3-phase rectier and
a four-leg inverter[12, 14]. This will use a space vector representation
in a three-dimensional space to describe the output voltage and
switching states[11, 12, 14]. This modulation technique will enable the
inverter, and thus the matrix converter, to provide any set of output lineto-neutral voltages, balanced or unbalanced, that may be required. This
three-dimensional approach will then be combined with the standard
two-dimensional SVM method for the input side of the matrix converter,
in a similar way to that performed for the 3x3 matrix converter[3, 4]. The
resulting SVM method will be a way of controlling the modulation of
the four-leg matrix converter so as to produce any set of line-to-neutral
voltages whilst also independently controlling the phase of the input
current waveforms.
1.1
The Matrix Converter
Matrix converters are a class of converters which perform direct AC-AC

power conversion and themselves are part of the larger class of converter which are called cycloconverters. The process is called direct
conversion to differentiate them from the more well known rectier and
inverter pairing as there is no intermediate DC link, and no energy storage devices within the converter. Cycloconverters rst appeared in the
1920s and 1930s using mercury arc rectiers[1517] and are still in use
today[17, 18], although now using devices such as the silicon controlled
rectier (SCR) and gate turn-off thyristor (GTO), in very high power
industrial applications such a rolling mills.[19]. An example of 3-phase
cycloconverter is shown in Figure 1.3.
The cycloconverters themselves fall into two main groups: those which use the supply line voltage to perform the current
commutation between the devices, which are known as naturally
commutated cycloconverters (NCCs)
those in which the current commutation is forced between devices,
3
and are known as force-commutated cycloconverters (FCCs)
The naturally commutated cycloconverters use devices such as thyristors and SCRs to be able to control the point at which the device starts
conducting, thus, by choosing the correct phases from the input voltage,
an output voltage can be synthesised. However, due to the nature of the
devices they require the current in the device to reach zero before the
device can be turned off, so while it is possible to control the turn on of
each device, the turn off happens as the current naturally falls within the
device due to the changes in input voltage. Being able to control only
the device turn on means that the range output frequency is limited to
being below the input frequency[1517].
Va
VA
VB
VC
Vb
Vc
Figure 1.3: A 3-phase Cycloconverter

With the advance in the capability of switching devices, most notably
insulated gate bipolar transistors (IGBTs), and due to its relative complexity, which can be seen in Figure 1.3, this type of cycloconverter now
tends to only be used in high power applications, above the 1MW level,
where the low frequency output is able to be used effectively, for example, like driving induction motors in large industrial processes, or for
thrusters for large navel vessels[17, 18].
The force-commutated cycloconverters on the other hand, use devices
which are capable of being switched off while current is still owing
through them, and so can be turned off at any point in the conduction
cycle, instead of having to wait for the current through the device to
drop to zero. This allows the force-commutated cycloconverter to overcome the largest drawback of the naturally commutated one, and be able
4
to produce outputs at any frequency required, regardless of the input
frequency[5].
Figure 1.4: A 3-Leg Matrix Converter

A 3x3 matrix converter is shown in Figure 1.4, and due to using switches
that have the ability to be turned of, this allows the circuit to be simpler.
Although the concept of matrix converters had been around for a number of years it was not until Alesina and Venturini published a paper
at the beginning of the 1980s[5] that there become a way of controlling
them which allowed both the input current and the output voltage to be
The initial Alesina and Venturini method had a disadvantage though,
that the output voltage was restricted to be a maximum of only 0.5 of the
input. However, towards the end of the 1980s they published a number
of papers which rst showed that the theoretically maximum output
voltage was 23 [20] and then went on to show how this was possible with
their optimum method[6]. Lipo produced a similar result in 1989, while
also succeeding in building a working converter[21] to demonstrate this.
At around the same time, a number of papers by Huber and Borojevic
were published, which presented a new space vector modulation technique for the matrix converter [710]. This like the Alesina\Venturini
Optimum method, was able to produce the theoretical maximum output
voltage. Space Vector Modulation is a well known technique for controlling inverters, and it uses a technique which transforms the input and
output voltages and currents into a 2-dimensional plane where they can
then be easily manipulated. This is as opposed to the method Alesina
and Venturini used which is based around the use and theory of sine
waves.
Later on the space vector modulation technique was rened further by
Casadei[3, 4], and while more recent matrix converter congurations
5
and modulation strategies have been proposed[22, 23], it is the technique
proposed by Casadei which this project seeks to extend onto the 4-Leg
Matrix Converter.
1.2
The 4-leg Inverter
The four-leg inverter rst appeared in the early 1990s[24] when a solution was sought to allow the standard 3-leg inverter to drive unbalanced
and non-linear loads[2427]. Due to the nature of these loads they cause
an imbalance in the current drawn from each phase of the supply, which
then requires an extra neutral connection to deal with the zero sequence
current which then results. While the use of a split capacitors to provide
this neutral point was investigated[26, 28], this arrangement only works
well if the imbalance, or non-linearity, is small. Instead of the split capacitors, the 4-legged inverter uses an extra inverter leg to provide this
connection, and Figure 1.5 shows an example.
Vdc
Sn1
a pwm
n pwm
Vn
Sn2
n pwm
Sb1
Sa1
c pwm
b pwm
Vc
Vb
Va
Sa2
a pwm
Sc1
Sb2
b pwm
Sc2
c pwm
Figure 1.5: A 4-Leg Inverter

The initial attempts at controlling the 4-leg inverter were based around
controlling the fourth leg separately, and using it to reduce any deviation
in the neutral voltage[24, 26]. It was then in the late 1990s that Space
Vector Modulation techniques for these inverters were introduced[25].
This was around the same time that Zhang et al[2, 13] introduced a new
3-Dimensional Space Vector Modulation technique which allowed the
independent control of each of the 3 main output phases with respect
to the neutral. The concepts which were introduced by Zhang were
then later expanded upon by Ryan, Lorenz and De Doncker[11, 12] who
produced a mathematical grounding for this new SVM technique.
Later in 2002, Zhang et al presented a fuller version of their original
approach[14], and it is this work that this project seeks to extend in
6
conjunction with the SVM technique for matrix converters which was
proposed by Casadei[4].
1.3
The 4-leg Matrix Converter
The 4-leg Matrix Converter was, at the start of this project, a novel circuit
which had yet to see any work published about it, although this may not
be surprising with the majority of research effort in the matrix converter
eld being concentrated on the practical side to converter implementation, and the relative lack of appreciable applications.
Figure 1.6: A 4-Leg Matrix Converter

It is, quite simply a 3x3 matrix converter with a fourth output leg added
to act as the neutral leg, with Figure 1.6 showing the basic layout. The
idea being that as with the 4-leg inverters, the extra output leg would
enable the converter to be able to power non-linear and unbalanced
loads.
At the beginning of this work, although presumed possible, it was unknown as to the ability to control one of these converters by using either the Space Vector Modulation principles, or the Alesina\Venturini
methods. The Space Vector Modulation SVM method was chosen to be
the basis of the work as it looked to be the most promising due to the
existence of similar methods for both the matrix converter and the 4-leg
inverter.
1.4
Applications and Limitations
One major application for this type of converter is as part of a eld power
supply, which is the type of system briey described above and shown in
7
Figure 1.1, and which has since entered development by the University
of Nottingham[29, 30]. In this application it is able to demonstrate its
main advantage over other types of converter in that it is able to supply
power for not only balanced 3-phase sources, but also unbalanced and
single phase loads. So, along with the advantages that comes from being
a matrix converter, so it being compact and able to achieve high power
densities due to not requiring a DC link capacitor, means that it is highly
suited to this task.
Having the converter in this conguration, running directly from a generator also helps mitigate the biggest drawback of this converter, and
that is the quality of the input current when drawing an unbalanced
load. As will be demonstrated, once the load becomes unbalanced, due
to the direct nature of the converter with it having no energy storage
elements unlike a normal inverter, there is no way to buffer the supply
from the irregular power drawn, which, if the load is highly unbalanced
can lead to distortion of the supply voltage. However, with the standalone setup above these harmonic currents will be drawn from the
generator, and by careful speed control of the engine the worst effects
of this imbalance can be moderated.
One characteristic that this converter has, is the ability to individually
alter its output phase voltages, and frequencies, independently of one
another. While this might not immediately appear to have an application, it might be of some use when dealing with fault situations on the
load, where the converter would be able to balance the load power per
phase individually in order to not affect the supply, however such work
fell outside the scope of this project and so will need to be investigated
separately.
1.5
Objectives
The objective of this project was simple, to investigate the use of Space
Vector Modulation to enable the control a 4-Leg Matrix converter. To this
end it would have a number of outcomes:
Firstly, as this is a novel implementation of SVM on a new converter, it
would involve the understanding and analysis of the two similar types
of space vector modulation that previously existed, that of the 4-leg inverter and the matrix converter, and only from this point would it be
possible to extent both methods to cover the 4-leg matrix converter. Then
once the theory behind the operation of those converters was under8
stood, it would then be possible to understand the rules which would
govern the behaviour of the 4-leg matrix converter. At this point it would
then be possible to derive the equations which would govern its operation.
The next objective would be to then produce a set of simulations which
would be able to accurately model the behaviour of the 4-leg matrix
converter using the derived equations. This would lead to a set of Matlab
programs which however this would rst require the implementation of
the two other converters to prove that the
The nal objective in this project is to build and run a working demonstration model of the 4-leg matrix converter. This would involve the
evolution of a pre-existing matrix converter design to add the extra output leg, and then require a new set of software to be able to operate and
control the converter.
1.6
Thesis Overview
In Chapter 1 the concept of the matrix converter is discussed along with

a brief history of the circuit, followed by a short discussion on the 4-leg
inverter. This will then follow on to an introduction of the concept of the
4-Leg Matrix converter, followed by short look at a possible implementation, and also a look at its possible drawback.
Chapter 2 then looks into the detail of how a number of different modulation schemes work for the 4-leg inverter, most importantly, it sets out
the basis for and the equations which govern the use of space vector
modulation with the circuit.
Chapter 3 looks at the other important relative of the 4-leg matrix converter, the normal matrix converter and goes on to examine the two
major different methods which enable its control, nishing on the implementation of space vector modulation for the converter.
Chapter 4 then takes a brief look into the different possible commutation
strategies which are employed in switched power converters, and matrix
converters specically.
In Chapter 5 the basis behind Space Vector Modulation of a 4-Leg Matrix
converter is derived. Starting by looking at both the input and outputs
vector spaces, this chapter goes on to see how they are linked together,
demonstrating the symmetry between the two and produces the calculations which will select the required switching states and calculate the
9
duty cycles.
Chapter 6 then builds on the work of the previous chapter, taking the derived equations and then initially simulates them mathematically within
Matlab, before moving on to perform a number of circuit based simulations within the Saber simulation software. These simulations will be
used to validate the derivation, while also becoming a good base for the
code which will be required to build an actual converter.
Chapter 7 describes the build of a demonstration converter based on
an existing 3x3 matrix converter design. This chapter briey looks at
each of the main parts that goes into building a converter, describing its
operation and going into detail where it is required.
Chapter 8 gives a summary of the results from testing the converter. It
shows how the output from the converter is very well matched with that
expected after the simulations, but then goes on to describe the issues
which the converter had during testing, which ultimately meant that
the converter failed and stopped testing short of the ideal, but still with
enough information to demonstrate that the concept worked well.
Chapter 9 then follows with the conclusions on the work presented here.
10
C HAPTER 2
Four-Leg Inverter Modulation

The four-leg inverter is an evolution of the standard three-leg inverter,
and was bought about by the need to run non-linear and unbalanced
three-phase loads, a fourth-wire as the neutral connection to the load.
This was initially congured so that the fourth wire was held at the midpoint of a pair of capacitors[28], with Figure 2.1 showing an example of
this layout.
Vdc
Sa1
Sb1
a pwm
Vn
b pwm
c pwm
a pwm
Vc
Vb
Va
Sa2
Sc1
Sb2
b pwm
Sc2
c pwm
Figure 2.1: 3-Leg 4-Wire Inverter with a Split dc Neutral Connection

As can be seen the pair of capacitors, when charged, hold the voltage
of the fourth wire at the midpoint of the DC voltage, with any neutral
current being passed to one or the other of these. This arrangement
works well when the level of unbalance is low, and so neutral currents
are relatively low, as the technique relies upon the capacitors holding
the neutral point voltage steady at the mid-point of the DC-link. But as
loads become more non-linear or unbalanced then the neutral current
can become large, with this current needing to ow through the capacitors and so requiring large value capacitors capable of handling high
11
C HAPTER 2: F OUR -L EG I NVERTER M ODULATION

ripple currents to avoid shifting the neutral point, which if allowed to
occur will distort the output voltages.
This is actually a relatively simple circuit to control however, with each
of the three switched legs effectively operating as a stand-alone halfbridge single phase inverter, switching its output about the clamped DC
mid-point. This means that a simple carrier based pulse-width modulation (PWM) technique can be employed as shown below in Figure
2.10. In this technique, each of the three output phases is driven by
a separate voltage demand signal and these are then compared to a
triangular carrier waveform. The results of these comparisons are then
fed into the respective gate drive circuits, which in turn drive the IGBTs.
Va
a pwm
Vb
b pwm
Vc
c pwm
(a) 3-Leg 4-Wire Inverter PWM Scheme

Vdc
2
Va
Vc
0V
Vb
dc
- V2
Ts /2
Ts /2
Ts
a pwm
b pwm
c pwm
(b) 3-Leg 4-Wire Inverter PWM Timing
Figure 2.2: 3-Leg 4-Wire Inverter PWM

However, using such a simple technique shows another drawback of
this topology, in that it only allows a maximum voltage transfer ratio of
12

0.5Vdc per phase. Techniques which are used in 3-phase 3-wire inverters
to increase the maximum voltage transfer ratio, such as Third Harmonic
Injection, are now not really applicable. For example, with third harmonic injection, the injected harmonics present in the output phases will
force a shift in the neutral point voltage, at the third harmonic frequency,
and so generate a respective neutral current through the capacitors.
2.1
Space Vector Modulation of the 4-Leg 4-Wire

Inverter
To overcome the limitations with the above circuit, instead of generating the neutral voltage using a split DC link the neutral voltage can be
generated by using a fourth inverter leg[24, 25, 27], leading to the actual
4-leg inverter as shown in Figure 2.3.
Vdc
Sn1
Sa1
a pwm
n pwm
Vn
Sn2
n pwm
Sb1
c pwm
b pwm
Vc
Vb
Va
Sa2
a pwm
Sc1
Sb2
b pwm
Sc2
c pwm
Figure 2.3: 4-Leg 4-Wire Inverter

Now while it is possible to independently control the neutral voltage to
mimic that generated by the split capacitor circuit above, this does not
make full use of the ability of the extra leg to control the neutral point
to any voltage up to the DC link voltage. However, once the neutral
voltage is shifted from its mid point the simple PWM control of the 3-Leg
4-wire inverter is no longer enough, as and shift in the neutral voltage
needs to be reected in changes to all 3 phase voltages. As such, the
Space Vector Modulation technique which is commonly used in 3-wire
inverters was extended by Zhang et al in 1997[2, 13] to allow the control
of the 4-Leg inverter. This method is briey described below, after a
short introduction to how Space Vector Modulation on a more normal
3-leg inverter.
13

So, consider rst a standard 3-leg inverter where the relationship between the three phase voltages Va , Vb and Vc dened by
Va + Vb + Vc = 0
(2.1.1)
This constraint means that only 2 of the phase voltage variables are actually independent. Using this means that the three phase voltages can be
transformed into a 2-dimensional space, in this case the space using
(2.1.2)
Va
Vb
Vc
V
V
1 1
2
2
3
3
2
1
2
3
2
(2.1.2)
With a 3-leg inverter, each leg has only got two possible switching states
during operation, that is to switch that output leg to either the positive or
the negative of the DC link. With 3 legs, each with 2 possible switching
states, this gives 8 possible switching states that can be generated and
these are shown in Table 2.1 below.
Table 2.1: 3-Leg Inverter Switching Combinations
ppp
Va
Vb
Vc
nnn
pnn
ppn
npn
npp
nnp
pnp
1
2 Vdc
1
2 Vdc
1
2 Vdc
- 1 Vdc
2
1
- 2 Vdc
- 1 Vdc
2
1
2 Vdc
- 1 Vdc
2
- 1 Vdc
2
1
2 Vdc
1
2 Vdc
- 1 Vdc
2
- 1 Vdc
2
1
2 Vdc
- 1 Vdc
2
- 1 Vdc
2
1
2 Vdc
1
2 Vdc
- 1 Vdc
2
- 1 Vdc
2
1
2 Vdc
1
2 Vdc
- 1 Vdc
2
1
2 Vdc
Transforming the information in Table 2.1 into the 2-dimensional space

using (2.1.2) then gives the results shown in Table 2.2
Table 2.2: 3-Leg Inverter Switching Combinations in Space
V
V
ppp nnn
0
0
0
0
pnn
2
3 Vdc
0
ppn
1
3 Vdc
1
Vdc
3
npn
npp
nnp
pnp
1
2
1
1
- 3 Vdc - 3 Vdc - 3 Vdc
3 Vdc
1
1
1
Vdc
Vdc - Vdc
0
- 3
3
3
The vectors resulting from these 8 switching states can then be plotted
onto an Argand diagram, giving the well known result shown in Figure 2.4. This plot shows 6 space vectors placed equidistant from each
other around the origin, and these are created by the non-zero switching
states. The remaining two vectors, ppp and nnn, switch the same voltage
to each of the three output legs, and as such they are known as the zero
voltage states and do not produce a vector within the space.
14

Next, consider the demand voltages which are required as an output
from the inverter, now because this is a 3-leg inverter this will be a
3-phase set of voltages which meet the requirement set out in equation (2.1.1). Converting this demand voltage into space using (2.1.2)
produces a vector, vd , as can be seen in Figure 2.4.
pnp
ppn
npp
pnn
vd
npn
nnp
Figure 2.4: 3-Leg Inverter Demand Vector

The basic assumption behind Space Vector Modulation is that this demand vector, vd , within space can be synthesised by using the two
adjacent space vectors created by the converter switching states. So, in
the example shown in Figure 2.4, the demand vector, vd can be generated
using the space vector 1 and 6, which correspond to the switching states
pnn and npn.
Now, consider an inverter with an added fourth leg, as shown in Figure 2.3. By adding this extra leg it means that the equation (2.1.1) above
is no longer necessarily valid as
Va + Vb + Vc + Vn = 0
(2.1.3)
This means that all three phase voltages can now be considered to be
truly independent of each other, and so the 2-dimensional space does
not have enough degrees of freedom to be able to describe them fully. To
cater for the extra independent variable another degree of freedom needs
15

to be added, and so this is instead transformed into a 3-dimensional
space. For this case it is the space using (2.1.4)
1
0
1 2 1
V
2
3
3
0
V = 0 2 2
1
1
1
3
V
2
2
2
2
Va
Vb
Vc
Vn
(2.1.4)
Now, due to inclusion of the extra neutral leg, instead of the 8 possible
switching combinations shown in Table 2.1 above for the 3-leg inverter,
there are now 16 different ones, which are shown in Table 2.3 below
Table 2.3: 4-Leg Inverter Switching Combinations
Van
Vbn
Vcn
Van
Vbn
Vcn
pppp
0
0
0
pppn
Vdc
Vdc
Vdc
nnnp
Vdc
Vdc
Vdc
nnnn
0
0
0
pnnp
0
Vdc
Vdc
pnnn
Vdc
0
0
ppnp
0
0
Vdc
ppnn
Vdc
Vdc
0
npnp
Vdc
0
Vdc
npnn
0
Vdc
0
nppp
Vdc
0
0
nppn
0
Vdc
Vdc
nnpp
Vdc
Vdc
0
nnpn
0
0
Vdc
pnpp
0
Vdc
0
pnpn
Vdc
0
Vdc
Transforming this into the space using (2.1.4) then gives the results
shown in Table 2.4.
Table 2.4: 4-Leg Inverter Switching Combinations in Space
pppp
0
0
nnnp
0
0
pnnp
2
3 Vdc
0
V
V
0
pppn
0
0
Vdc
Vdc
nnnn
0
0
0
2 Vdc
3
pnnn
2
3 Vdc
0
1
3 Vdc
V
V
V
ppnp
1
3 Vdc
1
Vdc
3
npnp
1
3 Vdc
1
Vdc
3
1 Vdc
3
ppnn
1
3 Vdc
1
Vdc
3
2
3 Vdc
2
3 Vdc
npnn
1
3 Vdc
1
Vdc
3
1
3 Vdc
nppp
2
3 Vdc
0
1
3 Vdc
nppn
2
3 Vdc
0
2
3 Vdc
nnpp
1
3 Vdc
1
3 Vdc
2
3 Vdc
nnpn
1
3 Vdc
1
3 Vdc
1
3 Vdc
pnpp
1
3 Vdc
1
3 Vdc
1 Vdc
3
pnpn
1
3 Vdc
1
3 Vdc
2
3 Vdc
The vectors resulting from the 14 non-zero switching states can then
be plotted in the space as shown in Figure 2.5. The remaining 2
vectors, pppp and nnnn, switch the same voltage to each of the four
output legs, and so they are known as the zero vectors as they do not
produce a voltage across the output. As with the vectors for the 3-leg
inverter shown in Figure 2.4, the vectors for the 4-leg inverter are all
positioned equidistantly from each other within the space, and the
shape they describe is a type of icositetrahedron (24-faced polyhedron).
16
Vdc
pppn
2Vdc
3
ppnn
nppn
Vdc
3
pnpn
npnn
pnnn
nnpn
ppnp
nppp
dc
V3
npnp
2Vdc
3
pnpp
pnnp
nnpn
nnnp
Vdc
Figure 2.5: 4-Leg Inverter Switching Vectors

Next, consider a set of demand voltages which are required as the output
from the inverter. Now, because this is a 4-leg inverter this can be any set
of voltages which meet the requirement set out in equation (2.1.3) however, taking the example for the 3-leg inverter above, and applying (2.1.3)
now gives
Va = 240.00
(2.1.5)
Vb = 327.85
Vc = 87.84
Vn = 0
Converting this demand voltage into space using (2.1.4) produces a
vector, vd ,
V = 240.00
V = 240.00
V = 0
17
(2.1.6)

This vector can be seen in Figure 2.6 labelled as the demand vector, vd ,
along with the 3 space vectors required to generate this demand.
Vdc
3
pnnn
nnpn
0
vd
dc
V3
pnpp
Figure 2.6: 4-Leg Inverter Demand Vector

At any one time the demand vector, vd , is bound in a space by 3 of the
switching vectors, in the same way that the demand vector for the 2dimensional Space Vector Modulation is bounded by 2. These 3 switching vectors form the vertices of a tetrahedron, the base of which forms
one face of the icositetrahedron in the switching space. Just as the
3-leg inverter was able to synthesise the demand voltage by switching
between the 2 adjacent switching vectors, the 4-leg inverter is able to
synthesise its demand voltage by using these 3 switching vectors, which
can be seen in Figure 2.7.
Now, while it is a relatively straightforward task to then calculate the
duty cycles for those switching states for the 3-leg inverter, it becomes
somewhat harder for the 4-leg inverter due to the number of different
possible tetrahedrons. The solution proposed by Zhang is to use a lookup table which would dene a matrix[2, 13] that could be used to directly
calculate the duty cycles, so for the example shown in Figure 2.6, the
demand vector would be in Prism IV and Tetrahedron 1, and the duty
cycles would be calculated as
d1
1
d2 =
Vdc
d3
1
2
1
2
3
2
3
2
23
3
2
V (240.00)
1 V (240.00)
V (0.00)
0
1
d z = 1 d1 d2 d3
(2.1.7)
(2.1.8)
Once the duty cycles are known, it is a simple case to produce the re18
2Vdc
3
pnpn
Vdc
3
pnnn
vd
dc
V3
pnpp
Figure 2.7: 4-Leg Inverter Demand Vector Tetrahedron

spective PWM signals as shown in Figure 2.8 where each duty cycle is
for a respective switching state.
nnnn
pppp
pnnn
pnpn
pnpp
a pwm
b pwm
c pwm
f pwm
tz
4
t1
2
t2
2
t3
2
tz
4
Ts
2
Ts
2
Figure 2.8: 4-Leg Inverter Space Vector Modulation PWM Output
2.2
Carrier Based Pule-Width Modulation of the

4-Leg 4-Wire Inverter
Alongside the Space Vector Modulation technique shown above, a complete carrier based implementation of the 4-leg inverter has been proposed by Kim and Sul[31] in 2004. This technique uses an offset voltage
19

concept to be able to generate the three independent voltages Va f , Vb f
and Vc f .
Vdc
Sf1
Vn
Sa1
Vf
Sf2
Sb1
Sc1
Vc
Vb
Va
Sa2
Sb2
Sc2
Figure 2.9: 4-Leg 4-Wire Inverter

Using the circuit of the 4-leg inverter as shown in Figure 2.9 the method
states that the output line to neutral voltages are constrained by the
following equation
Vdc Va f , Vb f , Vc f Vdc
(2.2.1)
where each of the output voltages Va f , Vb f and Vc f are dened by
Va f = Van Vf n
Vb f = Vbn Vf n
(2.2.2)
Vc f = Vcn Vf n
This allows the use of Vf n , the fourth inverter output leg, as an offset
voltage which can be manipulated to control the other 3 output leg voltages where
V
Vdc
Van , Vbn , Vcn dc
2
2
(2.2.3)
Vdc
V
Vf n dc
2
2
(2.2.4)
and
It can then be shown that while Vf n is required to meet the constraints

shown in (2.2.4), in fact Vf n rarely falls outside the following limits
20
Vdc
V
Vmin Vf n dc Vmax
2
2
(2.2.5)
where
Vmin = min(Va f , Vb f , Vc f )
(2.2.6)
Vmid = mid(Va f , Vb f , Vc f )
(2.2.7)
Vmax = max(Va f , Vb f , Vc f )
(2.2.8)
and this should be limited to

Vmax Vmin < Vdc
(2.2.9)
as this would limit the possible offset voltages if the difference between
the maximum and minimum output voltages is equal to or greater than
the DC link voltage.
The optimum level for Vf n is then be calculated as
Vf n = mid
V
Vmax + Vmin
Vmax
, min ,
2
2
2
(2.2.10)
and the switching times for each leg calculated as
Ts
2
Ts
Tb =
2
Ts
Tc =
2
Ts
Tf =
2
Ta =
Van
Ts
Vdc
V
+ bn Ts
Vdc
Vcn
+
Ts
Vdc
Vf n
+
Ts
Vdc
(2.2.11)
(2.2.12)
As demonstrated by Kim and Sul[31], this method gives equivalent performance to the 3-dimensional Space Vector Modulation method as described above.
21
Van
Vaf
a pwm
Vbn
Vbf
b pwm
Vcn
Vcf
c pwm
Calc Vfn
Vfn
f pwm
(a) 4-Leg 4-Wire Inverter Carrier-based PWM Scheme

Vdc
2
Van
Vcn
Vfn
Vbn
dc
- V2
Ts /2
Ts /2
Ts
a pwm
b pwm
c pwm
f pwm
(b) 4-Leg 4-Wire Inverter Carrier-based PWM Timing
Figure 2.10: 4-Leg 4-Wire Inverter Carrier-based PWM
22
C HAPTER 3
Matrix Converter Modulation

The basic premise behind the matrix converter is that you have a set
of nxp bi-directional switches arranged to connect n input phases to
p output legs so that it is possible to connect any output leg to input
phase. The most common conguration for this is the 3-phase to 3phase matrix converter which is shown in Figure 1.4. Due to the inherent
bi-directional nature of the converter, with power able to ow in both
directions, the labelling of the input and output is essentially arbitrary.
However, due to the general modes of operation of the converter it has
become the normal convention that the voltage stiff port is designated
the input and the current stiff port the output. This designation does
however impose a fundamental restriction on how the converter can be
switched. This restriction is that no two input phases can be shorted
together due to their voltage stiff characteristic, and no output legs can
be left open circuit due to their current stiff behaviour.
Prior to the start of this work, the 3x3 matrix converter was the largest
matrix converter for which a solution had been proposed, and this chapter will investigate the different modulation strategies which were common at that time, and which were used as the basis of this investigation.
Since the initial publication of the basic derivation on the 4-leg matrix
converter [32] there have since been a number of different modulation
methods for the 4-leg matrix converter proposed. Since these were not
available at the time the work on this started they have not been included
in this chapter, however a summary of the different methods will be
discussed at the end of the Chapter 5.
23
C HAPTER 3: M ATRIX C ONVERTER M ODULATION
3.1
Basic theory
If we dene the input and output voltages of the converter as the vectors (3.1.1) and (3.1.2) respectively
VA (t)
Vi (t) = VB (t)
VC (t)
V (t)
a
Vo (t) = Vb (t)
Vc (t)
(3.1.1)
(3.1.2)
then a switching function S(t) can be dened as
s Aa (t) s Ba (t) sCa (t)
S(t) = s Ab (t) s Bb (t) sCb (t)

s Ac (t) s Bc (t) sCc (t)
(3.1.3)
where a switch snp in its on-state is represented by a 1 and in its off-state

by a 0. This relates the output voltages Vo (t) to the input voltages Vi (t)
so that
Vo (t) = S(t) Vi (t)
(3.1.4)
To satisfy the restriction that no inputs can be shorted together and no

outputs can be open circuit the following must always be true
n= A,B,C
sna (t) =
snb (t) =
n= A,B,C
snc (t) = 1
(3.1.5)
n= A,B,C
In a similar way the relationship for the input current is given by

Ii (t) = ST (t) Io (t)
(3.1.6)
where the matrix S T is the transpose of the matrix S.

The switching matrix S gives us the switching function at any particular
instant but as the switches are operated in sequence over a set sampling
period, a more useful value is a modulation index. This states that for
24

each sampling period each input is switched to each output for a time
tnp , so that
mnp =
tnp
Tsamp
(3.1.7)
Taking this set of modulation indexes the modulation matrix M(t) can
be constructed such that
Vo (t) = M(t) Vi (t)
(3.1.8)
Ii (t) = MT (t) Io (t)
(3.1.9)
and
which expand to give

m Aa (t) m Ba (t) mCa (t)
VA (t)
Va (t)

Vb (t) = m Ab (t) m Bb (t) mCb (t) VB (t)
m Ac (t) m Bc (t) mCc (t)
VC (t)
Vc (t)
(3.1.10)

m Aa (t) m Ab (t) m Ac (t)
Ia ( t )
I A (t)

IB (t) = m Ba (t) m Bb (t) m Bc (t) Ib (t)
mCa (t) mCb (t) mCc (t)
Ic (t)
IC (t)
(3.1.11)
and
Once again, to satisfy the requirement that no input phase is short circuited and no output leg is open circuit
mna (t) =
n= A,B,C
mnb (t) =
n= A,B,C
mnc (t) = 1
(3.1.12)
n= A,B,C
where 0 mnp 1.
These are the basic starting assumptions on which the different modulation strategies as based.
25
3.2
Alesina/Venturini Method
This scheme is was proposed by Alesina and Venturini in 1981[5], and

it is a modulation method which allows direct control over the output
voltage and input power factor.
It states that with a given set of sinusoidal input voltages Vi (t) i, and
assuming that the output currents are also sinusoidal and given by Io (t)
vi cos(i t)
Vi (t) = vi cos(i t + 2 )
3
vi cos(i t + 4 )
3
io cos(o t + o )
Io (t) = io cos(o t + 2 + o )
3
io cos(o t + 4 + o )
3
(3.2.1)
(3.2.2)
From this a suitable modulation matrix M(t) can be determined such

that the required set of input currents Ii (t) and output voltages Vo (t)
are both sinusoidal, while also being constrained by the modulation
restriction stated in (3.1.12).
vo cos(o t)
Vo (t) = vo cos(o t + 2 )
3
vo cos(o t + 4 )
3
ii cos(i t + i )
2
Ii (t) = ii cos(i t + 3 + i )
4
ii cos(i t + 3 + i )
(3.2.3)
(3.2.4)
The solution to this the generalised equation for the modulation function
M(t) as
1 + 2qCS(0)
1
4
M ( t ) = 3 1
1 + 2qCS( 3 )
2
1 + 2qCS( 3 )
1 + 2qCA(0)
1
+ 3 2 1 + 2qCS( 2 )
3
1 + 2qCS( 4 )
3
2
1 + 2qCS( 3 )
1 + 2qCS(0)
1 + 2qCS( 4 )
3
2
1 + 2qCS( 3 )
1 + 2qCS( 4 )
3
1 + 2qCS(0)
26
1 + 2qCS( 4 )
3
2
1 + 2qCS( 3 )
1 + 2qCS(0)
4
1 + 2qCS( 3 )
1 + 2qCS(0)
1 + 2qCS( 2 )
3
(3.2.5)

where
CS( x ) = cos [ M t + x ]
CA( x ) = cos [( M + 2i )t + x ]
M = o i
1
1 = 2 [1 + tan(i ) cot(o )]
1
2 = 1 1 = 2 [1 tan(i ) cot(o )]
q = vo ,
v
i
with
1 0
2 0
1
0 q 2,
Solving the above equation gives the required modulation indices for
each of the switches, and so can be used to directly drive the converter.
There is however one problem with this method, which is shown in the
last equation, and that is the maximum voltage transfer ratio q is only
0.5, meaning that the output voltage can only be a maximum of half the
input.
3.3
Alesina/Venturini Optimum Method
To overcome the low voltage transfer ratio found in the original Alesina/Venturini method it was proposed that the transfer ratio could be increased
by adding a proportion of the third harmonic into the output frequency,
and due to the balanced nature of the loads being driven, this third
harmonic would boost the output voltage yet not feed back into the
supply side current. This method was formalised in 1989 by Alesina
and Venturini which became known as the Optimum Method[6] and
produces a voltage transfer ratio, q, of 23 or 0.866.

By using the same input voltage (3.2.1), input current (3.2.4) and output
current (3.2.2) as in the earlier method, and now requiring the output
voltage to be
27
vo cos(o t) + 1 vi cos(3i t) 1 vo cos(3o t)

4
6
Vo (t) = vo cos(o t + 2 ) + 1 vi cos(3i t) 1 vo cos(3o t) (3.3.1)

3
4
6
vo cos(o t + 4 ) + 1 vi cos(3i t) 1 vo cos(3o t)
3
4
6
Solving for the modulation matrix M(t) then gives the following from[6]:
Let Z () be a function of time dened as
Z ()(t) = cos (o + i )t +
(3.3.2)
and
1
3
1
m ( x1 , x2 , x3 , x4 , x5 , x6 ) = 1 +
p Z1 ( x1 ) + Z1 1 ( x2 )
3
2
1
1 1
Z3 ( x3 ) Z3 1( x4 )
6
6
1
7
4
2
+ sgn( p) Z0 ( x5 ) + Z0 ( x6 )
6 3
6 3
1
+ a1 Z1 ( x1 ) + a2 Z1 1( x2 )
(3.3.3)
where
tan(vi )
tan(v0 )
a = 2| | v o
vi
2 vo a
vi
p=
3
a1 = a and a2 = 0 if < 0
a1 = 0 and a2 = a if > 0
a1 = a2 = 0 if = 0,
then
m(0, 0, 0, 0, 0, 0) m(2, 4, 2, 4, 2, 4) m(4, 2, 4, 2, 4, 2)
M(t) = m(2, 2, 0, 0, 0, 0) m(4, 0, 2, 4, 2, 4) m(0, 4, 4, 2, 4, 2) (3.3.4)

m(4, 4, 0, 0, 0, 0) m(0, 2, 2, 4, 2, 4) m(2, 0, 4, 2, 4, 2)
28

Both this set of equations and the ones from previous Alesina/Venturini
method look complicated, as would be their direct implementation, however both are simplied by making the assumption that having a unity
input power is benecial. But, due to the complexities in this approach
other methods were sought out with the Space Vector Modulation method
being chief amongst them.
3.4
Space Vector Modulation
While the Space Vector representation had previously been used for inverter control it was not until Huber and Borojevic in 1989[710] where
this method was proposed for use with matrix converters. This was then
extended with a paper by Casadei at al in 2002[3, 4], giving a full Space
Vector Modulation strategy that controlled both the output voltage and
input power factor.
This space vector modulation approach to matrix converter modulation
is all based on the space vector representation of the input and output
voltages and currents at any one instant. For a 3-phase set of line-toneutral voltages this is given by
V(t) =
2
v a + avb + a2 vc
3
(3.4.1)
where
a = ej
2
3
(3.4.2)
Plotting the three vectors that make up V(t) on an Argand diagram gives
a set of 3 vectors spaced evenly 120 apart due to the a and a2 terms.
Plotting V(t) on the same diagram then produces a vector of constant
length, vo rotating about the origin at the output frequency o and with
a phase angle of o , as shown in Figure 3.1.
The basis of the Space Vector Modulation technique is that the output
voltage Vo (t), which is expressed in the above space vector form (3.4.1),
can be generated by switching between adjacent space vectors and producing a time averaged value over a switching period that is equal to
the required output space vector. This is the same technique as used in
conventional inverters but by adding in the control of the input current it
allows complete control over the operation of a matrix converter. However, instead of the 8 possible switching states of the 3-phase inverter,
29
vb
Vo
o
o
va
vc
Figure 3.1: Base set of SVM Vectors for a Balanced 3-Phase Set plotted in
the plane
there are now 27 possible switching states. This is because instead of just
switching the DC link onto the outputs, the converter has the three input
phases to use. Now, unlike with the inverter, not all of the switching
states are usable and they fall in the following three groups
Group I : Where all 3 input phases are switched to the output,
thus producing a constant amplitude vector which rotates about
the origin at the input frequency.
Group II : Where any 2 input phases are switched to the output,
meaning that two output legs are connected to the same phase.
This gives a vector of a xed angular displacement but with varying amplitude.
Group III : Where only a single phase is switched to all 3 outputs,
meaning that there is no difference in voltage between the output
legs. This gives a vector of zero length placed at the origin.
Of these three groups, only Groups II and III, which are shown in Table 3.1 are required in this method, with the rotating Group I switching
states not being used as they cannot readily be employed to generate the
required output voltages.
30

Table 3.1: 3x3 Matrix Converter Stationary and Zero Switching
Combinations
Vector
No.
+1
1
+2
2
+3
3
+4
4
+5
5
+6
6
+7
7
+8
8
+9
9
01
02
03
Leg
a
A
B
B
C
C
A
B
A
C
B
A
C
B
A
C
B
A
C
A
B
C
Leg
b
B
A
C
B
A
C
A
B
B
C
C
A
B
A
C
B
A
C
A
B
C
Leg
c
B
A
C
B
A
C
B
A
C
B
A
C
A
B
B
C
C
A
A
B
C
Vab
Vbc
Vca
VAB
VAB
VBC
VBC
VCA
VCA
VAB
VAB
VBC
VBC
VCA
VCA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VAB
VAB
VBC
VBC
VCA
VCA
VAB
VAB
VBC
VBC
VCA
VCA
0
0
0
VAB
VAB
VBC
VBC
VCA
VCA
0
0
0
0
0
0
VAB
VAB
VBC
VBC
VCA
VCA
0
0
0
In the same way as was done for the switching states for the 4-leg inverter, the switching states in Table 3.1 are then transformed into the
plane using the transform
V
V
2
3
1 1
2
3
2
1
2
3
2
Va
Vb
Vc
(3.4.3)
to give the results shown in Table 3.2.

If these vectors are now plotted in the planes, then the familiar hexagonal shape from the standard SVM used within inverters can be seen.
Figure 3.2 and 3.3 show these plots.
As stated above, this method works by identifying a set of 2 output space
vectors that need to be generated which sit either side of the required
output voltage vector. For each of these space vectors there are then
31

Table 3.2: 3x3 Matrix Converter Stationary and Zero Switching
Combinations transformed in the Plane
Vector
vo
ii
2
3 VAB
2 VAB
3
2
3 VBC
2 VBC
3
2
3 VCA
2 VCA
3
2
3 VAB
2 VAB
3
2
3 VBC
2 VBC
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3 VCA
2 VCA
3
4
3
4
3
4
3
4
3
4
3
4
3
2
ia
3
ia
23
2
ia
3
ia
23
2
ia
3
ia
23
2
ib
3
ib
23
2
ib
3
ib
23
2
ib
3
2
3 i b
2
ic
3
2
3 i c
2
ic
3
2
3 i c
2
ic
3
2
3 i c
01
02
03
No.
+1
1
+2
2
+3
3
+4
4
+5
5
+6
6
+7
7
+8
8
+9
2
3 VCA
2 VCA
3
2
3 VAB
2 VAB
3
2
3 VBC
2 VBC
3
0
0
0
0
0
2
7
6
7
6
2
7
6
7
6
2
7
6
7
6
6 switching states that can generate this output voltage vector depending on the sign of the input voltage. However, each of these switching
states generates a different input current vector, as shown in Figures 3.2
and 3.3, and it is this link between the input current and the output
voltage that allows the selection of the switching states, and thus control
over the converter. Due to the number of possible switching states it
is always possible to nd a set of 4 states that can generate the output
voltage required while also controlling the phase of the input current.
This method is set out by Casadei [3, 4] and is generated as follows.
32
4
5,
6
vo
1, 2, 3
8,
Figure 3.2: Output Voltage Vectors plotted in the plane

Figure 3.4 shows the input current and output voltage sectors which
contain their respective vectors, each with its pair of bounding space
vectors, and from this it is possible to write down the equations for the
lengths of the output voltage space vectors as
I
I
vo = vo I + vo I I I
j [ ( K v 1) + ]
2
3
3
e
= vo cos o
3
3
I
IV
vo = vo I I I I I + vo IV
2
j [ ( K v 1) ]
3
= vo cos o +
e
3
3
(3.4.4)
(3.4.5)
where I to IV are the duty cycles for the 4 switching states.

Now, from the current sector plot in Figure 3.4, the equations governing
the behaviour of the input current can be written down as
33
2, 5, 8
vi
ii
i
i
,
6
4,
Figure 3.3: Input Current Vectors plotted in the plane

9
3, + vi
+
ii
,+
+1
vo
+7
,+
+1, +3
Figure 3.4: Input Current and Output Voltage Sectors, showing the
required switching states
iiI I + iiI I I I je ji e j(Ki 1) 3 = 0
(3.4.6)
iiI I I I I I + iiIV IV je ji e j(Ki 1) 3 = 0
(3.4.7)
Solving equations (3.4.4) to (3.4.7) with respect to the duty cycles then
gives us
34
2 cos o cos i
3
q
= (1)
cos i
3
2 cos o 3 cos i +
3
I I = (1)Kv +Ki q
cos i
3
2 cos o + cos i
3
3
I I I = (1)Kv +Ki q
cos i
3
cos o + cos i +
IV
K v + Ki +1 2
3
q
= (1)
cos i
3
I
K v + Ki +1
(3.4.8)
(3.4.9)
(3.4.10)
(3.4.11)
Taking the sum of these duty cycles then gives
| I | + | I I | + | I I I | + | IV | 1
(3.4.12)
and from here it is possible to the calculate the maximum possible transfer ratio, q, as
3 | cos i |
2 cos i cos o
(3.4.13)
These equations, with those described in Section 2.1, are going to form
the basis of the derivation of space vector modulation of the 4-leg matrix
converter.
35
C HAPTER 4
Commutation Methods
As has been stated several times, there are two fundamental rules for
the operation of a matrix converter that arise from the voltage-stiff input
and current-stiff output characteristics. The rst is that no two input
phases can be shorted together and the second is that no output phase
can go open circuit. Because of these restrictions, and due to the bidirectional nature of the switches that are needed for the converter to
operate, it means that there is a problem with the two most commonly
used commutation strategies for the inverter, Overlap and Dead-time.
This chapter will rst look at the Overlap and Dead-time strategies, and
explain why neither of these is really suitable for the needs of the matrix
converter, and will then go on to look at a number of other types which
do not have the drawbacks of the rst two.
S Aa
S Aa2
S Aa1
SBa
SBa2
Load
SBa1
Figure 4.1: Segment from a Matrix Converter Circuit

Figure 4.1 shows a small portion of a matrix converter circuit which
will be used to demonstrate the various different types of commutation
36
C HAPTER 4: C OMMUTATION M ETHODS

technique. The circuit contains two bi-directional switches, SAa and SBa ,
each made up of a pair of IGBTs labelled 1 and 2, which connect two
AC voltage source to a load which contains some inductance. For each
commutation strategy there is a timing diagram showing how the IGBTs
are being switched, with a high level turning that device on, and alongside the timing diagram there is a state representation of the switching
signals. These both aim to give an easy understanding of some of the
different types of commutation that are possible.
4.1
Overlap Commutation
Overlap commutation is a relatively simple method where the incoming

devices are switched on before the outgoing devices are switched off,
and is demonstrated in Figure 4.2.
a
SAa
SBa
S Aa1
S Aa2
SBa1
SBa2
td
(a) Overlap Current Commutation Timing Diagram
a
1
1
0
0
b
0
0
1
1
1
1
1
1
S Aa1
S Aa2
SBa1
SBa2
(b) Overlap Current Commutation State Diagram
Figure 4.2: Overlap Current Commutation

As can be seen this method ensures that the output legs are always
connected, but it also means that two of the input phases are shorted
together, thus breaking the rst rule specied above. While this is acceptable for use in an inverter, where all legs are connected to the same
37

DC link voltage, this is not acceptable for the matrix converter. While it
is possible to overcome the problem caused by shorting the input phases
by the inclusion of large inductors on the input lines to limit the rise
in input currents from shorting the phases together, it is not a favoured
solution as these inductors will not only need to be large, they will also
be expensive and heavy, and so remove one of the advantages of matrix
converters, that of being compact and an all silicon solution.
4.2
Dead-time Commutation
Dead-time commutation is also relatively simple, and can almost be seen

as the opposite of overlap commutation, in that instead of switching the
incoming device on before turning the outgoing device off, this method
turns off the outgoing device before turning on the incoming one, thus
giving a dead-time between conducting devices.
a
SAa
SBa
S Aa1
S Aa2
SBa1
SBa2
td
(a) Deadtime Current Commutation Timing Diagram
a
1
1
0
0
b
0
0
1
1
0
0
0
0
S Aa1
S Aa2
SBa1
SBa2
(b) Deadtime Current Commutation State Diagram
Figure 4.3: Deadtime Current Commutation

This is shown in Figure 4.3, and as can be seen means that when switching, unlike with Overlap commutation the input phases are never shorted
together, however the output legs are now allowed to go open circuit,
38

breaking the second of the rules for matrix converter operation as specied above. As before, there is a way to mitigate the problems associated with this method, and that is to use snubber circuits around each
switch to allow the current to continue owing in the output leg while
the switching is occurring. However, as for the Overlap commutation
before, one of the advantages of the matrix converter are that they are
compact and all silicon, and this would be compromised by adding high
capacity snubber networks using capacitors, and so this method is not
used.
4.3
4-Step Commutation
The 4-Step commutation process was one of the rst methods proposed
that allowed the matrix converter to be successfully switched between
states without violating either of the two rules dened above for their
operation. However, for this approach to work it requires a bi-directional
switch which can independently control the conduction path in each
direction, this is the example that is shown in Figure 4.1 above. As its
name suggests, unlike the previous two methods this method uses four
individual steps and this sequence is demonstrated in Figure 4.4
The rst step is for the non-conducting device in the outgoing switch to
be turned off( a). Then in the incoming switch, the device which will be
conducting is switched on(b). This can happen without creating a short
circuit between the two input phases because both switches are only
being turned on in one direction only, and both in the same direction
as the current ow, so the short circuit is not possible due to the series
diodes in the bi-directional switch. At this point it is then possible to
turn off the conducting device in the outgoing switch(c), turning off that
bi-directional switch entirely. The nal step, once the outgoing device
is completely turned off, is then for the non-conducting device in the
incoming switch to be turned on(d).
Unlike the 2-step commutation processes above, which only need to
know which switches are involved, this technique also needs to know
the current direction within the switch. This is important as it is the current direction within the bi-directional switch that denes which order
the devices are switched, and this is simple to achieve at higher currents
using hall effect sensors on the output legs. However there is a problem
using the hall effect sensors at very low currents, but at these current
levels, while not ideal, it would be possible to switch to a dead-time
39

a
SAa
SBa
S Aa1
S Aa2
SBa1
SBa2
td
(a) Four-Step Current Commutation Timing Diagram
b
1
0
0
0
IL < 0
c
1
0
1
0
d
0
0
1
0
1
1
0
0
IL > 0
0
0
1
1
0
1
0
0
0
1
0
1
S Aa1
S Aa2
SBa1
SBa2
0
0
0
1
(b) Four-Step Current Commutation State Diagram
Figure 4.4: Four-Step Current Commutation

commutation arrangement as long as an adequate voltage clamp circuit
was placed on the outputs. This circuit would have to be far smaller
than that needed if performing dead-time commutation all the time due
to this only being used at low levels of current.
4.4
Threshold 2-Step Current Commutation
As can be seen in the four-step commutation process above, at the required switching instant the rst and last steps do not really appear to
achieve much as neither of the devices are conducting, and they just slow
down the overall switching process as the incoming device only gets
turned on td after the switching process has started. To allow for this the
threshold 2-step commutation process was derived. It is essentially as
the four-step process except that it only ever turns on the conducting ele40

ments in the switch, keeping the non-conducting elements turned off until the current direction changes. This means that to commutate between
input phases the method only needs to turn on the incoming switches
conducting element followed by turning off the outgoing switch and the
method is shown in Figure 4.5.
a
SAa
SBa
S Aa1
S Aa2
SBa1
SBa2
td
(a) Threshold 2-step Current Commutation Timing Diagram
a
1
0
0
0
IL < 0
IL 0
IL > 0
b
1
0
1
0
0
0
1
0
1
1
0
0
0
0
1
1
0
1
0
0
0
1
0
1
S Aa1
S Aa2
SBa1
SBa2
0
0
0
1
(b) Threshold 2-step Current Commutation State Diagram
Figure 4.5: Threshold 2-Step Current Commutation

While this appears to have an advantage over the 4-step method in its
simplicity with only having to turn one device on and turn off another,
just as in the overlap method, it does mean however that the gate drive
circuits themselves need to be aware at all times what the current direction is, and be able to turn on the other device if the current direction
changes. As with the four-step process, the current detection is simple at
high currents using hall effect sensors, but once again there is a problem
at lower currents.
41

With the inability to accurately detect low current levels, this leads to
two problems. The rst is the same as that seen in the four-step technique, in that for commutation to occur correctly, the current direction
needs to be known. As with the four-step commutation, this can be
overcome by using dead-time commutation for the range of currents
where the hall effect sensor is inaccurate, as shown in Figure 4.6, along
with placing a voltage clamp circuit on the output.
a
1
0
0
0
IL < 0
IL 0
IL > 0
1
1
0
0
b
1
0
1
0
0
0
1
0
0
0
1
1
0
0
0
0
0
1
0
0
0
1
0
1
S Aa1
S Aa2
SBa1
SBa2
0
0
0
1
Figure 4.6: Threshold 2-Step with Low Current Deadtime Commutation

The second problem is that outside of any commutation between input
phases, the gate drive needs to ensure that the correct device is turned
on within the bi-directional switch so that normal current can ow. This
problem is overcome by setting a threshold level, below which the gate
drive turns on both devices within the switch, thus ensuring that the
switch is able to conduct no matter which direction the current ow is
in. Once the current level has risen once again to a level where the hall
effect sensors are accurate, then the gate drive circuit will switch off the
non-conducting device within the switch.
With these extra requirements over that of the four-step commutation
process, it means that the gate drive circuit needs to be more complex.
4.5
Voltage Sensed Current Commutation
As a solution to the current detection problem with the four-step, and

its derived 2-step, technique, a method was developed at Nottingham
University[33] that allowed the detection of the input current direction
42

even at very low levels. This was achieved by measuring, and comparing, the voltage drop across different parts of the switch, as shown in
Figure 4.7.
vy
vx
Figure 4.7: Current Direction Detection using Voltage drops in a

bi-directional Switch
If the switch is conducting in one direction, where the current is owing
from the left to the right, then the voltage drop across the conducting
IGBT, vy , will be positive with respect to the mid-point and the voltage
across the conducting diode, v x will be negative with respect to the midpoint. If the current direction changes, then so will the polarity of the
voltages and this is easily detected by a comparator circuit and this information used for the commutation. By using this technique it is possible
to accurately detect the current direction down to very small currents.
Because of the highly accurate nature of the current direction measurement, this allowed the derivation of this commutation method from the
2-step process above, in which there is only ever a maximum of a single
device turned on within a bi-directional switch at one time, as shown in
Figure4.8
43
SAa
SBa
S Aa1
S Aa2
SBa1
SBa2
td
(a) Voltage Sensed Current Commutation Timing Diagram
a
1
0
0
0
IL < 0
IL 0
IL > 0
b
1
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
1
S Aa1
S Aa2
SBa1
SBa2
0
0
0
1
(b) Voltage Sensed Commutation State Diagram
Figure 4.8: Voltage Sensed Current Commutation
44
C HAPTER 5
Derivation of the Space Vector

Modulation technique for the
4-leg Matrix Converter
As has been shown previously, all Space Vector Modulation SVM techniques are based around the idea that you can represent the input and
output voltages of a converter by a set of vectors within specic input
and output coordinate systems. By then dening the relationship between these two sets of vectors, this is used to dene a set of switching
states for the converter that will allow both the output voltage and input
current requirements to be satised. At any one point in time these
vectors are dened completely by the instantaneous voltages at both the
inputs and outputs of the converter.
It has previously been shown in Sections 2.1 and 3.4 how this has been
achieved for both the 4-leg inverter and the 3x3 matrix converter respectively, and the derivation of the technique for the 4-leg matrix converter
draws from both of these techniques and so develops along similar lines.
The technique will Initially dene the input voltage, followed by the
3-dimensional output voltage space. From this it will lead on to the
specication of the different switching states, which in turn allows the
denition of the generated space vectors. Once these space vectors have
been dened, it will then be possible to show the link between the input and output spaces, which will show how the converter will be able
to operate. The derivation of the duty cycles for each of the required
switching states will then be performed, before nally looking at the
possible voltage transfer ratio for this modulation strategy.
45
C HAPTER 5: D ERIVATION OF THE S PACE V ECTOR M ODULATION

TECHNIQUE FOR THE 4- LEG M ATRIX C ONVERTER
5.1
The Input Voltage Plane
Looking at the diagram in Figure 1.6, it shows the basic layout of the
4-leg matrix converter. From this it can be seen that while there are 4
output legs to the converter, there are only 3 input legs, so while the
output is capable of generating an unbalanced set of phase voltages, the
input must form a balanced three phase set as dened by
VA + VB + VC = 0
(5.1.1)
where each of the input phase voltages is dened by
VA = Vi cos (i )
(5.1.2)
2
3
4
VC = Vi cos i
3
VB = Vi cos i
(5.1.3)
(5.1.4)
where Vi is the phase input voltage, and i is the phase of the input
voltage at a particular instant in time. An example set of input voltages
are also shown in Figure 5.1(a).
In the same way as for the 3x3 matrix converter, this set of input voltages
can be represented as a space vector by using the following well known
-transform
V
V
2
3
1
0
1
2
3
2
1
2
23
VA
VB
VC
(5.1.5)
This equation (5.1.5) takes the three input phase voltages and calculates
the values V and V , which can be plotted as a vector vi in the plane.
Figure 5.1(c) shows an example where vi has been plotted for the input
voltages shown in Figure 5.1(b).
As the input is a balanced 3-phase set this vector will be of a constant
amplitude, |vi |, and rotate around the origin at the input frequency, i .
Using equations (5.1.1) and (5.1.5) it is possible to write down three
primary voltage space vectors which relate to the three input phase voltages, and there are labelled as Av , Bv , Cv , such that
46

400
300
VA
200
100
VC
Vin 0
-100
-200
-300
-400
VB
0
10 12 14 16 18 20
time (ms)
(a) 3-Phase Input Voltage
V (240)
V (240)
2
3
1
2
3
2
1
0
1
2
23
VA (240)
VB (328)
VC (88)
(b) Transform
Bv
Av
VA
VC
VB
Vi
Cv
(c) Input Space showing the example from (b)
Figure 5.1: Input space showing the 3 primary input voltage vectors
47

Av =
2
3
1
0
Bv =
2
3
1
2
3
2
Cv =
2
3
1
2
23
(5.1.6)
These three vectors can be seen plotted in Figure 5.1(c), and are the three
vectors spaced evenly 120 about the origin.
5.2
The Input Current Plane
In exactly the same way as for the input voltage plane shown above, the
input currents, I A , IB and IC , can also be transformed into the space
using the same transform as the input voltage, so
I
I
2
3
1
2
3
2
1
2
23
IA
IB
IC
(5.2.1)
As for the voltages above, the values I and I can be plotted to produce
an input current space vector, ii , in the space whose magnitude, |ii |,
and phase, i , are determined by the operation of the converter and by
the load. However, the converter is being designed to achieve a unity
input displacement factor which means that the fundamental frequency
of the input current should be in phase with the fundamental frequency
of the input voltage. In this case the phase angle of the input current
space vector will always match that of the input voltage vector, and so
will rotate around the origin at the input voltage frequency, i .
Therefore, as the input voltage vector was formed by a balanced 3-phase
set, and the input current vector rotates in phase with the resultant voltage vector, then then at any one instant the input currents must also form
a balanced 3-phase set such that
I A + IB + IC = 0
(5.2.2)
From equation (5.2.2) and using equation (5.2.1), the three primary current space vectors, Ai , Bi , Ci relating to the current in each input phase
can be written down as
Ai =
2
3
1
0
Bi =
2
3
1
2
3
2
48
Ci =
2
3
1
2
23
(5.2.3)

Bi
IA
i
IC
IB
Ai
ii
Ci
Figure 5.2: Input space showing the 3 primary input current vectors
Figure 5.2 shows the input current plane, with these three primary
current vectors plotted, these are the three vectors spaced evenly 120
about the origin, and are the same as for the input voltage. Also shown
is the direction of the desired input current vector ii for the example
shown in Figure 5.1.
5.3
The Output Voltage Space
The 3x3 matrix converter produces 3 different output voltages, but because these voltages are all referenced to each another, and form a balanced set, they are constrained by the following equation
Va + Vb + Vc = 0
(5.3.1)
So while there are three different variables, Va , Vb and Vc , they are all related to one another and so this actually only gives 2 degrees of freedom.
This means that it is only possible to independently set 2 out of 3 of the
output voltages, with the third being set by the solution to equation 5.3.1.
With the 4-leg matrix converter, which is able to produce 4 different output voltages, once again all the voltages are referenced to one another,
but are now constrained by
49

Va + Vb + Vc + Vn = 0
(5.3.2)
Because there are now four different variables, Va , Vb , Vc and Vn , in the

same way as before, this now gives 3 degrees of freedom. So this means
it is possible to independently set each of the 3 phase voltages, Va , Vb and
Vc , while the fourth, Vn , will be set by the solution to equation (5.3.2).
So, unlike with the 3x3 matrix converter, the 4-leg matrix converter is
able to independently control each of the 3 phase outputs with respect to
the voltage generated by the neutral leg, and so allow an unbalanced set
of 3-phase voltages to be demanded. This means that the three output
phase voltages can have any value, and are not constrained by equation (5.3.1), so
Va + Vb + Vc = 0
(5.3.3)
Due to this extra degree of freedom required by equation (5.3.2), the

two dimensional space used for the input voltage is just not able to
dene a unique space vector resulting from all 4 output legs and so a
three dimensional output space is required. This is dened as the
space[12], and is the same as that described for the 4-leg inverter in
Section 2.1. The output voltage space vector is then generated using
X = 0
3
X
2 2
1
2
3
2
1
2 2
1
2
3
2
2 2
Va
V
b
0
Vc
2 2
Vn
0
(5.3.4)
This transform takes the required instantaneous output voltages, Va Vb ,

Vc and Vn , and generates a single space vector that can be plotted in
the space as shown in Figure 5.3(c). An example transformation is
shown in Figure 5.3(b).
In a similar way to the input voltage space above, if the four output space
vectors relating to the four output legs are labelled a, b, c, n, then using
equation (5.3.2) the following equation can be written down
a+b+c+n = 0
(5.3.5)
Using the transform in equation (5.3.4) the four space vectors repre-
50

400
300
200
100
0
-100
-200
-300
-400
10 12 14 16 18 20
(a) 4-Phase Output Voltage
X (120)
X (120) =
X (0)
2
3
2 2
1
2
3
2
1
2 2
V (120)
a
0
Vb (164)
0
Vc (44)
3
2 2
Vn (0)
1
2
23
1
2 2
(b) Transform
c
Vc
Va
Vb
Vd
n
(c) Output Space showing the example from (b)
Figure 5.3: Output space showing the 4 primary output voltage

vectors
51

senting the output legs are
2
a= 3 0 b=
2 2
2
3
1
2
3
2
1
2 2
c=
2
3
1
2
23
1
2 2
n=
2
3
0
0
3
22
(5.3.6)
These are the four primary output vectors, and are also plotted on Figure 5.3(c) where it can be seen that, in a similar way to the input voltage
space vectors before, these are all equidistant from one another within
the space.
It should be noted that between the two papers which were used as
the source for the 3-dimensional space vector modulation that is used
in this derivation, there are a couple of differences with this transform
matrix. The rst being that Ryan, Lorenz and De Doncker[12] use the
Tdqo notation more commonly used for a rotating frame of reference,
while Zhang[14] uses the static notation. The notation which
was chosen for this derivation as the vector space does not move, and
the static frame of reference was thought to be preferable.
The second difference being the values used for the row in the trans
form matrix, with Ryan, Lorenz and De Doncker[12] using 1/(2 2) and
Zhang[14] using 1/2. The value used in this row determines the range
of possible values that can take, and for this derivation of the 4-leg
matrix converter, the value of 1/(2 2) was chosen because this means that
the 4 primary vectors, a, b, c and n, are all the same length. This is not
the case with the values used by Zhang. While this is not a problem
with the forms of the solution proposed by Zhang for the 4-leg inverter,
it was found that having the primary vectors of the same length was
advantageous for the 4-leg matrix converter.
5.4
The Switching States
Now that the input and output spaces have been initially set out, and
the primary space vectors in each area dened, the next stage in the
derivation of the 4-leg matrix converter is to ascertain the complete set
of switching states that are possible. These switching states are those
which obey the fundamental rules for any matrix converter, that two
input phases cannot be shorted together, and no output leg can be open
52

circuit. For the standard 3x3 matrix converter it has been shown that
there are 27 (33 ) possible switching states[4]. However, the addition of
the fourth output leg increases the total number of combinations for the
3x4 matrix converter to 81 (34 ). All of these switching states are shown
in Tables 5.1 and 5.2.
a+b
b+c
c+a
Figure 5.4: 3x3 Matrix Converter stationary vectors

As with the 3x3 converter [4], not all of these possible switching states
are useful for Space Vector Modulation, and so only those that produce
a vector with a constant direction within the output space are to be used,
and these are called the stationary vectors. The switching states of any
3-input matrix converter can be broken down into three distinct groups
Group I : Those that connect all three input phases to the output.
These switching states, which are all are shown in Table 5.1, are
those states that connect to all three of the input phases. As all of
the output legs have to be switched to an input phase this means
that two different line-to-line voltages must be present on the output legs. These line-to-line voltages that are generated change independently of each other meaning that the resultant vector created at the output legs is not only changing in magnitude, but
will also changing direction as well. These are the set of rotating
vectors which, as with the standard 3x3 matrix converter space
vector modulation, are not used within this method.
Group II : Those that connect any two input phases to the output.
53

Table 5.1: Rotating Switching States for the 4-Leg Matrix Converter
Rotating
Vectors
Output Leg Switching Vvector

Leg a Leg b Leg c Leg n
A
A
B
C
A
B
A
C
B
A
A
C
B
B
A
C
B
A
B
C
A
B
B
C
A
A
C
B
A
C
A
B
C
A
A
B
C
C
A
B
C
A
C
B
A
C
C
B
B
B
C
A
B
C
B
A
C
B
B
A
C
C
B
A
C
B
C
A
B
C
C
A
A
B
B
C
C
A
A
B
B
C
C
A
A
B
B
C
C
A
B
A
C
B
A
C
B
A
C
B
A
C
B
A
C
B
A
C
C
C
A
A
B
B
C
C
A
A
B
B
C
C
A
A
B
B
A
A
A
A
A
A
B
B
B
B
B
B
C
C
C
C
C
C
L-N Output Voltage Ivector

Van Vbn
Vcn
-VCA -VCA VBC
-VCA VBC -VCA
VBC -VCA -VCA
VBC VBC -VCA
VBC -VCA VBC
-VCA VBC
VBC
V AB V AB -VBC
V AB -VBC V AB
-VBC V AB
V AB
-VBC -VBC V AB
-VBC V AB -VBC
V AB -VBC -VBC
-V AB -V AB VCA
-V AB VCA -V AB
VCA -V AB -V AB
VCA VCA -V AB
VCA -V AB VCA
-V AB VCA VCA
0
-V AB
-V AB
VCA
VCA
0
V AB
0
0
-VBC
-VBC
V AB
-VCA
VBC
VBC
0
0
-VCA
54
-V AB
0
VCA
-V AB
0
VCA
0
V AB
-VBC
0
V AB
-VBC
VBC
-VCA
0
VBC
-VCA
0
VCA
VCA
0
0
-V AB
-V AB
-VBC
-VBC
V AB
V AB
0
0
0
0
-VCA
-VCA
VBC
VBC
Input Current
IA
IB
IC
Ia +Ib
Ic
-Ia -Ib -Ic
Ia +Ic
Ib
-Ia -Ib -Ic
Ib +Ic
Ia
-Ia -Ib -Ic
Ic
Ia +Ib -Ia -Ib -Ic
Ib
Ia +Ic -Ia -Ib -Ic
Ia
Ib +Ic -Ia -Ib -Ic
Ia +Ib -Ia -Ib -Ic
Ic
Ia +Ic -Ia -Ib -Ic
Ib
Ib +Ic -Ia -Ib -Ic
Ia
Ic
-Ia -Ib -Ic Ia +Ib
Ib
-Ia -Ib -Ic Ia +Ic
Ia
-Ia -Ib -Ic Ib +Ic
-Ia -Ib -Ic Ia +Ib
Ic
-Ia -Ib -Ic Ia +Ic
Ib
-Ia -Ib -Ic Ib +Ic
Ia
-Ia -Ib -Ic
Ic
Ia +Ib
-Ia -Ib -Ic
Ib
Ia +Ic
-Ia -Ib -Ic
Ia
Ib +Ic
-Ib -Ic
-Ia -Ic
-Ia -Ib
-Ia -Ib
-Ia -Ic
-Ib -Ic
Ia
Ib
Ic
Ic
Ib
Ia
Ia
Ib
Ic
Ic
Ib
Ia
Ib
Ia
Ia
Ib
Ic
Ic
-Ia -Ic
-Ib -Ic
-Ib -Ic
-Ia -Ic
-Ia -Ib
-Ia -Ib
Ib
Ia
Ia
Ib
Ic
Ic
Ic
Ic
Ib
Ia
Ia
Ib
Ic
Ic
Ib
Ia
Ia
Ib
-Ia -Ib
-Ia -Ib
-Ia -Ic
-Ib -Ic
-Ib -Ic
-Ia -Ic

These states, which connect any two of the input phases to the outputs are the main ones that are of interest as these are the ones that
generate the stationary vectors. With only two of the input phases
are connected through to the output legs at any one time, and with
all the output legs needing to be connected to an input phase, the
output legs must be connected to one or other of these two phases.
From this it can be seen that the only output voltages that can be
generated on the outputs are either zero, or the line-to-line voltage
between the two connected phases. Even though this line-to-line
voltage can be generated on more than one output leg, because all
of the voltages are the same, the resultant vector, even if changing
in magnitude, will always have a xed angle within the output
space. This is true no matter which input phases are switched.
This was also true for the 3x3 matrix converter, where this generates the set of 6 vectors evenly spaced around the zero point,
giving the well known hexagonal plot. In this case, for the 4-leg
matrix converter, this generates a set of constant vectors within a
three dimensional output space as shown in Figure 5.5. These
vectors can be seen in Table 5.2 marked as the Stationary Vectors.
Group III : Those that connect a single input phase to the outputs.
These are the states which connect to all four output legs to a single
input phase can only ever produce a zero vector at the outputs.
With only a single input phase connected through to the output
legs, and once again, with all the output legs needing to be connected to an input phase, the output legs can only be connected to
that single phase. As they are all now connected to the same input
phase, the voltage between them will therefore be zero. These
vectors are important as they allow a zero state to be applied to the
output while also maintaining the validity of equation ref4 phase
balanced output voltage sum, and without using these states it
would not be possible to otherwise generate a zero state without
disconnecting the output legs from the input phases. These vectors
can be seen at the top of Table 5.2 marked as the Zero Vectors.
55

Table 5.2: Stationary and Zero Switching States for the 4-Leg Matrix
Converter
Zero
Vectors
Switching Output Leg Switching Vvector L-N Output Voltage Ivector

State
Leg a Leg b Leg c Leg n
Van Vbn
Vcn
0A
A
A
A
A
ZA
0
0
0
0B
B
B
B
B
ZB
0
0
0
0C
C
C
C
C
ZC
0
0
0
IA
0
0
0
Input Current
IB
0
0
0
IC
0
0
0
+1
-1
+2
-2
+3
-3
B
A
C
B
A
C
B
A
C
B
A
C
B
A
C
B
A
C
V8
V7
V8
V7
V8
V7
V AB
-V AB
VBC
-VBC
VCA
-VCA
0
0
0
0
0
0
0
0
0
0
0
0
I6
I3
I2
I5
I4
I1
Ia
-Ia
0
0
-Ia
Ia
-Ia
Ia
Ia
-Ia
0
0
0
0
-Ia
Ia
Ia
-Ia
+4
-4
+5
-5
+6
-6
B
A
C
B
A
C
A
B
B
C
C
A
B
A
C
B
A
C
B
A
C
B
A
C
V4
V11
V4
V11
V4
V11
0
0
0
0
0
0
V AB
-V AB
VBC
-VBC
VCA
-VCA
0
0
0
0
0
0
I6
I3
I2
I5
I4
I1
Ib
-Ib
0
0
-Ib
Ib
-Ib
Ib
Ib
-Ib
0
0
0
0
-Ib
Ib
Ib
-Ib
+7
-7
+8
-8
+9
-9
Stationary
Vectors
A
B
B
C
C
A
B
A
C
B
A
C
B
A
C
B
A
C
A
B
B
C
C
A
B
A
C
B
A
C
V2
V13
V2
V13
V2
V13
0
0
0
0
0
0
0
0
0
0
0
0
V AB
-V AB
VBC
-VBC
VCA
-VCA
I6
I3
I2
I5
I4
I1
Ic
-Ic
0
0
-Ic
Ic
-Ic
Ic
Ic
-Ic
0
0
0
0
-Ic
Ic
Ic
-Ic
+10
-10
+11
-11
+12
-12
A
B
B
C
C
A
A
B
B
C
C
A
B
A
C
B
A
C
B
A
C
B
A
C
V12
V3
V12
V3
V12
V3
V AB
-V AB
VBC
-VBC
VCA
-VCA
V AB
-V AB
VBC
-VBC
VCA
-VCA
0
0
0
0
0
0
I6
I3
I2
I5
I4
I1
Ia +Ib
-Ia -Ib
0
0
-Ia -Ib
Ia +Ib
-Ia -Ib
Ia +Ib
Ia +Ib
-Ia -Ib
0
0
0
0
-Ia -Ib
Ia +Ib
Ia +Ib
-Ia -Ib
+13
-13
+14
-14
+15
-15
B
A
C
B
A
C
A
B
B
C
C
A
A
B
B
C
C
A
B
A
C
B
A
C
V6
V9
V6
V9
V6
V9
0
0
0
0
0
0
V AB
-V AB
VBC
-VBC
VCA
-VCA
V AB
-V AB
VBC
-VBC
VCA
-VCA
I6
I3
I2
I5
I4
I1
Ib +Ic
-Ib -Ic
0
0
-Ib -Ic
Ib +Ic
-Ib -Ic
Ib +Ic
Ib +Ic
-Ib -Ic
0
0
0
0
-Ib -Ic
Ib +Ic
Ib +Ic
-Ib -Ic
+16
-16
+17
-17
+18
-18
A
B
B
C
C
A
B
A
C
B
A
C
A
B
B
C
C
A
B
A
C
B
A
C
V10
V5
V10
V5
V10
V5
V AB
-V AB
VBC
-VBC
VCA
-VCA
0
0
0
0
0
0
V AB
-V AB
VBC
-VBC
VCA
-VCA
I6
I3
I2
I5
I4
I1
Ia +Ic
-Ia -Ic
0
0
-Ia -Ic
Ia +Ic
-Ia -Ic
Ia +Ic
Ia +Ic
-Ia -Ic
0
0
0
0
-Ia -Ic
Ia +Ic
Ia +Ic
-Ia -Ic
+19
-19
+20
-20
+21
-21
A
B
B
C
C
A
A
B
B
C
C
A
A
B
B
C
C
A
B
A
C
B
A
C
V14
V1
V14
V1
V14
V1
V AB
-V AB
VBC
-VBC
VCA
-VCA
V AB
-V AB
VBC
-VBC
VCA
-VCA
V AB
-V AB
VBC
-VBC
VCA
-VCA
I6
I3
I2
I5
I4
I1
Ia +Ib +Ic
-Ia -Ib -Ic
0
0
-Ia -Ib -Ic
Ia +Ib +Ic
-Ia -Ib -Ic

Ia +Ib +Ic
Ia +Ib +Ic
-Ia -Ib -Ic
0
0
0
0
-Ia -Ib -Ic
Ia +Ib +Ic
Ia +Ib +Ic
-Ia -Ib -Ic
56

Figure 5.5: Stationary vectors plotted in space
5.4.1
Output Voltage and Switching States
Now, each of the switching states within Table 5.2 denes a particular
space vector within the space, and are shown plotted in Figure 5.5.
So, if switching state +1 from Table 5.2 is examined, it can be seen that input phase A is switched to output leg a, while input phase B is switched
to the remaining output legs bcn. Looking at the output voltages it is
easy to see that this gives
Va = VA
Vb = VB
Vc = VB
Vn = VB
Transforming this into the space using (5.3.4) gives
57
(5.4.1)

1
2
Vo = 0
3
2 2
1
2
3
2
1
2 2
VA
0
1
V
B
2
= VAB 0
0
3
VB
3
1
2 2
2 2
VB
1
2
23
1
2 2
(5.4.2)
This same result can also be achieved using the primary voltage vectors
as set out in equation (5.3.6), where a is
a = VA 0
3
(5.4.3)
2 2
and then b + c + n gives
b + c + n = 2 VB
3
1
2
3
2
1
2 2
2
+ 3 VB
1
2
3
2
1
2 2
0
1
+ 3 VB 0 = 2 VB 0
3
2 2
2 2
(5.4.4)
As can be seen, this is a vector in the opposite direction to a with magnitude VB . The resultant space vector for this switching state is the sum of
the two vectors which is
2
2
3 VA 0 + 3 VB
2 2
1
0
1
22
2
= 3 VAB 0
(5.4.5)
2 2
and gives a vector in the direction of a with a magnitude of VAB , and is

the same result as shown in equation (5.4.2).
Now, if the values 8, 4, 2, 1 are assigned to the primary space vectors
dening the output legs (a, b, c, n), the above gives
58

a=8
b+c+n = 4+2+1 = 7
(5.4.6)
and, as noted above, the vector generated by b + c + n is the opposite

of a and so can be considered to be part of a pair, one vector being the
inverse of the other. If the values assigned the two vectors in this pair
are then added together, the result equals 15.
In the same way, each of the other space vectors can be generated by
the addition of 2 or more of the 4 primary vectors. If this is done for
all combinations of the four primary space vectors, that give stationary
vectors from Table 5.2, this results in a total of 10 extra vectors, giving
a total of 14 space vectors. Each vector has a unique value of 1 to 14
generated by adding together the values assigned to the primary vectors,
and each vector having an inverse that it is paired with. Just as with
the example above, if the two values associated with the vector pair are
added together, the result is always 15. This lead to the vectors being
labelled with their assigned numbers, so for example a is V8 and b +
c + n is V7. Figure 5.6 shows these 14 vectors plotted in space.
Looking once again at Table 5.2, it can be seen that the switching states
that produce these vectors have all been labelled as positive/negative
pairs(eg. 1), one being the inverse of the other. This is because each of
these pairs of switching states generates a corresponding pair of space
vectors that, like the switching states, are the inverse of each other. For
example, switching state +1 generates the voltage space vector V8, while
switching state 1 generates the opposite space vector V7.
It should also be noted that this single pair of switching states is not
unique in generating this pair of voltage space vectors. Looking at Table 5.2 shows that for each pair of output voltage space vectors there
are three pairs of switching states that can be used to generate it. Each
of these different switching state pairs produces the space vector using
a different pair of input phases. It is this the symmetry between the
switching states and the output space vectors which means that at any
given point in the input voltage cycle, there will be a set of switching
states that can create any required output voltage space vector.
59

V14
1/sqrt2
V6
V12
V4
2/3sqrt2
V10
1/3sqrt2
V2
V8
0
V7
V13
V5
-1/3sqrt2
V11
V3
-2/3sqrt2
V9
-1/sqrt2
V1
Figure 5.6: Stationary vectors plotted in space
5.4.2
Input Current and Switching States
Now looking at the input current, and in a similar way to above, if

switching state +1 is once again examined it can be seen that only two
input phases are used, VA and VB , so no current ows in the third phase,
VC . Also, as only a single output leg is switched to VA , with the other
output legs switched to VB the only current owing is that from output
leg a, also taking into account equation (5.2.2) then
I6 = Ia .Ai + ( Ia ).Bi
substituting in from (5.2.3) gives
60
(5.4.7)

2
I6 = Ia
3
1
0
2
Ia
3
1
2
3
2
I6 = Ia
(5.4.8)
1
3
2
which denes a space vector with magnitude Ia and a xed phase
3
displacement of . If this process is repeated for each of the switching
6
states, as seen in the right-hand columns in Table 5.2, it can be seen that
the input current only has six space vectors, labelled I1 to I6, and that
each can be generated using any of seven switching states. These vectors
can be seen plotted in the space in Figure 5.7, and it can be seen that
although the hexagonal shape made by the vectors is the same, with an
angle of between each vector, the overall space has been rotated by
3
6
to that seen in Figure 5.4.
I2
I3
Bi
I1
Ai
I4
I6
Ci
I5
Figure 5.7: Stationary Current vectors plotted in space
As with the voltage vectors above, this means that there will always be a
set of switching states that can be used to generate any particular input
current space vector irrespective of the required output space vector. It
is this ability to decouple the input vectors from the output vectors that
61

allows the independent control of both output voltage and input current
phase[4].
5.5
Determining the output sector
With all the input and output vectors now dened in terms of the available switching states, the next stage is to identify which of these vectors
is required generate the demanded output voltage. This is initially done
by calculating which input and output sectors the input current and
output voltage vectors reside within.
Looking at the output rst, which as previously stated has four output
legs and is transformed using equation (5.3.4) into a three-dimensional
() space as shown in Figure 5.6. From Table 5.2, and as shown in Section 5.4.1, there are fourteen xed space vectors describing this volume[11,
12, 14]. On closer inspection it can be seen that this volume is actually
a superset of the two-dimensional plane, which can be seen in Figure 5.8 where the space is projected on the plane[11] by looking
along the axis.
Figure 5.8: Projection of the Vector Space onto the plane

In Figure 5.8 there can be seen two areas which are shaded red. These
62

show a prism taken from the switching volume in space and made
up from two rows of adjacent switching vectors along its boundaries,
and as can be seen, this prism corresponds to a sector in the plane.
Now looking back at Figure 5.5, the prism is shown as the lighter blue
shaded area, while the darker red shaded area in this gure shows the
smallest possible bounded volume for the output voltage space. This
is a tetrahedron bounded by three of the stationary space vectors at its
vertices, and this tetrahedron is one of four stacked on top of one another
that makes up a single prism. Figure 5.9 shows how the tetrahedrons t
together to form a single prism.
Figure 5.9: Exploded Diagram of how the Tetrahedrons make up a

Prism
The way that four tetrahedrons t together to form a single prism, and
then project as a single sector into the plane means that it is relatively
simple to calculate which prism the output voltage vector sits within, the
harder part however, is to calculate which one of the 4 tetrahedrons it
lies within, although this is been simplied greatly by using the method
found by Zhangl[14].
So, if we take a set of output demand voltages, Vd , and using the example
given in Figure 5.3(b), it can be dened as
63

Va (120)
Vb (164)
Vd =
Vc (44)
Vn (0)
(5.5.1)
and transform this set into the three-dimensional space by using

(5.3.4), giving the following result
X (120)
X (120)
X (0)
= 0
3
2 2
1
2
3
2
1
2 2
Va (120)
V (164)
b
Vc (44)
Vn (0)
1
2
3
2
2 2
(5.5.2)
As has been stated previously in this section, and shown in Figure 5.8,
by looking along the -axis this three-dimensional space can be seen
projected on the plane. This projection is in the same form as the input
voltage plane, and as such can be seen to be made up of six sectors. By
comparing (5.1.5) and (5.3.4), and ignoring the third dimension in (5.3.4),
the transforms are then identical. This allows the output voltage vector
to be easily converted into the 2-dimensional plane by ignoring the
axis, and from here it is trivial to calculate the phase angle in this plane
by using equation (5.5.3) below, which species which prism the output
voltage vector lies within.
1,
2,
3,
Prismo =
4,
5,
6,
for 0 <
for
for
3
< 2
3
3
2
3
<
4
3
< 5
3
for <
for
for
4
3
5
3
(5.5.3)
< 0
where is the phase angle of the output voltage in the plane.

So, using the values dened in equation (5.5.1) and ignoring , the phase
of the demand vector in the plane can be calculated by
64

= arctan
X
X
= arctan
140
140
=
4
4
(5.5.4)
Taking this result and comparing it with (5.5.3), it can be seen that this
output demand voltage lies within Prism 6.
Once the prism has been determined, the exact tetrahedron containing
the demand vector needs to be found. This is achieved by using a method
rst described by Zhang[14], where the tetrahedron is found using a
lookup table, and the one required for the 4-leg matrix converter is shown
in Table 5.3. Along with specifying which tetrahedron the demand vector lies within, this table also gives the three output space vectors which
make up the vertices of that tetrahedron, and these are the space vectors
required to be able to create any demand vector within that tetrahedron.
Table 5.3: Tetrahedron Lookup Table
Tetrahedron
1
3
Prism
4
Vectors
V1
V9
V13
Vectors
V1
V5
V13
Vectors
V1
V5
V7
Vectors
V1
V3
V7
Vectors
V1
V3
V11
Vectors
V1
V9
V11
V V V
an bn cn

V V V
an bn cn

V V V
an bn cn
V V V
an bn cn
V V V
an bn cn
V V V
an bn cn
2
Vectors
V8
V9
V13
Vectors
V4
V5
V13
Vectors
V4
V5
V7
Vectors
V2
V3
V7
Vectors
V2
V3
V11
Vectors
V8
V9
V11
V V V
an bn cn
+
V V V
an bn cn
+
V V V
an bn cn
V V V
an bn cn
V V V
an bn cn
V V V
an bn cn
Vectors
V8
V12
V13
Vectors
V4
V12
V13
Vectors
V4
V6
V7
Vectors
V2
V6
V7
Vectors
V2
V10
V11
Vectors
V8
V10
V11
V V V
an bn cn
+ +
V V V
an bn cn
+ +
V V V
an bn cn
+ +
V V V
an bn cn
+ +
V V V
an bn cn
+ +
V V V
an bn cn
+ +
Vectors
V8
V12
V14
Vectors
V4
V12
V14
Vectors
V4
V6
V14
Vectors
V2
V6
V14
Vectors
V2
V10
V14
Vectors
V8
V10
V14
V V V
an bn cn
+ + +
V V V
an bn cn
+ + +
V V V
an bn cn
+ + +
V V V
an bn cn
+ + +
V V V
an bn cn
+ + +
V V V
an bn cn
+ + +
Zhang found that if you know the prism that the demand vector lies
within, then it is possible to nd the correct tetrahedron by matching the
signs of the three line-neutral voltages Van , Vbn , Vcn for the demand with
the polarities of each of the switching vectors which make up the vertices
of the four tetrahedrons within a single prism. So, from the example
above, where it has already been shown that the output demand voltage
is within Prism 6, the phase-neutral demand voltages are
65

V
an
Vbn
Vcn
120

= 164

44
(5.5.5)
Now if these are compared with the signs of the tetrahedrons which go
to make up Prism 6 in Table 5.3, this gives the result that the output
demand voltage is contained within tetrahedron 3 of that prism, and the
table then gives the three bounding space vectors as being V8, V10 and
V11.
5.6
Determining the input sector
Moving onto the input current, and once again looking at Figure 5.7 it
can be seen that one area is shaded, and this shows the smallest bounded
area for the input current space. Any space vector within this area can
be generated by combining the two stationary space vectors that bound
either side, and this can be seen in Figure 5.10.
As before, these bounded areas are called sectors and are numbered as
For the matrix converter where the primary concern is controlling the
output voltage, while also controlling ensuring that the converter has a
unity input displacement factor, it is then not the input current magnitude that is directly controlled, as this is dependant on both the output
voltage and the characteristics of the load, instead it is the phase of the
input current which needs be controlled for a unity displacement factor.
Hence the input current vector will be maintained in phase with the
input voltage vector. This phase relationship allows a simple determination of which of the input current sectors the demand vector lies within
for any set of input voltages[4], as it will have the same phase angle as
the input voltage vector, and where the input current sectors are dened
as
66

I2
3
I1
I3
VA
VB
VC
i I5
i I6
ii
i
1
I4
Vi
I6
I5
Figure 5.10: Input Current Plane showing input current vector ii
1,
2,
3,
Sector =
4,
5,
6,
for
for
for
for
for
for
11
6 < 6
6 < 2
5
2 < 6
5
7
6 < 6
7
3
6 < 2
3
11
2 < 6
(5.6.1)
with being the phase angle of the input voltage vector within the
plane. This can be seen in Figure 5.10 where the input voltage phasor
is within the shaded area, which is dened as current sector 6 and the
required input space vectors are I5 and I6.
67

5.7
Selecting the Switching States
Now that both the input and output sectors are known for the required
output voltage and input current phase, these are then used to dene
the set of switching states that are needed. However, due to the extra
output leg this is more complex than with the 3x3 matrix converter.
The switching states are found by comparing the two sets of possible
switching states that can be used to generate the input current vector
and output voltage vector, and by using the measured input line-to-line
voltages to select the correct set.
For the output, as has been described above in Section 5.4.1, the entire
output voltage space is dened by fourteen vectors and using the symmetry between the vectors themselves and the switching states used to
create them, it is easy to see that for each output space vector there are
42
three ( 14 ) associated switching state pairs, so as there are three output
space vectors, this then gives nine possible switching state pairs that can
be used within any one tetrahedron.
In a similar manner for the input, the input space is dened by six space
vectors and using the inherent symmetry between the vectors themselves, and switching states, as set out in Sections 5.4.1 and 5.4.2, it
can be seen that for each input current space vector there are seven
( 42 ) associated switching state pairs. So, as there are two input current
6
space vectors for each input current sector, this gives fourteen possible
switching state pairs that can be used for any one stationary space vector.
Continuing to the examples from above, where the input current is in
sector 6, so requiring input vectors I5 and I6 and the output voltage in
tetrahedron 3 of prism 6, requiring output vectors V8, V10 and V11.
Then, referring to Table 5.2 it is possible to select all of the possible
switching states that are able to generate the required vectors, remembering that the vectors themselves come in positive/negative pairs and
so the switching states associated with both of these should be used here.
So for the example above the Table 5.4 shows all the possible switching
states that can be used to generate the different input and output vectors. However, only those switching states which correspond to both the
input current and output voltage vectors can possibly be used with this
combination of input current sector and output tetrahedron, and these
are shown as the Matching States in Table 5.4.
Looking at these six matching switching state pairs in Table 5.2, where
the required output vectors, V8, V10 and V11, can be created by these
68

Table 5.4: Switching state selection example
Input
Output
V8
Current Sector 1
Voltage Sector 6:3
V10
V11
V8 :
1, 2, 3
I5 : 2, 5, 8, 11, 14, 17, 20
V10 : 16, 17, 18
I6 : 1, 4, 7, 10, 13, 16, 19
V11 :
4, 5, 6
1, 2, 4, 5, 16, 17
+1, 2, 4, +5, +16, 17
I1
I6
Space Vectors Required
Possible Switching States

Matching Switching States
Actual Switching States used
matching switching states, however the value of the switched line-toline voltage will dictate which of these 12 switching states are actually
used. Once again using the example above, it is known that the input
current vector is within sector 6, where as can be seen in Figure 5.11, VAB
will always be positive and VBC will always be negative. Looking further
at Figure 5.11 it can be seen that for every input current sector, there is
always a single line voltage which is always positive, and is always the
most positive line voltage. There is also a single line voltage which is also
always negative, and this is always the most negative line voltage. It is
the point where the third line voltage either become the most positive,
or the most negative, when the input current sector changes.
1
1
VAB
VBC
VCA
VA
VB
VC
5
6
7
6
3
2
11
6
Figure 5.11: Line and Phase Voltage plots showing current sector
Now looking at the switching state pair 2 that will be used to generate
69

the vector V8. This switching state uses the input phases VB and VC
and switches them to the outputs, so, knowing this and using the fact
that with VBC will always be negative in this input current sector, it can
be seen from Table 5.2 that switching state 2 is needed. Using the
symmetry of the vectors, switching state +2 would normally create V8
if is VBC was positive, but as VBC is negative in this case, switching state
+2 would actually create vector V7. The opposite is true for switching
state 2, which is why it is selected in this case.
However, if the same exercise is performed for the switching state pair
1, which is also being used to generate vector V8 except this time it is
using VAB , which in this example is positive, the switching state +1 will
need to be used. Completing this for each of the switching state pairs
listed gives the six switching states which are required for the example,
and these are shown at the bottom of Table 5.4 labelled Actual Switching
Stated used.
5.8
Combining the Input and Output Spaces

v1
vd
o
v3
o
o
v2
Figure 5.12: Demand Vector generation from the 3 Space Vectors
From the vector diagram given in Figure 5.12 the following equation can
be written down for the demand voltage
vd = o + o + o
70
(5.8.1)

Table 5.5: The Base Vectors for the stationary space vectors
V0
V1
V2
V3
V4
V5
V6
V7
c+n
b+n
b+c
b+c+n
nnpp
npnn
npnp
nppn
nppp
nnnn nnnp nnpn

V
1
-3
1
-3
-1
3
-1
3
2
-3
-2
3
1
- 3
1
- 3
1
-
3 2
3 2
3
2
3 2
3
1
3 2
3 2
V8
V9
V10
V11
V12
V13
V14
V15
a+n a+c a+c+n a+b a+b+n a+b+c+n
pnnn pnnp pnpn
3 2
pnpp
ppnn
ppnp
pppn
pppp
2
3
2
3
1
3
1
3
1
3
1
3
1
- 3
1
- 3
3 2
3 2
3 2
3
1
3 2
3
2
3 2
3 2
where o , o and o are dened as the 3 vectors that when combined

make up the required output demand voltage vector in space and
o = vo v1
(5.8.2)
o = vo v2
(5.8.3)
o = vo v3
(5.8.4)
where vo , vo and vo are the magnitudes, and v1 , v2 and v3 are the base
vectors in the directions of the three output space vectors. These base
vectors are the direction vectors for the 14 stationary output switching
vectors, along with the 2 zero state vectors, and these are all generated
from the primary vectors (5.3.6) as shown in Section 5.4.1 and listed in
Table 5.5.
So, it is known that the smallest bound volume in the output space is the
tetrahedron, and that it requires 3 stationary voltage vectors to dene the
vertices of this tetrahedron. From Section 5.7 it is known that for each of
the 3 stationary vectors are themselves created by using two switching
states. This therefore means that for each of the vectors o , o and o ,
there are two switching states associated with them, so therefore
71

I
o = vo v1 = vo v1 I + vV I v1 V I
o
o =
o =
(5.8.5)
I
v o v2 = v o I v2 I I + vV v2 V
o
I
IV
vo v3 = vo I I v3 I I I + vo v3 IV
(5.8.6)
(5.8.7)
I
where I to V I are the duty cycles for the six switching states, and vo to
vV I are the instantaneous voltages generated at the output legs.
o
i1
vi
III
III i i
I I +
ii
IV
ii I V
II
II i i
ii
+V
ii V
+V
I V
ii I
i2
Figure 5.13: Input Current Vector generation from the 2 Space Vectors
For in the input current vector, the situation is slightly different. As
stated above, the converter is not directly controlling the magnitude of
the input current vector, instead it is controlling the phase. As this is
done to give the converter a unity displacement factor this means that
the phase angle of the input current should match the phase angle of
the input voltage, . So, as the input current vector is required to
follow the input voltage vector and looking at Figure 5.13, the following
equations, (5.8.8) to (5.8.10), can be written down. These equations force
a zero value onto the perpendicular component of the required current
vector with respect to the input voltage vector. This perpendicular component is signied by the je ji term. This is done in the same way as for
the 3x3 matrix converter[4] and so gives
72

V
iiI I + ii I V I je j i e j(Ki 1) 3 = 0
V
iiI I I I + ii V je j i e j(Ki 1) 3 = 0
iiI I I I I I + iiIV IV je j i e j(Ki 1) 3 = 0
(5.8.8)
(5.8.9)
(5.8.10)
where Ki is the input current sector and i is the input current phase
angle measured with respect to a line bisecting the input current sector,
and is limited by
i
6
6
(5.8.11)
What this means is that a particular output voltage vector is created by

the sum of the two vectors created by the associated pair of switching
states (5.8.5), however these two switching states create different vectors
within the input current plane and so by balancing the ratio of the duty
cycles of this pair of switching states, it is possible to create a resultant
input current vector which is directly in phase with the input voltage
vector, or in other words, has a zero length component in the direction
perpendicular to the input voltage vector, and this is what equation 5.8.8
states.
So, looking at Figure 5.13, and taking into account the restriction being
forced in equation (5.8.8) which forces the components of each vector
in the direction perpendicular to the input voltage vector to equal one
another, so as the two current space , it is then possible to write down
the following ratio
|iiI | I cos i
3
= |iiV I |V I cos i +
3
(5.8.12)
then due to the current stiff nature of the output of the matrix converter,
and that the two switching states being used to create a single output
voltage space always switch the same current, as shown in Table 5.2,
this means that
|iiI | = |iiV I |
therefore
73
(5.8.13)

cos i +
I
=
V I
cos i
I I I
I I
= IV
V
(5.8.14)
Substituting (5.8.14) into (5.8.5) then gives

vo =
I
vo I
cos i +
cos
+ vV I I .
o
(5.8.15)
As has been shown, as a consequence of the symmetry between the input

and output vectors it can be seen that the pair of switching states used to
generate a particular output voltage vectors are used to generate different input current vectors. This means that by changing the duty ratios of
the two switching states with respect to one another, it is possible to alter
either the input current phase, or output voltage vector, independently.
So, for a particular output voltage vector, the input current phase can be
any value within the limits of the sector, and likewise, for any particular
input current phase, the output voltage vector can have any value within
the limits of the tetrahedron.
This result shows that for the 4-leg matrix converter, the input current
phase and output voltage vector can be completely uncoupled from one
another, and this therefore allows complete control over the output voltage and input current phase.
5.9
Calculating the Duty Cycles
The nal stage of this derivation is to determine the required duty ratios
for each of the 6 switching states.
Initially, the length of each of the three vectors o , o and o which
produce the demand voltage is required. One solution to this problem is
given by Zhang[14] by using a lookup table, however, while this works
well for the 4-leg matrix converter, it was not thought to be general
enough for use with the 4-leg matrix converter. So, a more general approach to solving this problem was sought, initially using trigonometry
in a similar fashion to that employed by Casadei[4] for the 3x3 matrix
converter. This initial method was unsuccessful as, while it was possible
to perform the calculation, the addition of the third dimension complicated things greatly, and on a practical level the approach did not appear
to be simple, or suitable, for implementation in a DSP.
After further investigation a solution was found using the vector nota74

v o v1
vd
v3
O
v2
Figure 5.14: Distance of the vector vd from the plane Ov2 v3

tion already used to describe the vectors. Figure 5.14 shows how this
method works, where a plane is dened which contains the Origin and
the two vectors v2 and v3 . As the plane contains two of the three switching vectors which dene one of the output tetrahedrons, any deviation
of the demand vector from this plane can only be due to the third vector
v1 . The distance of the demand vector from the plane in the direction of
v1 can then easily be calculated. Taking the general vector equation of a
plane using the dot product as
n23 ( P P0 ) = 0
(5.9.1)
where P0 is a point in the plane and n23 is the normal to the plane, and is
dened as
n23 = v2 v3
(5.9.2)
In this case, and that of every plane that is of interest, the plane always
passes through the Origin, so the equation then becomes
n23 ( P) = 0
(5.9.3)
Now, the equation of a line is dened as

P = P1 u( P2 P1 )
(5.9.4)
where P1 and P2 are two points on the line and ( P2 P1 ) denes the
direction, and so for every value of u there is a point P that lays on
the line. In this case we want to know the distance, in the direction of
vector v1 , from the tip of the demand vector vd to the plane formed by
75

the vectors v2 and v3 . Therefore, in this case
P1 = vd
P2 P1 = v1
therefore
P = v d v o v1
(5.9.5)
Substituting (5.9.5) into (5.9.3) then gives

n23 (vd vo v1 ) = 0
(5.9.6)
and rearranging then gives

vo =
n23 vd
n23 v1
(5.9.7)
Now, the equation for the dot product is given by

a b = | a||b| cos
(5.9.8)
where is the angle between the two vectors a and b. So, expanding
equation (5.9.7) now gives
vo =
|n23 ||vd | cos o

|n23 ||v1 | cos 1
(5.9.9)
where 1 is the angle between the vector v1 and the normal vector n23 ,
and o is the angle between the demand vector vd and the normal vector
n23 .
As vector v1 is a xed space vector, it is therefore xed in relation to
the plane Ov2 v3 and likewise, it is xed in relation to the normal of this
plane. Therefore |v1 | cos 1 is a constant when working in this tetrahedron, and it can easily be shown that, due to the symmetry between the
space vectors, it is in fact constant for all tetrahedra within this space,
and for all stationary space vectors, and it is equal to
1
|v x | cos x =
3
76
(5.9.10)

Now substituting (5.9.10) into (5.9.9) and cancelling |n23 | leaves
vo =
3|vd | cos o
(5.9.11)
Now, substituting this into (5.8.15) gives
I
3|vd | cos o = vo I + vV I I .
o
cos i
cos i +
(5.9.12)
Re-arranging for the duty cycle I gives

I =
3| v d |
cos o cos i +
3
I
vo cos i + + vV I cos i
o
3
(5.9.13)
Now, once again using the example from above, where the three output
space vectors being used are V8 , V10 and V11, if it is taken that v1
corresponds to V8 then the two switching states that are being used to
generate this vector are +1 and 2 as shown in Table 5.2.
For switching state 2, this produces input space vector I5, and as this
would correspond to the lower of the two vectors when looking at the
sector as in Figure 5.13, referring back to (5.9.13) it can be seen that
the switching state is therefore controlled by duty cycle V I . When this
switching state is selected, the input phases VB and VC are switched onto
the output, so the voltage, vV I , generated across the output legs which is
o
dened by
VBC = VB VC
(5.9.14)
substituting in from (5.1.3) and (5.1.4) gives

VBC = Vi cos i
2
3
Vi cos i
4
3
(5.9.15)
where i is the input voltage phase angle. Then using the cosine sum-toproduct identity gives
77

. sin
3
= 3.Vi sin i
3
5
= 3.Vi cos i
6
VBC = 2.Vi sin i

VBC
VBC
4
3
(5.9.16)
However as the equations which dene the input current duty cycles
(5.8.8) to (5.8.10) use a phase angle related to a line which bisects the
current sector, the input voltage phase angle i needs to be referred to
the same line, therefore
i = i
(Sectori 1)
3
(5.9.17)
where Sectori is in the input current sector, and so as the input voltage
vector is within sector 6 equation (5.9.16) becomes
VBC
5 5
3
6
= 3.Vi cos i +
3
VBC =
3.Vi cos i +
(5.9.18)
In the example the input voltage vector is sat within input current sector
6, and as can be seen in Figure 5.11, this means that the voltage VBC is
negative. However switching state 2 is being used and this switches
VB C onto the output, so
VBC = 3.Vi cos i +

6
VBC = 3.Vi cos i

2
(5.9.19)
which means that the voltage produced alon

vV I =
o
3.Vi cos i
(5.9.20)
In a similar manner, when switching state +1 is used, it produces input

vector I6, which corresponds to the upper of the two vectors when look-
78

ing at the sector as in Figure 5.13. Once again, referring back to (5.9.13) it
can be seen that this switching state is therefore controlled by duty cycle
I
V I . So, during this input sector the voltage, vo , produced at the output
is dened by
I
vo =
3.Vi cos i +
(5.9.21)
Now, substituting (5.9.20) and (5.9.21) into equation (5.9.13) gives
I =
|vd |
Vi cos i +
cos o cos i +
3
cos i + + cos i
3
cos i
(5.9.22)
Looking at the denominator, and now using the cosine product-to-sum

rule this becomes
cos i +
+ cos i
cos i
6
3
2
3
1
= cos i + i +
+ cos i i
2
2
6
+ cos i + i
+ cos i i +
(5.9.23)
2
6
cos i +
Collecting alike terms
cos i + i +
+ cos i + i
2
2
2
+ cos i i +
+ cos i i
6
6
(5.9.24)
Using the identity cos ( + /2) = cos ( ), and then cancelling gives
cos i + i +
2
+ cos i i
6
1
cos i i
=
2
cos i + i +
2
+ cos i i +
6
+ cos i i +
6
(5.9.25)
This leaves two cosine terms, both using i i which is the dened as ,
the phase lag between the input voltage and input current. Substituting
79

this into (5.9.25) and simplifying using the cosine sum-to-product rule
once again
cos
+ cos +
2
6
6
1
=
2 cos () cos
2
6
3
=
cos ()
2
(5.9.26)
Substituting this back into (5.9.22) gives

2 |vd | cos o cos( i + )
3
=
cos
3 Vi
I
(5.9.27)
In a similar way the equations for the other ve duty cycles can be calculated as
II
I I I =
IV =
V =
V I =
2 |vd | cos o cos( i + )

3
cos
3 Vi
2 |v | cos o cos( i + )
3
d
Vi
cos
3
2 |vd | cos o cos( i )
3
cos
3 Vi
2 |v | cos o cos( i )
3
d
Vi
cos
3
2 |vd | cos o cos( i )
3
cos
3 Vi
(5.9.28)
(5.9.29)
(5.9.30)
(5.9.31)
(5.9.32)
It should be noted that |vd | in these equations is the the length of the
demand vector in the space, and is not the peak voltage of the
demand. However, if the demand voltages do form a balanced 3-phase
set then the length of |vd | equates to the peak phase voltage.
5.10
Voltage Transfer Ratio
A normal procedure at this point would be to derive the voltage transfer

function for the converter, however by adding the extra output leg, it
now becomes possible to produce a wide range of possible waveform
80

outputs, ranging from single phase outputs, up to the more normal balanced set of voltages, and on to having the converter produce different
voltage and frequencies on each output leg. As the range of outputs that
the converter is capable of producing is so large, it becomes very difcult
to write a generic equation that would give a voltage transfer function
in every possible case. But, as a general rule the instantaneous peak
output voltage between any of the output phases, including the neutral
leg, must always be less than the smallest difference between the most
positive and most negative phase voltages. Figure 5.15 shows how the
output voltages sit within the envelope of the input voltages.
400
VA
300
VB
VC
200
Vouta
100
Voutb
Voutc
0
-100
-200
-300
-400
0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
time(s)
Figure 5.15: Input Phase Voltage waveforms with the Output Voltage
Waveforms contained with the envelope
So, if a general, balanced or unbalanced, set of voltages is dened such
that
Va = Va sin ()
2
3
4
Vc = Vc sin
3
Vb = Vb sin
(5.10.1)
the difference between these phases are the respective line voltages, which
81

in this case are
Vab = Va Vb
Vbc = Vb Vc
Vca = Vc Va
2
3
2
4
= Vb sin
Vc sin
3
3
4
= Vc sin
Va sin ()
3
= Va sin () Vb sin
(5.10.2)
(5.10.3)
Now, taking the exponential form of sin such that
sin ( ) =
e j e j
2j
(5.10.4)
and substituting this into the equation for Vab in (5.10.2) above gives
2
2
e j e j
e j( 3 ) e j( 3 )
Vab = Va .
Vb .
2j
2j
(5.10.5)
Re-arranging the Vb part, this then becomes

j
j
e j e j
j 2 e e
3 .
Vb .e
Vab = Va .
2j
2j
(5.10.6)
and using the exponential form of sin once more from (5.10.4)
Vab = Va Vb .e j
2
3
. sin
(5.10.7)
Now, as
e j = cos + j sin
and solving for =
2
3
Vab =
(5.10.8)
the equation in (5.10.7) now becomes

V
Va + b
2
jVbi .
3
2
. sin
(5.10.9)
This voltage, when plotted on an Argand diagram produces a vector of

length |Vab | and phase ab , where
82

|Vab | =
Va +
Vb
2
+ Vb .
sqrt3
2
(5.10.10)
and
ab = arctan
Vb .
sqrt3
2
Vb
2
Va +
(5.10.11)
It is only the magnitude of the voltage which is of interest at this point,

and so re-arranging (5.10.10) then gives
|Vab | =
Va2 + Va .Vb + Vb2
(5.10.12)
The same exercise can be performed for each of the other two line-line
voltages giving
|Vbc | =
Vb2 + Vb .Vc + Vc2
|Vca | =
Vc2 + Vc .Va + Va2

(5.10.13)
Taking these equations, it can be easily seen that if the magnitudes of

the phase voltages Va , Vb and Vc are the same, Vx , then the magnitude of
the resultant line-line voltages will all be the same, and become the well
known result
|Vab | = |Vbc | = |Vca | =
3Vx
(5.10.14)
Looking at the input voltages rst, and plotting the resultant line-line
voltages in Figure 5.16, it can be seen that the difference between the
most positive and most negative input phase voltages is the envelope of
the rectied input voltage waveforms.
The entire area under the rectied waveform could be used to generate the output voltage, however, in order to guarantee that it is always
possible to produce the desired output, the output line-line voltage must
always be less than the minimum line-line voltage. This is because at any
instant in the input voltage cycle the converter must be able to generate
any point in the output voltage cycle, so the peak output line voltage
83

VAB
VBC
VCA
5
6
7
6
3
2
11
6
Figure 5.16: Line-Line Input Voltage waveforms, showing the envelope

of the rectied waveforms
must always be less than the minimum input line voltage.
As can be seen, the minimum occurs when the input angle, i , equals ,
3
therefore the peak line-line voltage, Vo(line) , which can appear between
any of the output phases is dened as
3Vi sin
3
3
3Vi
2
3
Vi
2
Vo(line)
(5.10.15)
and as
Vo(line) =
3Vo( phase)
(5.10.16)
Combining these two equations gives the well known voltage transfer
function for space vector modulation
84

3
2
(5.10.17)
Exactly the same procedure can be used with an unbalanced set of output voltages as well, however in this case there will be a different magnitudes for each of the output line voltages. This will therefore mean
that there are three different results for the voltage transfer ratio, and so
some care must be taken to ensure that the correct ratio is chosen.
If an unbalanced set of output voltages are demanded such that
Vo
3
2Vo
Vb =
3
Vc = Vo
Va =
(5.10.18)
with Vo being the largest of the three output voltage values. Then using
the equations laid out in (5.10.12) and (5.10.13) the following results are
obtained
|Vab | =
Vo
3
|Vbc | =
2Vo
3
|Vca | =
Vo2
Vo 2Vo
+ .
+
3 3
2
2Vo
.Vo + Vo2
3
Vo
+ Vo . +
3
Vo
3
7Vo
9
19Vo
9
13Vo
9
2Vo
3
7
Vo
3
19
=
Vo
3
(5.10.19)
13
=
Vo
3
and combining these results with the result in equation 5.10.16 then gives
3 3
2 7
3 3

2 19
3 3

2 13
q ab
1.70
qbc
1.03
qca
1.25
85
(5.10.20)

and therefore
q min (q ab , qbc , qca ) 1.03
(5.10.21)
It can be seen that with with this arrangement of unbalanced output

voltages, that the maximum voltage transfer ratio here is actually greater
than 1. The limit of this is when producing only a single output voltage,
with the other two output phases set to zero. In this case the maximum
voltage transfer ratio rises to become 1.5. This is because the converter
is able to control the voltage on the neutral leg to be negative, at the
same time as the output leg is being being positive, up to the maximum
allowed in equation 5.10.15, which is 1.5Vi . On further investigation, it
turns out that the maximum voltage transfer ratio always tracks that calculated from the two largest phase voltages, which in the above example
are Vb and Vc .
It needs to be noted here that the above derivation is only valid for
unbalanced outputs if all the three controlled outputs are all at the same
frequency, and have an equal phase displacement from each other. While
it would be possible to re-do the above equations for a different set
of phase relationships quite simply, it was found to be a signicantly
more complex task to produce a similar set of equations for outputs with
different frequencies. As such a slightly different approach was looked
at.
So, irrespective of whether the output is balanced or unbalanced, at
different or the same frequency, it is also possible to calculate the instantaneous voltage transfer ratio from the duty cycles calculated earlier, and
this has been laid out below.
Having previously derived all of the duty cycles, I to V I , it is possible
to calculate the voltage transfer ratio for the converter.
I + I I + I I I + IV + V + V I 1
substituting in equations (5.9.27) to (5.9.32) gives
86
(5.10.22)

2 v 1
d
cos o cos( i + ) + cos( i
3
3 Vi cos

3

3
) +
3
) +
3
) 1
3
(5.10.23)
Given that
cos i +
+ cos i
3
3
= cos i
(5.10.24)
this can be substituted into (5.10.23) and re-arranged which therefore

gives
3 cos
1
2 cos i (cos o + cos o + cos o )
(5.10.25)
where q is the ratio of the input and output voltages.

This equation represents the maximum voltage transfer ratio for the converter at any one instant when the output phase voltages are balanced.
If this equation is compared to that of the 3x3 matrix converter (3.4.13)
then it can be seen that this is of a very similar form, with both equations
being dependant on the input current phase angle and its displacement
angle to the input voltage, plus a the output voltage phase angle. Now,
whereas for (3.4.13) this is simply down to the phase angle of the output
voltage, in (5.10.25) it can be seen to be more complex, and is actually
dependant on the angles of the output voltage vector with respect to the
normal vectors for each of the three planes (cos o + cos o + cos o ).
Just as for the 3x3 matrix converter, the maximum voltage transfer ratio
for a whole cycle occurs when the denominator of (5.10.25) is at its minimum, and this occurs when cos i and (cos o + cos o + cos o ) both
equal one, and so this then gives
3
cos
2
(5.10.26)
which if unity displacement factor is assumed leads to the maximum

voltage transfer ratio being equal to 0.866, which is the well known value
seen in space vector modulation when used for other converters.
87

5.11
Other Four-Leg Matrix Converter Modulation Methods
At the time when this work started, the four-leg matrix converter was a
novel circuit for which there was no available prior work, and as such
the work here is entirely based on the extension of the methods used
for modulation in the 3x3 matrix converter and the four-leg inverter.
However, after the rst publication of the basic derivation [32] there have
since been two other approaches to the problem of modulating the fourleg matrix, both of which have originated from the Power Electronic and
Machine Control (PEMC) group at the University of Nottingham.
The rst approach is an extension of the Alesina/Venturini optimum
method [30], as it was perceived that the SVM based method described
within the original work was too computationally intensive to be able to
implement with any reasonably fast switching frequency. While this was
correct with the equations given in the original paper [32], the simplication to the calculation of the duty cycles described in this chapter, and
the further simplications which will be described in Chapter 6 mean
that it is believed that this is no longer the case.
With the difference in computational effort between the extended Alesina
/Venturini optimum method and the method described in this work
now being negligible, there is thought to be very little difference in performance between them, with the choice of which one to use being mostly
down to personal preference.
The second, and possibly most interesting, of the alternative modulation
methods is the one developed by Yue Fan [34, 35]. For this method it
separates the two functional halves of the matrix converter, the rectier
and inverter, and deals with each separately, joining them by a ctitious
DC link. Figure 5.17 below shows a diagram of a 4-leg matrix converter
using this technique, and as can be seen there is a signicant difference to
the circuit layout for this type of matrix converter as it looks a lot closer
to a normal rectier/inverter circuit. However, as can be seen, there is
no DC link capacitor and so this is a type of direct converter just as the
more standard 4-leg matrix converter used in this work, although due to
the two-stage nature this is sometimes called an indirect converter.
While this looks very much like a standard rectier/inverter setup, the
link between the two is not actually a DC link as it varies depending on
the switching of the rectier stage, and this is where the ctitious DC
link name comes from. The main job of the rectier stage in this circuit
88

Input
Fictitious
DC Link
Output
Figure 5.17: Circuit Diagram of the 4-Leg Matrix Converter using the
Fictitious DC Link
is to ensure that there is a positive voltage across the link, and to draw
unity displacement input current.
The inverter in this circuit works just as a normal inverter does, but has
the complexity of having to operate without a steady DC link voltage,
and so this complicates the operation. However, by knowing the input
voltages, and controlling the rectication stage the voltage across the
link can be known at all times, and so the inverter switching adjusted
accordingly.
This circuit has a number of advantages over the standard four-leg matrix converter, rstly the obvious one is that the number of switches in
this circuit is reduced from the 24 required in the standard converter, to
20 in this one with its related cost savings. The second advantage is
that due to some further advances in inverter and rectier modulation []
which allow the use of the demand voltages to dene the duty cycles, it
is possible to create a very simple method for calculating the duty cycles.
Apart from the different computational requirements between the three
techniques discussed here, it is thought that, based on their 3-phase
equivalents, all three techniques would give an equivalent output performance.
89
C HAPTER 6
Simulation of the 4-leg Matrix

Converter
While the concept and theory of the equations for the 4-leg matrix converter derived in Chapter 5 appears to hold together in a coherent manner, with the resulting equations being relatively simple and holding
a similar form to those found in the space vector modulation method
for the 3x3 matrix converter, the equations still require validation to
demonstrate that they are correct. This will be achieved via simulation.
It was decided that the simulation would proceed in several stages.
The initial stages were performed using Matlab in order to verify both
the method of simulation and the basic equations and concepts of the
4-leg matrix converter. Initially the method of simulation was tested by
implementing a standard 3x3 matrix converter. This was then followed
by the implementation of a 4-leg inverter to prove the 3-dimensional
output space vector, which, once working was then extended to be the
full 4-leg matrix converter.
In order to verify the derivation of the Space Vector Modulation technique shown in Chapter 5 above, it was necessary to preform a series of
simulations. The rst simulations were performed using Matlab as this
allowed a relatively quick way to check that the fundamental equations
outlining the output behaviour of the converter were sound, and to show
that part of the derivation to be correct. The limitation in the model that
was used in for these simulations in Matlab was that it only looked at
the output voltage and was also time-averaged, so giving the average
voltage over a switching period at each of the output legs.
Once it had been shown that the basic equations governing the behaviour
of the output voltage of the 4-leg matrix converter were sound, the simulation moved onto a more advanced stage using the Saber modelling and
90
C HAPTER 6: S IMULATION OF THE 4- LEG M ATRIX C ONVERTER

simulation software. This is a powerful software package that allowed
the converter to be dened as a set of bi-directional switches all controlled by a software block implementing the equations for the 4-leg matrix converter. The Saber package allows for very accurate simulations
of both the voltage and the current within the circuit, which allowed an
examination of both the input and output, voltage and current.
6.1
Simulation using Matlab
The initial simulation work was done using the Matlab software package, as this would be a relatively quick and easy way to implement the
equations derived in Chapter 5, allowing them to be checked that they
were valid and that the conclusions were correct.
6.1.1
4-Leg Inverter
The initial stages of the simulation work was taken up by proving that
the chosen simulation method was correct, where the output voltage is
time averaged over a switching period. This was done by simulating
a 3x3 matrix converter in a number of different methods, and checking
that the results for this chosen method were consistent. As the 3x3 matrix converter has been extensively simulated the results for this work
will not be included here, and so the rst simulation covered here is
an implementation of a 4-leg inverter. This would allow the basics of
the 3-dimensional SVM method as dened in Section 2.1 above to be
tested. Checking this would be especially important as it would ensure
that the code which is used for selecting the required output tetrahedron
is correct, and that the method of calculating the duty cycles for the space
vectors is also correct. These need to be shown to work correctly are they
are both required for the simulations of the 4-leg matrix converter.
There are several methods which can be used for calculating the duty
cycles for the 4-leg inverter, Zhang[14] uses a simple lookup table approach, however due to the more complex nature of the calculations
required for the 4-leg matrix converter, it was felt that the more general
approach derived in Chapter 5 should ultimately be used here. However, the look-up table approach would also be implemented to allow
the general method to be proved prior to using it within the 4-leg matrix
converter simulation.
The implementation for the simulation using the both of these methods
91

is a relatively simple task within Matlab, with the equations being easily
written out into a series of Matlab m-les, with Figure 6.1 showing the
major steps required.
inverter_sim.m
Setup Demand Matrices and dc Input Voltage
Transform into coordinates
Calculate output vector angle

matrix_angle_v.m
Calculate prism sector
tetra_calc.m
Calculate output
tetrahedron
Lookup Method
General Method
inverter_lookup.m
inverter_calc.m
Lookup switching states
inverter_lookup_delta.m
inverter_calc_delta.m
Calculate duty ratios
Calculate duty cycles
inverter_voltage_lookup.m
inverter_voltage_calc.m
Calculate output
voltages
Calculate output
voltages
Plot results
Figure 6.1: Block Diagram for the Matlab simulation for the 4-Leg
Inverter
This being a converter with 4 output legs, instead of the 3 for the 3x3
matrix, it might be expected that the simulation setup of the demand
voltages would require 4 different demand voltages. However, in practice it is either the output line voltage demands, Vab , Vbc and Vca , or the
phase voltage demands, Va , Vb and Vc , that are used. The value of Vn
in these situations is generally not specied as this is not generally of
interest when setting the demands, with its value being dened by the
92

other three voltages.
So, the output voltage demand for the 4-leg inverter simulation can be
dened as
Vdemab(0) Vdemab(1) ... Vdemab(t1) Vdemab(t)
Vdemline = Vdembc(0) Vdembc(1) ... Vdembc(t1) Vdembc(t)
Vdemca(0) Vdemca(1) ... Vdemca(t1) Vdemca(t)
(6.1.1)
such that
Vdemab(t) =
2Vdem cos(2 f dem t)
2
)
3
4
)
= 2Vdem cos(2 f dem t
3
Vdembc(t) =
Vdemca(t)
2Vdem cos(2 f dem t
(6.1.2)
where Vdem is the line-line voltage and f dem is the frequency for the desired output. These line-neutral demand voltages are then converted to
being the relevant phase voltages as
Vdema(0) Vdema(1) ... Vdema(t1) Vdema(t)
Vdem phase = Vdemb(0) Vdemb(1) ... Vdemb(t1) Vdemb(t)
Vdemc(0) Vdemc(1) ... Vdemc(t1) Vdemc(t)
(6.1.3)
using
1
(2Vdemab(t) + Vdembc )
3
= Vdema(t) Vdemab(t)
Vdema(t) =
Vdemb(t)
(6.1.4)
Vdemc(t) = Vdema(t) Vdemb(t)

Alternatively, the phase voltages can be dened directly as
Vdema(0) Vdema(1) ... Vdema(t1) Vdema(t)
Vdem phase = Vdemb(0) Vdemb(1) ... Vdemb(t1) Vdemb(t)
Vdemc(0) Vdemc(1) ... Vdemc(t1) Vdemc(t)

using
93
(6.1.5)
Vdema(t) =
2Vdem cos(2 f dem t)
2
)
3
4
= 2Vdem cos(2 f dem t
)
3
Vdemb(t) =
Vdemc(t)
2Vdem cos(2 f dem t
(6.1.6)
where in this case, Vdem is the RMS phase voltage.

The demand vector is then transformed into the space using
1
V(t)
2
V(t) = 0
3 1
V(t)
2 2
1
2
1
2
3
2
1
2 2
3
2
1
2 2
Vdema(t)
Vdem
b(t)
Vdemc(t)
(6.1.7)
The next step is to identify which sector, or in this case as the sector is
a volume in space, tetrahedron, the output demand vector lies in,
and the method for doing this is as described in Section 2.1. It by rst
calculating the angle that the demand vector would project on the
plane using
= arctan
V
V
(6.1.8)
and then selecting the Prism using
3
Prismo =
4
if
if
if
if
if
if
0 o <
3
o < 2
3
3
2
3 o <
o < 4
3
4
5
3 o < 3
5
3 o < 2
(6.1.9)
The sector in space identies which of the 6 prisms in space

contains the demand vector. The difculty now lies in algorithmically
nding a way to tell which of the 4 tetrahedrons, which go to make up
each prism, is the one containing the demand vector. Fortunately there is
a simple technique found by Zhang[14] where the correct tetrahedron is
selected by matching the signs of the output line-neutral voltages to the
signs of the three vectors which make up the vertices of the tetrahedron
in the direction. Figure 6.2 below shows an exploded view of one
94

of the six prisms which make up the output voltage space. Looking
at the vertices for each of these tetrahedrons it can be seen that each
one has a different distribution of signs in the direction, and a similar
distribution carries through on each of the other 5 prisms.
pnnn
[+ + +]
Tetrahedron 4
0
+
+
+
0
0
+
+
+
+
+
+
pnpn
+ 0 +
pppn
nnpn
0 0 +
pnpn
+ 0 +
nnpn
0 0 +
Tetrahedron 3
pnpn
0
+
0
+
nnpn
nnpn
0 0 +
0
0
-
0
+
+
+
pnpp
0 - 0
2
Tetrahedron 2
0
-
0
-
+
0
0
+
pnpp
pnpp
0 - 0
nnpp
- - 0
nnpn
pnpp
0 - 0
nnnp
Tetrahedron 1
nnpp
- - 0
nnnp
[- - -]
0
-
0
0
-
Figure 6.2: Exploded view of a single prism, showing the 4 tetrahedrons

Taking the example in equation 5.3 above where we know that this demand vector falls within prism number 6, now, looking at the signs of
the demand vector, there are 2 positive and 1 negative demand lineneutral voltages. Comparing that to the prisms shown in Figure 6.2
it can be seen that the tetrahedron 2 matches the signs, and so this is
the tetrahedron which the demand vector falls within, with Figure6.3
showing this demand vector plotted into the output voltage space, and
it can be seen that it does indeed fall within tetrahedron 2, showing that
it this is correct.
The simplest way to perform this in the simulation is to count how many
of the phase voltages which make up the demand voltage are positive
using
1 sign = 1 ;
3 i f ( Vdemand ( 1 ) >= 0 )
sign = sign + 1 ;
5 end
7 i f ( Vdemand ( 2 ) >= 0 )
sign = sign + 1 ;
95
pnpn
pnnn
vd
Prism 6
Tetrahedron 3
pnpp
Figure 6.3: Closeup view of a single prism, showing the Demand Vector
9 end
11 i f ( Vdemand ( 3 ) >= 0 )
sign = sign + 1 ;
13 end
This is the point where the more general method that is going to be
used for the calculation of the duty cycles in the 4-leg matrix converter
differs from this method, in that the information that it gathers from
the lookup table does not include the duty cycle matrix. For the more
general method this matrix is calculated on the y during the simulation.
6.1.1.1
Lookup Table Method for Calculating Duty Cycles
The output from the code above gives us the tetrahedron number which
can then be used, alongside the prism number, to look up the required
switching states, and the information used to calculate the duty cycles,
using Table 6.1.
Taking the matrix dened within the table, the duty cycles are then worked
96

Table 6.1: Switching state and Duty-Cycle selection for the 4-Leg
Inverter
3
Prism
Output Voltage Sector

Tetrahedron 1
Tetrahedron 2
Tetrahedron 3
I,II,III
I,II,III
I,II,III
11,6,7
1,11,6
1,9,6
3/2 - 3/2
3/2
1
0
1
0
- 3/2 0
3/2
1
3
0 1/2 - 3/2 -1 -1/2
0
1/2
3/2
-1
-1
0
-1
0
3
0
6,14,7
9,6,3
6,3,14
3/2
3/2
3/2
3/2
0
1
0
1
0

3
3/2
3/2
3/2 -1 -1/2
1
0 1/2
- /2
1/2
3/2
-1
0
-1
- 3/2 -1
-3/2
0
14,2,7
3,14,2
3,12,2
3/2
0
3
0
-1/2
1
0
3
0
3/2
-1 -1/2 - 3/2 1
- /2 - 3/2 0 1/2
1/2
-3/2 - 3/2 0
-1
0
-1
- 3/2 -1
2,10,7
12,2,5
2,5,10
3/2
3/2
3/2
-3/2
0
-1/2
1
-3/2
0
- 3 0 -1
0
-1 -1/2 - 3/2 1
0
1/2
1/2
3/2 -1
0
- 3 0
- 3/2 -1
10,4,7
5,10,4
5,13,4
-3/2 - 3/2 0
-1/2 - 3/2 1
-3/2 - 3/2 0
0
-1 1
0
1
/2 - 3/2 0 -1
1/2
3/2
1/2
3/2
-1
- 3/2 0
- 3/2 -1
4,11,7
13,4,1
4,1,11
0 - 3 0
-1/2 - 3/2 1
0 - 3 0
3/2
0 1/2 - 3/2 1 1
0
1
/2
3/2
1/2
3/2 -1
- 3/2 0
-1
0
-1
Tetrahedron 4
I,II,III
1,9,8
3/2
- 3/2 0
3 0
0
-1/2 - 3/2 1
9,3,8
3/2
3/2
0
3/2
3/2
0
-1/2 - 3/2 1
3,12,8
0
3 0
-3/2 - 3/2 0
1
0
1
12,5,8
3/2 0
-3/2
0
- 3 0
1
0
1
5,13,8
-3/2 - 3/2 0
3/2
- 3/2 0
3/2
-1/2
1
13,1,8
0
- 3 0
3/2
3/2 0
1/2
3/2 1
-
out directly using
I
(t)
II
= 1
(t)
Vdc
I
(tI)I
1 3
2
2
1
2
3
2
23
3
2
V(t)
1 V(t)
V(t)
0
1
(6.1.10)
Now that both the duty cycles and switching states are known, the output voltages at each time point can be calculated using
Vo =
Va(t)
Vb(t)
Vc(t)
Vn(t)
= VI(t) . I + VII(t) . I I + VIII(t) . I I I

(t)
(t)
(t)
97
(6.1.11)

where Vx are the voltages at the output legs for the respective switching
states taken from Table 6.2.
Table 6.2: Switching States for a 4-Leg Inverter
Switching
Output Leg Switching
L-N Output Voltage
State
Leg a Leg b Leg c Leg n Van Vbn
Vcn
Zero
Vectors
0A
0C
1
0
1
0
1
0
1
0
0
0
0
0
0
0
Vectors
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1
0
0
1
0
1
0
1
1
0
1
0
1
0
0
1
1
0
0
1
0
1
1
0
0
1
0
1
0
1
0
1
1
0
0
1
0
1
0
1
1
0
0
1
0
1
0
1
1
0
0
1
1
0
0
1
Vdc
-Vdc
0
0
0
0
-Vdc
Vdc
Vdc
-Vdc
0
0
Vdc
-Vdc
0
0
Vdc
-Vdc
0
0
-Vdc
Vdc
Vdc
-Vdc
-Vdc
Vdc
0
0
0
0
0
0
Vdc
-Vdc
-Vdc
Vdc
0
0
-Vdc
Vdc
Vdc
-Vdc
The results from this calculation being saved into the matrix shown below
Voutan(0) Voutan(1) .. Voutan(t1) Voutan(t)
Vout phase = Voutbn(0) Voutbn(1) .. Voutbn(t1) Voutbn(t)
Voutcn(0) Voutcn(1) .. Voutcn(t1) Voutcn(t)
(6.1.12)
where
Voutan(t) = Vouta(t) Voutn(t)

Voutbn(t) = Voutb(t) Voutn(t)
(6.1.13)
Voutcn(t) = Voutc(t) Voutn(t)

If required, the inverter line output voltages can be calculated using
98
Voutline
Voutab(0) Voutab(1) .. Voutab(t1) Voutab(t)
Vout
=
Voutbc(1) .. Voutbc(t1) Voutbc(t)
bc(0)
Voutca(0) Voutca(1) .. Voutca(t1) Voutca(t)
(6.1.14)
where
Voutab(t) = Voutan(t) Voutbn(t)

Voutbc(t) = Voutbn(t) Voutcn(t)
(6.1.15)
Voutca(t) = Voutcn(t) Voutan(t)

The calculated output phase voltage matrix can then be easily plotted
against time, and compared to the expected values dened by Vdema(t) ,
Vdemb(t) and Vdemc(t) from equation 6.1.2. The results from a simulation
run can be seen in Figure 6.4, where the calculated output from the
converter is using the + marker, and the expected output is shown with
the o marker. From this it is simple to see that the two sets of outputs are
matching.
200
Vdema
Vdemb
150
Vdemc
100
Vouta
50
Voutb
Voutc
0
-50
-100
-150
-200
0.5
1.5
2.5
3.5
4.5
time(ms)
Figure 6.4: Output from the 4-Leg Inverter Simulation, showing the
Calculated and Demand Output Voltages
99

In Figure 6.5 it shows how the selected tetrahedron and prism change
with vector angle.
12
Prismo
sign
10
Tetrao
o
0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
Figure 6.5: Output Voltage Vector angle, Tetrahedron and Prism for the
4-Leg Inverter Simulation
The results demonstrated in these gures show that the method used to
implement the 3-dimensional space vector modulation for the 4-leg inverter is correct. The next step is to implement the more general method
of calculating the duty cycles, which will be used with the 4-leg matrix
converter, and ensure that the outputs from both methods match.
6.1.1.2
General Method for Calculating Duty Cycles
With the prism and tetrahedron identied, the next step in calculating
the duty cycles via this method is to calculate the length of the space
vectors at the vertices. This is examined in Section 5.9, and while the
derivation of the lengths of the space vectors v1 , v2 and v3 shown is
correct, and this same method is shared with the inverter, it does not
lend itself to straightforward calculation. This means that a modication
is required for the program to be as efcient as possible, and this is
described below.
As the directions of all three output vectors is known, we can dene a
plane which contains any two of them and the origin Ov2 v3 such that
100

Table 6.3: Switching state and Duty-Cycle selection for the 4-Leg
Inverter
Output Voltage Sector
Tetrahedron 1 Tetrahedron 2 Tetrahedron 3 Tetrahedron 4
I,II,III
I,II,III
I,II,III
I,II,III
1
2
3
Prism
4
5
6
1 9 13
1 5 13
157
137
1 3 11
1 9 11
8 9 13
4 5 13
457
237
2 3 11
8 9 11
8 12 13
4 12 13
467
267
2 10 11
8 10 11
n23 ( P) = 0
8 12 14
4 12 14
4 6 14
2 6 14
2 10 14
8 10 14 ]
(6.1.16)
where n23 is the normal vector to the plane Ov2 v3 and P is any point on
the plane.
Then, using the same method as shown in Section 5.9, vo , is then the
length of the vector which intersects both the demand voltage vd and
the plane Ov2 v3 in the direction v1 . This then gives the equation
n23 (vd vo v1 ) = 0
(6.1.17)
and re-arranging then gives

vo (n23 v1 ) = n23 vd
(6.1.18)
Using the equation for the dot product (5.9.8) on the left hand side then
gives
vo |n23 ||v1 | cos 1 = n23 vd
(6.1.19)
And as stated earlier that

1
|v1 | cos 1 =
3
(6.1.20)
Substituting that back into equation (6.1.19) and re-arranging gives

vo .|n23 | =
101
3n23 vd
(6.1.21)

Now, the vector n23 is the normal vector to the plane Ov2 v3 and is dened by
n23 = v2 v3
(6.1.22)
which in turn is dened by
v2 v3 =
v 2 v 3 v 2 v 3
v 1 v 3 v 1 v 3
v 1 v 2 v 1 v 2
(6.1.23)
Now, for any single tetrahedron, there will be 3 space vectors which
make up its vertices, using the example from Chapter 5 once again these
would be V8, V10 and V11, and these are dened as
2
3
V8 = 0 V10 =
3 2
1
3

13
3 2
V11 =
1
3
1
3
(6.1.24)
3 2
Calculating the vector product (6.1.23) on the three combinations of these

vectors which are used in this method, and then calculating the length
of each vector gives the result that
|n xy | =
2
3
(6.1.25)
So, the length of the normal vector to the plane, irrespective of which 2
of the 3 vectors are used to dene it, is always the same length. Looking
at sim: tetrahedron vectors it can be seen that of the 3 vectors, V8 and
11 are the same length
1
sqrt2
, while 10 is longer
2
3
. It can then be
shown that unlike the 6 space vectors which describe the plane in 2dimensional SVM, the 14 space vectors used in 3-dimensional SVM are
not all equidistant from each other, and in fact this must be true for the
result in (6.1.25) to stand. It is in fact the case that there are two different
length groups of vectors, 8 shorter vectors and 6 longer vectors, and that
every tetrahedron is dened by 2 short and 1 long vector, and so the
result shown in (6.1.25) holds true at all times.
So, substituting (6.1.25) into (6.1.28) now gives
102
3 3
vo = n23 vd
2
(6.1.26)
As both the vectors n23 and vd are known, then the value of their dot
product can be easily calculated using
n23 vd = n23 .vd + n23 .vd + n23 .vd
(6.1.27)
which is a straightforward calculation.

The duty cycle for the switching state which then produces that vector is
calculated by dividing the result by the input voltage, in this case the dc
link voltage, giving the overall equation as
3 3
n23 vd
=
vdc 2
(6.1.28)
with the other duty cycles dened as
3 3
n13 vd
=
vdc 2
3 3
n12 vd
=
vdc 2
(6.1.29)
(6.1.30)
While it would be perfectly possible, and correct, to calculate the value

of vo , and then directly from (6.1.18), by dividing the two dot products,
the simplication was performed with a thought towards how the calculations would be implemented within a DSP, in which case the number
of divisions should be kept to a minimum. With the equations in (6.1.28)
and (6.1.29), only a single division needs to be performed, to calculate
the value of v1 , which is then used in each calculation.
dc
Now, with all the duty cycles now dened, all that is required is to
perform a similar set of calculations as for the lookup method, and to
produce the output phase voltage matrix
Voutan(0)
Voutan(1) .. Voutan(t1) Vouten(t)
Vout phase = V outbn(0) Voutbn(1) .. Voutbn(t1) Voutbn(t)
Voutcn(0)
Voutcn(1) .. Voutcn(t1) Voutcn(t)
103
(6.1.31)

where
Voutan(t) = Vouta(t) Voutn(t)

Voutbn(t) = Voutb(t) Voutn(t)
(6.1.32)
Voutcn(t) = Voutc(t) Voutn(t)

and the inverter line output voltages can be calculated using
Voutab(0) Voutab(1) .. Voutab(t1) Voutab(t)
Voutline = Voutbc(0) Voutbc(1) .. Voutbc(t1) Voutbc(t)
Voutca(0) Voutca(1) .. Voutca(t1) Voutca(t)
(6.1.33)
where
Voutab(t) = Voutan(t) Voutbn(t)

Voutbc(t) = Voutbn(t) Voutcn(t)
(6.1.34)
Voutca(t) = Voutcn(t) Voutan(t)

6.1.1.3
Matlab 4-Leg Inverter Simulation Results
As before, the results from a simulation, where the demand voltage is

200V and the demand frequency is 200Hz, were plotted to compare the
results with the demand voltages, Vdeman(t) , Vdembn(t) and Vdemcn(t) , along
with the results from the rst simulation using the lookup table method,
Voutan(t) , Voutbn(t) and Voutcn(t) , and the results shown in Figure 6.6. As can
be seen, the results from both types of simulation match the demand
voltages.
However, while the output voltages from both simulation methods were
found to be the identical, it was discovered that there was a difference
between the two methods when comparing the duty cycles. Plots of the
two sets of duty cycles are shown in Figure 6.7, where it can be seen that
there are jumps in the duty cycle values when using the lookup method,
whereas the duty cycle values always appeared to changed smoothly for
the general method. When comparing the actual sets of values for both
methods, it was easily seen that both sets of duty cycles included the
same three values, but they were just in held in different orders. This
104

200
Vdema
Vdemb
150
Vdemc
100
Vouta
50
Voutb
Voutc
Vouta
-50
Voutb
Voutc
-100
-150
-200
0.5
1.5
2.5
3.5
4.5
time(ms)
(a) Output Phase Voltage for a 4-leg Inverter using the general method for calculating
the duty cycles
300
Vdemab
Vdembc
200
Vdemca
Voutab
100
Voutbc
Voutca
Voutab
Voutbc
-100
Voutca
-200
-300
0.5
1.5
2.5
3.5
4.5
time(ms)
(b) Output Voltage Vector angle, tetrahedron and prism
Figure 6.6: Line and Phase Output Voltages from the 4-Leg Inverter
Simulation, showing the results from the Lookup and General Method
is entirely due to the way that the order that the switching states are
105

0.8
tot
I
0.7
I I
0.6
I I I
0.5
0.4
0.3
0.2
0.1
0
0.5
1.5
2.5
3.5
4.5
time(ms)
(a) Output Phase Voltage for a 4-leg Inverter using the general method for calculating
the duty cycles
0.8
tot
I
0.7
I I
0.6
I I I
0.5
0.4
0.3
0.2
0.1
0
0.5
1.5
2.5
3.5
4.5
time(ms)
(b) Duty Cycles for the General method
Figure 6.7: Duty cycle plots for the Lookup and General methods of
4-Leg Inverter Simulation
selected is different between the two methods, and that if these could be
106

matched, the duty cycle output would also be matched.
The results from these simulations demonstrate that the 4-leg inverter is
capable of generating a balanced 3-phase set of voltages at the outputs,
both when referenced to the neutral leg of the inverter as a phase voltage
and also referenced to the other output legs as a line voltage. However,
as this is a balanced set of voltages, which means that when the demand
voltages are transformed into the space, they produce a vector that
rotates evenly around the origin in the plane. Because the demand
vector stays in the plane this means that stays at zero for the entire
simulation. For a value to be generated in the demand vector, the
demand needs to be unbalanced. In normal use this would occur when
the inverter was supplying a non-linear or unbalanced load when the
inverter would need to be able to handle the neutral current, but as the
simulation for this inverter is not investigating the current ow, another
way needs to be found to introduce into the simulations. The easiest
way to do this is to create an unbalanced demand vector such that
Van + Vbn + Vcn = 0
(6.1.35)
For the simulation this is done by setting one of the demand for one of
the output phases, Vdema(t) , to have twice the voltage level of the other
2 phases, and then another output phase, Vdemb(t) , to have a twice the
output frequency of the other 2 phases, as shown in equation 6.1.36.
Vdema(t) = 2 2Vdem cos(2 f dem t)
2
Vdemb(t) = 2Vdem cos(4 f dem t
)
3
4
Vdemc(t) = 2Vdem cos(2 f dem t
)
3
(6.1.36)
Unlike the balanced 3-phase set, using these demand voltages gives the
demand vector a complex path within the space, with the value
going both positive and negative, instead of the vector being entirely
within the plane as with the balanced set of demand voltages.
The results from this simulation can be seen in Figure 6.8, which show
that both the lookup and general method for calculating the duty cycles
are capable of producing an output to match the demand voltages.
From these results it is possible to state that the output from the gen107

eral method for calculating the duty cycles produces the same results
on the output legs as for the lookup table method. This shows that
the derivation for this general method of calculating the duty cycles is
correct, along with also proving that the simulation technique chosen
for is correct, backing up the results from the 3x3 matrix converter. This
then allows the nal stage of the Matlab simulations to proceed, and
begin looking at simulating the 4-leg Matrix converter.
108

100
Vdema
80
60
Vdemc
40
V
Vdemb
Vouta
20
Voutb
Voutc
0
-20
-40
-60
-80
-100
0.5
1.5
2.5
3.5
4.5
time(ms)
(a) Output Phase Voltage for a 4-leg Inverter using the lookup method for calculating the
duty cycles
100
Vdema
80
60
Vdemc
40
V
Vdemb
Vouta
20
Voutb
Voutc
0
-20
-40
-60
-80
-100
0.5
1.5
2.5
3.5
4.5
time(ms)
(b) Output Phase Voltage for a 4-leg Inverter using the general method for calculating
the duty cycles
Figure 6.8: Output Phase Voltage for a 4-leg Inverter when following a
complex set of demand voltages
109
6.1.2
4-Leg Matrix Converter
With the results from the 4-leg inverter simulations proving that the
method for simulating the 3-dimensional space vector modulation was
correct, along with the general approach to calculating the duty cycles,
the next stage was to pull together the various different parts from the
above simulations to produce a simulation model for the complete 4-leg
matrix converter. However there were a number of steps that needed to
be overcome before this simulation could be made to work.
With the 4-leg inverter, as it only has a single input voltage, it is only
possible to create a switching vector in a single way. However with the
matrix converter, there are numerous converter switching states which
can create any particular switching vector depending on the state of
the input voltages at that time. This is a problem shared with the 3x3
matrix converter, however, with the greater number of output phases it
increases the possible number of combinations, and makes the selection
slightly more complex.
As with the 4-leg inverter, the switching states that would be required at
any one instant would need to be vertices in the output voltage tetrahedron, but on top of that, they also need to be vertices in the input sector
for the input current. Because any output tetrahedron can be associated
with any input sector, and vice versa, then with six input sectors and
twenty four output tetrahedrons this gives a possible of 144 different
combinations. While it would be perfectly possible to use a large 1:1
lookup table to perform this task, this would lead to a quite large and
unwieldy table, and with some experience from using the lookup tables
in the previous simulations, one that would be hard to nd errors within.
As such another method was sought that could make this signicantly
easier to program, and less likely to error.
Early on in the work it had been noticed that there was a certain amount
of symmetry within the input and output spaces, this can also be seen
in with the 3x3 matrix converter, and so these would be a good place to
start looking to simplify things.
As has been shown in Chapter 5 above, for each output voltage tetrahedron there is a set of possible switching states. Using the example in
Table 5.4 above, the tetrahedron 6 : 3 is made up of the space vectors
V8, V10 and V11, and these can be generated by the following switching
states
110
V8
1 2 3

Tetrahedron 6 : 3 = Vectors V10 = 16 17 18 (6.1.37)

V11
4 5 6
By repeating this exercise for each tetrahedron in the output voltage

space it can be seen that there is a symmetry between them. With the
above example, the opposite tetrahedron would be 3 : 2, which is made
up from the space vectors V4, V5 and V7, and these can be generated by
the following switching states
1 2 3
V7
Tetrahedron 3 : 2 = Vectors V5 = 16 17 18
V4
4 5 6
(6.1.38)
As can be seen, the set of possible switching states that can be used to
create the space vectors for the two tetrahedrons opposite to one another
are the same set of switching states. This is possible because, unlike the
4-leg inverter, there are always possible negative input voltages available, and switching a negative voltage in a particular switching state
produces a vector in the opposite direction.
Now moving onto the input sector, as stated in Section 5.7 above, this
selection of switching states can be narrowed depending on which input
current sector is required. As one of the requirements for this matrix
converter is that the input has a unity displacement factor, it is a simple
case of dening the required input current sector as being the sector
which the input voltage vector resides. Continuing the example from
Table 5.4 above, if the input current sector is 6, this is made up of the
space vectors I6 and I5, and these can be generated by the following
switching states
Sector 1 = Vectors
I6
I5
1, 4, 7, 10, 13, 16, 19

2, 5, 8, 11, 14, 17, 20
(6.1.39)
If this is then also performed for each of the other input current sectors,
as for the output voltage tetrahedrons above, it can be seen that once
again there is a symmetry between sectors. So, the opposite input cur111

rent sector to the one shown above is sector 3, and this is made up of
the space vectors I3 and I4, and these can be generated by the following
switching states
Sector 3 = Vectors
I3
I2
1, 4, 7, 10, 13, 16, 19

2, 5, 8, 11, 14, 17, 20
(6.1.40)
Once again it can be seen that the possible switching states that can be
used to generate the pair of opposite sectors are the same, and once again
this is due to having both positive and negative voltages being generated
at the outputs. Using these symmetries it is now possible to reduce the
number of combinations of input and output from 144 to 36 such that
Tetrahedrons
3:2
3
and Sectors = 1, 2, 4, 5, 16, 17
6:3
6
(6.1.41)
For each tetrahedron/sector pair there are 6 different pairs of possible

switching states, however this needs to be rened further as there are
only 6 different individual switching states required at any one point.
Once again using the example from above, where the input current vector is in sector 6 and the output voltage demand is in tetrahedron 6 : 3
this gives
Tetrahedron 6 : 3 and Sector 1 = 1, 2, 4, 5, 16, 17
(6.1.42)
Know that the input current is in sector 6, due to the unity displacement
factor this means that the voltage vector must also in input current sector
6, and to be in that sector it means that
VA
+ve
Sector 6 = VB = -ve
VC
+ve
(6.1.43)
Looking at Table 5.2 at the 6 switching state pairs it can be seen that
for these switching states the converter only switches between the lineline voltages VAB and VBC . So, during this time the only possible input
voltages are
112
Sector 6 =
VAB
VBC
+ve
-ve
(6.1.44)
Knowing that to generate the correct space vectors for the output voltage
tetrahedron the switching states need to generate the vectors V8, V10
and V11, and once again referring back to Table 5.2, it shows that with
a positive VAB and a negative VBC the following switching states are
needed
Sector 6 =
+VAB
VCA
+1 +5 +16
2 4 17
(6.1.45)
Performing this same analysis for the other three tetrahedron/sector pairs
which share this set of 6 switching state pairs then gives the results seen
in Table 6.4.
Current Sector
Current Sector 3
Current Sector 6
Tetrahedron
3:2
6:3
1, +2, +4, 5, 16, +17

1, +2, +4, 5, 16, +17
+1, 2, 4, +5, +16, 17

+1, 2, 4, +5, +16, 17
From these results it is possible to see yet another set of symmetries

within this set of sector/tetrahedron pairs, where for the same tetrahedron the two opposite input current sectors lead to sets of switching
states with opposite signs, and then for the same input current sector
the two opposite output voltage tetrahedrons lead to sets of switching
states with opposite signs. If this is considered for a moment then this
should be obvious as, for both the pair of input current sectors and pair
of output voltage tetrahedrons, they are generated from opposite sets of
space vectors, for example V8 equals V7 and I5 equals I2.
This exercise was then repeated for each of the set of sector/tetrahedron
pairs and it was found that they all contain the same symmetry as that
seen in Table 6.4. This pointed to how it would be possible to calculate
the required switching states for each combination of input current sector and output voltage tetrahedron using the procedure shown below.
As will become apparent, most of the information used in this process is
held in a number of different lookup tables. While this might not be the
most efcient method, it was chosen, instead of having a small separate
routine for each tetrahedron/sector pair, because it held all of the similar
113

data together, and so it was far easier to ensure the information was
correct, to make changes to the code, and to nd any bugs within the
simulation les. The loss in speed by performing the simulation in this
way is minimal in this instance.
The rst step is to calculate the input current sector using the same
method as used for the 3x3 matrix converter so
3
Sectori =
4
if
if
if
if
if
if
11
6 i < 6
6 i < 2
5
2 i < 6
5
7
6 i < 6
7
3
6 i < 2
3
11
2 i < 6
(6.1.46)
Then calculate the output voltage tetrahedron in the same way as for the
4-leg inverter, by rst calculating which prism in space the demand
vector resides in by
3
Prismo =
if
if
if
if
if
if
0 o <
3
o < 2
3
3
2
3 o <
o < 4
3
4
o < 5
3
3
5
3 o < 2
(6.1.47)
and then selecting which tetrahedron by counting the number of positive

phases in the demand voltages
1 sign = 1 ;
3 i f ( Vdemand ( 1 ) >= 0 )
sign = sign + 1 ;
5 end
7 i f ( Vdemand ( 2 ) >= 0 )
sign = sign + 1 ;
9 end
11 i f ( Vdemand ( 3 ) >= 0 )
sign = sign + 1 ;
13 end
114

Then, using the values found in Prismo and sign, using the lookup table
shown in Table 6.5 to nd Tetrao which determines which tetrahedron
the demand vector lies within. Once again it should be noted that due to
the symmetry of the space vectors and tetrahedrons, only the 12 tetrahedrons need to be dened, as the as the tetrahedrons opposite each other
in space are dened by the same set of switching states.
Table 6.5: Tetrahedron Lookup
1
2
3
Prism
4
5
6
1
1
5
9
4
8
12
sign =
2 3
2 3
6 7
10 11
3 2
7 6
11 10
4
4
8
12
1
5
9
Next, using the values already found for Sectori and Tetrao , use another
lookup table, shown in Table 6.6 , to nd the 3 space vectors, v1 , v2 and
v3 , which form the vertices of the tetrahedron
The order that both the space vectors and the switching states is held
is important here because of the relationship between them. As can be
seen in Section 5.9 the relationship is that the switching states ssI and
ssVI are associated with space vector v1 , and likewise ss2 and ss5 with
space vector v2 and then ss3 and ss4 with v3 .
With this relationship, it becomes easy to identify the pairs of switching
states related to each vector, but some care needs to be taken when identifying which switching state to associate with with duty cycle. Comparing the equations for the duty cycles I (5.9.27) and V I (5.9.32), both of
which are associated with the same space vector v1 . As can be seen the
only different between the two equations is that one uses ( i + , and
3
the other ( i 3 in the numerator. By once again using the example

throughout Chapter 5, and looking at Figure 5.13, it can be seen that the
( i + duty cycle is associated with the lower of the two space vectors,
3
in this case I5, while the ( i duty cycle is related to the upper space
3
vector (I6).
From Table 5.4, the switching states +1, 4and + 16 are associated with
space vector I6 and so use the ( i + duty cycles, and switching states
3
2, +5and 17 with space vector I1 and ( i . By performing this
3
analysis for each tetrahedron and input current sector, it was possible
115

Sectori
1, 3 or 5
2, 4 or 6
Space Vectors (v1 , v2 , v3 )
1
2
3
4
5
6
Tetrahedron
7
8
9
10
11
12
1:1
4:4
1:2
4:3
1:3
4:2
1:4
4:1
2:1
5:4
2:2
5:3
2:3
5:2
2:4
5:1
3:1
6:4
3:2
6:3
3:3
6:2
3:4
6:1
V1, V9, V13
V2, V6, V14
V8, V9, V13
V2, V6, V7
V8, V12, V13
V2, V3, V7
V8, V12, V14
V1, V3, V7
V1, V5, V13 V2, V10, V14

V4, V5, V13 V2, V10, V11
V4, V12, V13 V2, V3, V11
V4, V12, V14 V1, V3, V11
V1, V5, V7
V8, V10, V14
V4, V5, V7
V8, V10, V11
V4, V6, V7
V8, V9, V11
V4, V6, V14
V1, V9, V11
to build up the following sets of lookup tables, which would not only
work for the Matlab simulation, but would also be used for the Saber
simulations and the build of the actual converter.
So, using the same values found for Sectori and Tetrao , use the lookup
table, shown in Table 6.7 to determine the base set of switching states,
ssI to ssVI , for that input sector/tetrahedron pair.
The next step is to dene which switching state in each of the selected
pairs is going to be required, and which duty cycle that switching state
is associated with. Once again a lookup table is used, which is shown in
Table 6.8.
116

Sectori
1 or 4
2 or 5
3 or 6
Switching states (ssI , ssII , ssIII , ssIV , ssV , ssVI )
1
2
3
4
5
6
Tetrao
7
8
9
10
11
12
1:1
4:4
1:2
4:3
1:3
4:2
1:4
4:1
2:1
5:4
2:2
5:3
2:3
5:2
2:4
5:1
3:1
6:4
3:2
6:3
3:3
6:2
3:4
6:1
19, 13, 7, 9, 15, 21 21, 15, 9, 8, 14, 20 20, 14, 8, 7, 13, 19

1, 13, 7, 9, 15, 3
3, 15, 9, 8, 14, 2
2, 14, 8, 7, 13, 1
1, 10, 7, 9, 12, 3
3, 12, 9, 8, 11, 2
2, 11, 8, 7, 10, 1
1, 10, 19, 21, 12, 3 3, 12, 21, 20, 11, 2 2, 11, 20, 19, 10, 1
19, 16, 7, 9, 18, 21 21, 18, 9, 8, 17, 20 20, 17, 8, 7, 16, 19
4, 16, 7, 9, 18, 6
6, 18, 9, 8, 17, 5
5, 17, 8, 7, 16, 4
4, 10, 7, 9, 12, 6
6, 12, 9, 8, 11, 5
5, 11, 8, 7, 10, 4
4, 10, 19, 21, 12, 6 6, 12, 21, 20, 11, 5 5, 11, 20, 19, 10, 4
19, 16, 1, 3, 18, 21 21, 18, 3, 2, 17, 20 20, 17, 2, 1, 16, 19
4, 16, 1, 3, 18, 6
6, 18, 3, 2, 17, 5
5, 17, 2, 1, 16, 4
4, 13, 1, 3, 15, 6
6, 15, 3, 2, 14, 5
5, 14, 2, 1, 13, 4
4, 13, 19, 21, 15, 6 6, 15, 21, 20, 14, 5 5, 14, 20, 19, 13, 4
At this point everything is known that will allow the duty cycles to be
calculated:
Sectori states what input current sector the input voltage vector lies
within
Prismo states which prism in the output voltage space the demand
vector sit in
Tetrao , which is in a particular tetrahedron in the output voltage
space the demand vector sits within
117

sign
Vectors
1, 2 or 3
4, 5 or 6
ssI ssII ssIII + ssIV + ssV + ssVI +ssIII + ssII + ssI ssVI ssV ssIV
1
v1 = v1
1,
+ssI ssII ssIII + ssIV + ssV ssVI +ssIII + ssII ssI + ssVI ssV ssIV
2
v2 = v2
+ssI + ssII ssIII + ssIV ssV ssVI +ssIII ssII ssI + ssVI + ssV ssIV
3
v3 = v3
or 5
+ssI + ssII + ssIII ssIV ssV ssVI ssIII ssII ssI + ssVI + ssV + ssIV
Sectori
Prismo
Space
ssIV ssV ssVI + ssI + ssII + ssIII +ssVI + ssV + ssIV ssIII ssII ssI
1
v1 = v3
2,
ssIV ssV + ssVI ssI + ssII + ssIII ssVI + ssV + ssIV ssIII ssII + ssI
2
v2 = v2
ssIV + ssV + ssVI ssI ssII + ssIII ssVI ssV + ssIV ssIII + ssII + ssI
3
v3 = v1
or 6
4
+ssIV + ssV + ssVI ssI ssII ssIII ssVI ssV ssIV + ssIII + ssII + ssI
v1 , v2 and v3 hold the 3 space vectors dening the tetrahedron

associated with Tetrao
ssI to ssVI hold the switching states which create the space vectors
associated with v1 , v2 and v3
The next step is to dene the duty cycles in relation to this information.
Using the same method as was used for the 4-leg inverter, and looking at
equations 5.9.27-5.9.32 in Section 5.9, they are the set of equations which
allow the calculation of the duty cycles for each switching state. These
all follow the basic form
2 v cos x cos( i + )
3
x = d
cos
3 vi
(6.1.48)
As previously stated, this converter is designed to have a unity displacement factor, therefore cos is set to 1. Alongside this, it was shown in
(6.1.25) that the length of the normal vector is always constant, no matter
which combination of the 3 space vectors which dene a tetrahedron are
chosen, so the dot product of the normal vector to the plane nyz and
the demand vector (nd ) becomes
nyz vd =
3
vd cos x = nyz vd
2
118
2
v cos x
3 d
(6.1.49)

Substituting this back into 6.1.48, the basic form of the equation then
becomes
x =
vi
nyz vd cos( i
)
3
(6.1.50)
As this work on deriving the various equations took place, each part was
written into a separate Matlab m-le function. This allowed each stage
to be easily checked to ensure that it was correct before then using each
of them be used to build up the overall program to simulate the entire
converter. Figure 6.9 shows each of these different functions, and how
they all t together to form the overall simulation. As can be seen in
the block diagram, the simulation actually performs the calculation of
the duty cycles twice, once by using the equations (5.9.27)-(5.9.32) for
derived in Chapter 5, and the second set is to validate the simplication
of the equations which were derived earlier in this section.
6.1.2.1
Matlab 4-Leg Matrix Converter Simulation Results
Once the Matlab functions had each been proved to be functioning, it

was then possible to perform a complete simulation of the 4-leg matrix converter, and Figure 6.10 shows the results for the output voltage calculated from the duty cycle equations (5.9.27)-(5.9.32) derived
in Chapter 5. In this simulation, the converter was supplied with an
input voltage of 240Vrms, and was asked to provide an output with
a peak voltage of 200V at 100Hz. The results here are the phase to
neutral voltages Van , Vbn and Vcn plotted alongside the respective voltage
demand signal, and as can be seen, the results match perfectly.
The simulation was also setup to calculate the simplied method of calculating the duty cycles, as set out earlier in this chapter, and the results from this method, in the same simulation as before, are shown
in Figure 6.11. Once again, the calculated phase-neutral voltages at the
outputs match the demand voltages.
The last sets of Matlab simulations to be performed were to compare
the output voltage transfer ratio with the sum of the non-zero switching
state duty cycles. As discussed in Section 5.10, the voltage transfer ratio
is not a simple matter now that the converter has a fourth output leg, and
these simulations were performed in order to test the equation (5.10.26),
which states that the maximum transfer ratio is dened by
119

matrix_3D_svm.m
Setup Input Voltage and Demand Matrices

Transform input
into coordinates
Transform demand
into coordinates
Calculate input vector
angle
tet_list.m
Calculate output
tetrahedron
current_sector.m
Calculate input
current sector
matrix_switch_lookup.m
Derived Method
Simplified Method
delta_calc_derived.m
delta_calc_new.m
Vout_calc.m
Vout_calc.m
Calculate output
voltages
Calculate output
voltages
Plot results
Figure 6.9: Block Diagram of the 4-Leg Matrix Converter Matlab

Simulation
qmax =
3
cos
2
(6.1.51)
The rst simulation used a demand voltage of 23 Vin peak with an output
frequency of 100Hz, and the results of the output voltage can be seen in
Figure 6.13, and these are as expected, with the output voltage matching
the demand voltage. With this demand voltage, being the calculated
maximum for the input voltage, the plot of the sum of the duty cycles
should reach a peak of 1 at several points during the simulation when the
output voltage is at its maximum, and the available input voltage at its
minimum. However, looking at the plot of the duty cycles in Figure 6.14a
it can be seen that the total of the duty cycles does not actually reach 1,
120
Vdema
200
Vdemb
150
Vdemc
100
V
Voutan
50
Voutbn
Voutcn
0
-50
-100
-150
-200
0
0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
time(s)
Figure 6.10: 4-Leg Matrix Converter output voltages for the original
derived duty cycle equations
Vdema
200
Vdemb
150
Vdemc
100
V
Vouta
50
Voutb
Voutc
0
-50
-100
-150
-200
0
0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
time(s)
Figure 6.11: 4-Leg Matrix Converter output voltages for the simplied
duty cycle equations
it reaches a maximum of approximately 0.96, and so it appears to not
be following the inequality found in equation (5.10.26). The reason for
this discrepancy is found in Figure 6.14b, which is a plot of the voltage
generated at each of the output legs, including the neutral output leg,
and all referenced to the supply neutral. This shows that the output
121

7
Sectori
i
5
4
3
2
1
0
-1
0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
time(s)
(a) 4-Leg Matrix Converter Simulation Input Current Vector angle and sector
12
Prismo
Tetrao
10
sign
0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
time(s)
(b) 4-Leg Matrix Converter Simulation Output Voltage Tetrahedron and Sector
Figure 6.12: 4-Leg Matrix Converter Simulation Internal Variables

voltage, being at a frequency which is an integer multiple of the input
frequency, is synchronised with the input so that the peak demands in
the output voltage match the peaks in the available input voltage, and
122

likewise for the minimums.
300
Vdema
Vdemb
200
Vdemc
Voutan
100
Voutbn
Voutcn
0
-100
-200
-300
0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
time(s)
Figure 6.13: 4-Leg Matrix Converter Output Voltages when operating

with q
If the frequency of the output voltage is just slightly offset from that
of the input frequency this synchronisation is lost and the total of the
non-zero duty cycles once again peaks at 1, and this can be seen in Figure 6.15a, where the simulation is identical to the previous one, except
that the input frequency has been offset by 12 . The output phase-neutral
voltages remain unchanged from those shown in Figure 6.13, but looking
that the individual leg voltages when referenced to the supply neutral,
shown in Figure 6.15b, the difference with the previous simulation is
easy to see, and that there are several points throughout the cycle where
the peak output voltage equals the available input voltage.
So, as can be seen by the results shown above, while limit to the voltage
transfer ratio of 0.866Vin is true in a general case for a balanced 3-phase
output, there are once again specic times when this is not the case.
Looking at all the results from the Matlab simulations, they show that
the assumptions made, and the derived equations appear to be correct,
with the output voltages Va , Vb and Vc being able to be independently
controlled with respect to the neutral leg voltage. Obviously there are
limitations to these simulations in that this is only simulating the output
voltage, and so the input current control has yet to be tested. So, while
this does not fully validate the design, it gives enough condence in
the operation of the circuit at this point to move onto the next stage,
123

1
tot
0.9
0.8
I I
0.7
I I I
IV
0.6
0.5
V I
0.4
0.3
0.2
0.1
0
0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
time(s)
(a) 4-Leg Matrix Converter Simulation Duty Cycles when operating with q and
synchronised
400
Vin A
VinB
300
VinC
200
Vouta
100
Voutb
Voutc
Voutn
-100
-200
-300
-400
0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
time(s)
(b) 4-Leg Matrix Converter Simulation Input and Output Voltages, referenced to supply
neutral, when operating with q and synchronised
Figure 6.14: 4-Leg Matrix Converter Simulation Results when operating

with q and voltages synchronised
124

1
tot
0.9
0.8
I I
0.7
I I I
IV
0.6
0.5
V I
0.4
0.3
0.2
0.1
0
0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
time(s)
(a) 4-Leg Matrix Converter Simulation Duty Cycles when operating with q and
unsynchronised
400
Vin A
VinB
300
VinC
200
Vouta
100
Voutb
Voutc
Voutn
-100
-200
-300
-400
0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
time(s)
(b) 4-Leg Matrix Converter Simulation Input and Output Voltages, referenced to supply
neutral, when operating with q and unsynchronised
Figure 6.15: 4-Leg Matrix Converter Simulation Results when operating

with q and voltages unsynchronised
125

simulating the entire circuit using Saber.
6.2
Simulation using Saber
The Matlab simulations had so far proved that the equations which had
been derived were providing the expected results at that stage. They
show that the output voltage is able to be controlled, and also demonstrated how the internal variables used for selecting the input sector
and output tetrahedron were being correctly selected. At this point the
simulation was moved on to the next stage by using Saber, which is a
simulation software package from Synopsys. This is a powerful circuit
simulation tool which can be used to simulate complex circuits, both
analogue and digital, and this would allow a more detailed simulation
of the 4-leg matrix converter to be performed, this time being able to
take into account the load on the converter. This meant that in addition
to looking at the output voltage it would also allow the input current
waveforms to be investigated as well.
The rst step in the simulation process with Saber is to design the circuit
which will be simulated. Now, Saber is an incredibly powerful tool, and
it is easy to over-complicate a simulation by going into far too much detail in the circuit design, and while this will provide very accurate results
it would also be very slow, and the vast amount of the information which
it would be able to provide would be unnecessary for this investigation.
So, as always with any simulation, there is a trade-off between the speed
which the simulation runs and the amount of detail which the results
provide.
The circuit for the 4-leg matrix converter is made up of 12 bi-directional
switches, the basic layout of which can be seen in Figure 1.6, with an
example switch being shown in Figure 6.16. Each switch is made up
of 2 diodes and 2 IGBTs, with each of the IGBTs requiring a separate
gate drive circuit, and then also each IGBT has a separate gate drive
signal to ensure that current commutation occurs correctly, using one of
the techniques described in Chapter 4. Now, while a gate drive, with
the logic required to commutate the current correctly, might be a simple
circuit to build within Saber, having 24 of these will increase the number
of elements requiring simulation. Even though this would lead to a very
good model of a working converter, the extra information held in the
results would be unnecessary as the interest in these simulations is in
being able to verify that the derivation and operation of the 4-leg matrix
126

converter is correct, and that the overall switching patterns and overall
circuit operation are as expected when attached to a load.
Gate Drive
Circuit
Gxy
Four Step
Commutation
Gate Drive
Circuit
Figure 6.16: Bi-directional Switch Circuit

So, taking this into account, the decision was taken to use a circuit that
would be a lot simpler, and therefore quicker, to simulate. In place of
the IGBTs with their gate drives and the added complexity of their commutation, ideal switching elements were used. These has a number of
advantages, rstly they are driven by a logic level input which removes
the need to any extra gate drive circuit, and secondly, due to it being an
ideal switch, it has near instantaneous switching times, which removes
the need to use any commutation. So, by making this change, and using
simple ideal switches instead the IGBTs, a large number of circuit elements were removed, simplifying things greatly, and so speeding up the
simulation greatly. The new circuit for the bi-directional switch is shown
in Figure 6.17.
The circuit was then built up using a 3 x 4 block of these bi-directional
switching elements as the basis of the converter. This circuit is shown
in Figure 6.18, and as can be seen, without the need for gate drives
and commutation, it is now a relatively simple circuit. The only other
required circuit elements being a control block, which will be discussed
below, a set of sinusoidal voltage sources which make up the 3-phase
source feeding directly into the converter, a set of output inductors on
all 4 converter output legs, and nally a resistive load on each of the 3
output phase legs. Using the voltage sources directly onto the inputs
gives the voltage stiff characteristic as required at the input to the converter, and likewise, the inductors on each of the 4 output legs ensures
that the output is current stiff.
The biggest challenge for this simulation was the formation of the control
block, which is shown in Figure 6.19. It is by far the most complex
element making up the simulation circuit and its operation will be now
127
Q1
D2
D1
P1
D4
D3
Q2
Gate1
P2
Figure 6.17: Circuit Diagram used for the Bi-Directional Switch block in
the Saber simulations
be discussed.
The control block shown, as shown in Figure 6.19, is an element which
uses Sabers internal scripting language, MAST, to dene its internal
operation, and then dene how that appears on its outputs. The MAST
language is a hardware description language(HDL) which gives a programmatic way of describing both analogue and digital circuits. For this
simulation the control block is being used to calculate the duty cycles
and then output the respective switch control signals for each of the 12
switching blocks in the converter. These output signals will need to
depend on both the input voltage and the demand voltage/frequency.
There are also a number of additional outputs labelled to0 to to7, these
are used to allow the internal variables within the block to be monitored.
The design of the MAST language template for the control block started
with the Matlab m-les used in Section 6.1.2 above, but as it is not possible to directly run the Matlab simulation les within the simulation
package, these had to be modied. Obviously a reasonable amount of
the Matlab les themselves were also concerned with the mechanics of
the simulation itself, and so needed to be removed anyway, this left
behind the core logic required to calculate the switching states and duty
cycles for the converter. This core part of program could then be modied to meet the requirements of the MAST language. While the basic
128
SAa
SAb
SAc
SAn
SBa
SBb
SBc
SBn
SCa
SCb
SCc
SCn
matrix svm gen1

SAa
SAb
SAc
SAn
SBa
SBb
SBc
SBn
SCa
SCb
SCc
SCn
A
B
C
to0
to1
to2
to3
to4
to5
to6
to7
clk
gnd
gnd
Va
Vb
5m
Va_load
Vc
5m
Vb_load
30
Vn
5m
Vc_load
30
5m
Vn_load
30
Figure 6.18: Circuit Diagram used for the Saber simulations

steps of the calculations were kept essentially the same as those used
within the Matlab simulations, in order to increase the simulation speed
a number of the lookup tables were been removed, and this information
within the tables was included into the main body of the program. By
doing this it increased the speed of the simulation by approximately
10%.
Having modied the core calculations for the converter to more suit the
MAST environment, there was still an issue which needed to be solved
before the simulation begin. That problem was to do with how the actual
switching would take place, in what order, and how that would be generated within the MAST language. Because the actual switching process
was not required for the Matlab simulations, as the output voltages were
calculated as a time-averaged value directly from the switching states
and duty cycles, this switching process had so far remained undened.
129

matrix svm gen1
SAa
SAb
SAc
SAn
SBa
SBb
SBc
SBn
SCa
SCb
SCc
SCn
A
B
C
to0
to1
to2
to3
to4
to5
to6
to7
clk
gnd
Figure 6.19: Control Block for Saber simulation

Alongside this, when performing the Matlab simulations the only times
of interest were those related to the switching states, any unused time
within a switching period was simply ignored. These periods are the
times when the Zero states are used, and they are those switching states
which connect all 4 output legs to the same phase(see Table 5.2), and
so the voltage applied across the outputs is 0 for this time. Unlike the
Matlab simulations, Saber is a time based simulation package, and it will
need to know what to do with the outputs during this Zero state period
in order for the simulation to work correctly, just as would be required
in a physical converter.
Before choosing the Zero states, and where to place them, it is important
to rst look at the switching order of the switching states. Referring back
at Table 5.2, and once again using the example in used in Chapter 5, it is
possible to write down how the input phases are connected through to
the outputs for each of the switching states from Table 5.4, which then
gives
On examination of the way the phases change between the different
switching states when used in this order, then it is easy to see that they
are unbalanced, and that output leg b does not appear to switch at all
for this period, while output leg a switches on every change of state.
Bearing in mind that a large proportion of the losses seen within a matrix converter will occur during the switching process, when current is
forced to ow through a device which is in the process of switching, and
130

Table 6.9: Switching state output leg input phase
+1
2
4
Switching State
+5
+16
17
Output Leg
a b c n
A B B B
C B B B
A B A A
C B C C
A B A B
C B C B
so has a voltage developed across it. So, if the converter is used with the
above switching arrangement, the power loss in the devices in output
leg a will be signicantly higher during this period than those in leg b.
It is therefore an advantage to be able to reduce the number of switching
transitions where possible, and especially as in this case as it is as simple
as rearranging the order in which the switching states are used.
So, taking the switching order from in Table 6.9 above, these states can
then be re-arranged in such a way as to minimise the total number of
switching transitions required, and this is shown in Table 6.9.
Table 6.10: Modied switching state order to minimise the number of
switching transitions
+5
17
2
Switching State
+1
+16
4
Output Leg
a b c n
C B C C
C B C B
C B B B
A B B B
A B A B
A B A A
Alongside the need to reduce the number of switching transitions, to

attempt to minimise switching losses in the converter, there is another
reason why changing the switching order is advantageous, and that is to
do with the harmonic performance of the converter. This is important as
the harmonic make-up of both the input current and output voltage will
make a large impression on the size and cost of any lters which would
be required. As such it is always a good idea to try to keep the amount
of harmonics in both the input and output to a minimum. Obviously,
131

with a switching converter like this there will always be large amounts
of the switching frequency present in both the input current and output
voltage, but due to the relatively high switching frequency, these are
easily ltered out. The problem arises with harmonics which are closer
to the fundamental frequency of the output, and these get harder to
remove the closer they get, so requiring larger capacitors and inductors
and increasing both the cost and weight of the converter. So it is a good
idea to try to produce an output with as few low frequency harmonics
to start with.
In a paper by Zhang[14], which looked at, amongst other things, the harmonic performance of the 4-leg inverter with different switching schemes,
it was shown that by using a scheme which had the switch transitions
for each output leg symmetrically aligned about the mid point in the
switching period, they achieved the best performance of any scheme
that they tried. A brief look at the way the 4 legs are being switched in
Table 6.10 shows that the switching transitions for each leg are balanced
around the mid point, however it is a little more complex in this case
as each of the switching states has a different duty cycle. This can be
solved by effectively halving the switching period, and mirroring the
switching states in the second cycle, and an example of this is shown
in Figure 6.20. This does have the effect of doubling the number of
switching transitions, although in this case, the trade-off is worth it for
the increase in harmonic performance.
I
2
I I
2
I I I
2
IV
2
V
2
V I
2
4
+16
+1
2
17
+5
Ts
2
Ts
2
Figure 6.20: A Basic Switching Sequence

Moving to look at the Zero states now, and knowing that at least one
Zero state needs to be present to take up any unused time within the
period, it can be seen that the duty cycle for the zero state will be dened
by
132
z = 1 1 2 3 4 5 6
(6.2.1)
tz = Ts .z
(6.2.2)
where Ts is the sampling period. It is entirely possible to place this Zero

state at any point within the switching period, but as above, care needs
to be taken to ensure that the impact to the harmonic performance, and
any increase in switching loss, should be kept to a minimum. Looking
back at Zhang[14] once again, it was shown that the best distribution of
the Zero states throughout the switching cycle is to have them placed
symmetrically around the mid point, and for this converter that can be
done in one of two ways.
Looking at the switching sequence in Table 6.10 it can be seen that for
the rst and last switching states 3 out of 4 of the output legs are all
switched to a similar input phase. This neatly allows a Zero state to
be placed at each end of the period, with a duty cycle equal to z with
2
only a single switching transition being added each time. In this example
state ZC would be used at the beginning of the sequence, and ZA at the
end. This now appears to full the criteria in that all the switching edges
will be placed symmetrically around the mid point in the cycle, and that
there are now two Zero states that will take up the unused time in the
switching period. This is called the Two Zero method and is listed in
Table 6.11.
Table 6.11: Two Zero Switching State Sequence
ZC
+5
17
Switching State
2
+1
+16
4
ZA
Output Leg
a b c n
C C C C
C B C C
C B C B
C B B B
A B B B
A B A B
A B A A
A A A A
The second method starts off looking at the switching states in exactly
the same way, however this time it is also noted that the 3rd (+1) and
4th(2) switching states also have 3 of the 4 outputs switched to a sim133

ilar input phase, which allows a third zero state to be added into the
switching sequence. At rst, this seems to not be necessary as everything
required is in place for the Two Zero method, however on closer examination of the Two Zero method, if the number of switching transitions
per leg is examined, then without this third zero state being present leg a
has only a single transition compared to all the other legs having 2 transitions. By adding in the third zero state, this balances out the number of
switching transitions so that all 4 output legs have 2 transitions per half
cycle. This is called the Three Zero method and is listed in Table 6.12.
Table 6.12: Three Zero Switching State Sequence
ZC
+5
17
Switching State
2
ZB
+1
+16
4
ZA
Output Leg
a b c n
C C C C
C B C C
C B C B
C B B B
B B B B
A B B B
A B A B
A B A A
A A A A
Examples of the control signals for both of these possible switching sequences are shown in Figure 6.21. Due to all the output legs having the
same number of switching transitions in the Three Zero method, it was
thought that this would give the better harmonic performance, and so it
was chosen to be the initial method used within the simulation, although
both types of switching sequence would be investigated.
The nal step in the design of the MAST template was to nd a way
to interface the code which calculates the duty cycles and switching
states with the circuit shown in Figure 6.18. The problem that needed
to be overcome was this, how to ensure that the control block only performed its calculations once per switching period while still being able to
change the control outputs multiple times during this sampling period
with high accuracy. The rst part of this problem is relatively simple to
solve, by using an internal clock which is set to the converter switching
frequency, a positive going edge on this clock can be used to trigger
the control block into performing the duty cycle and switching state
calculations. This does not help with the switching of the control outputs
134
I
2
z
3
I I
2
I I I IV V
2
2
2
V I
2
z
3
S Aa
S Ab
S Ac
S An
SBa
SBb
SBc
SBn
SCa
SCb
SCc
SCn
ZC +5 17 2 +1 +16 4
ZA
Ts
2
Ts
2
(a) Two Zero Switching Sequence for the 4-Leg Matrix Converter
z
3
I
2
I I
2
I I I
2
z
3
IV V
2
2
V I z
2
3
S Aa
S Ab
S Ac
S An
SBa
SBb
SBc
SBn
SCa
SCb
SCc
SCn
ZC +5 17 2 ZB +1 +16 4 ZA
Ts
2
Ts
2
(b) Three Zero Switching Sequence for the 4-Leg Matrix Converter
Figure 6.21: 4-Leg Matrix Converter Switching Sequences

however, and it was initially thought that part of the control block would
need to be evaluated at every simulation time step to make sure that
135

these were changed at the correct time. This appeared to be a very poor
implementation, due to the extra calculations being added at every time
step, and so a more efcient solution was sought, and it was then realised
that a clock could also be used for this function as well.
When Saber performs the calculations within the control block, simulation time is stopped until all the control block calculations, and any
others required at that time step are complete, and so when triggered,
the results from the control block appear to be instantaneous within the
simulation. Once values for the duty cycles and switching states have
been calculated, as time is still stopped, it is simple to load the required
values for the rst switching state onto the outputs and then set a clock
which will trigger when the next switching transition is required. In the
example above using the Three Zero method, the rst switching state
would be Zero state ZC, with timer being set to
Ttimer =
z
3
(6.2.3)
Once this timer triggers, the new set values for this switching state are
loaded onto the outputs and the time to the next switching transition
loaded into the clock.
This method has the advantage that the simulation does not need to
perform any calculations within the control block at any time other than
at one of the clock transitions, to either calculate a new set of duty cycles,
or update the output states, and so this will speed up the simulation
considerably. This nal step completes the MAST template, and a block
diagram showing the functions within it is shown in Figure 6.22.
Having already proved that the duty cycle calculations and switching
state selection derived in Chapter5 are correct for controlling the converter output voltage, by having simulated and tested them using Matlab in Section 6.1.2, the rst step in the Saber simulations was to validate
the MAST control block template against these known results. This was
done using a series of tests to check on the state of the control blocks
internal variables.
6.2.1
Saber Simulation Results
The initial testing was used to make sure that the variables representing the input voltage vector were correct, and matched those results
found in the Matlab simulations. Figure 6.24 shows the results from this
136

matrix_3D_svm_3z.sin
On sampling clock going high
Read Input Voltage inputs

Transform input
into coordinates
On output clock going high
Calculate length & angle
of input voltage vector
Load next switching
matrix onto outputs
Calculate demand voltages

Transform demand
into coordinates
Load next switching

transition into clock
Calculate output prism

and tetrahedron
Reset output clock
Calculate input sector
Wait for next output

trigger

Calculate switching times
Setup switching matrices
Set output clock high
Wait for next sampling
trigger
Figure 6.22: Block Diagram of the MAST template for the Control Block
test where it can be seen that as the input voltage vector angle beta_in
changes, the input current sector isector changes with it in accordance
with equation (5.6.1). The changes in both of these are then also matched
by how the variable beta_in_bar varies, and so by comparing these results to those from the Matlab simulation in Figure 6.12a it can be seen
that they match perfectly.
The output variables representing the demand vector were also checked
along similar lines, with the results being shown in Figure 6.25. Once
again, by comparing the results from this simulation to those from the
Matlab simulation, shown in Figure 6.12b it can be seen that the internal
variables are working as expected, and match the values from the Matlab
simulation. From the results it can be seen that, although the angle that
the output vector makes on the plane is not plotted, the value can be
137

inferred by looking at how the value of prism is ascending regularly, as
this depends directly its value. This steady rise in output voltage angle is
indicative of a balanced 3-phase set of demand voltages, which is indeed
the case for this simulation.
It can also be seen in Figure 6.25 how sign just alternates between having
a value of 2 and 3. When you consider a balanced 3-phase set, then at
any one time there are either 2 positive phases, or 2 negative phases,
there can never be any other value, so as sign is the value
sign = No. of positive phases + 1
(6.2.4)
for a 3-phase set the value of sign will therefore only be 2 or 3, which
matches the result in Figure 6.25. This, so far, proves that the operation of
the control block MAST template is working in the same way in relation
to identifying the input and output vector spaces.
During the previous simulations the duty cycles were also calculated,
with a representative set being shown in Figure 6.26, and once again,
comparing this with the results from the Matlab simulations shows that
the control block is working as expected. The stepped nature of the
duty cycle waveforms seen in Figure 6.26 when compared to the Matlab
version shown in Figure 6.14a is because the control block duty cycles
only get calculated once per sampling period, whereas with the Matlab
simulation they were calculated at every iteration step.
With the two different set of internal variables being shown to be correct
for these simulations, along with the duty cycles having been calculated
correctly, the nal stage in the validation of the control block itself is
to show that the output voltage from the converter is being generated as
expected, and equals the demand voltage. Now this was a relatively easy
procedure with the Matlab simulations as the calculated output from
the simulations was a time averaged output signal, which to show it
was working, exactly matched the demand signal. Now that the output
voltage is actually being made up of the space vector modulated output
from the converter, it needs a little more care in checking the results.
Figure 6.27 shows a plot comparing the demand voltage Vdema with the
resulting phase-neutral voltage that is generated by the converter between output legs a and n. This is a valid comparison because the set
of demand voltages only contains the 3 values relating to Va, Vb and
Vc and due to equation 5.3.2 are therefore all implicitly dened with
respect to the neutral leg of the converter. As can be seen, the two
plots are exactly in phase with each other, but due to the switching
138

frequency component in the output voltage, as mentioned above, it is
very difcult to tell whether the demand voltage for this leg is being met
by the output.
To be able to measure this voltage, an fast Fourier transform (FFT) of the
output phase-neutral voltage shown in Figure 6.28 was taken and the
results of this are shown plotted in Figure 6.29. Now, with a 240V input
phase voltage being supplied to the converter, and using the maximum
value for q for a balanced set of output voltages, this gives a peak output
voltage of
Vdema =
3
2Vinrms =
2
3
.240 = 293.94V
2
(6.2.5)
Reading this value from Figure 6.29, the magnitude of the fundamental
frequency is shown to be 293.09V. On checking the other two output
phase-neutral voltages, these were also shown to match the phase of
their respective demand voltages, along with having very similar spectra
to that shown in Figure 6.29. From these it is therefore possible to state
that the converter is producing the correct output voltage, and that this
results matches up with the results from the Matlab simulations, thus
proving that the duty cycle calculations and switching state selection are
correct with respect to the output voltage.
Having shown that the simulation is generating the correct output voltages at the terminals to the converter, the resultant voltages which are
then produced across the load resistances were then plotted, and these
can be seen in Figure 6.30. These show each of the voltages to be almost
perfectly sinusoidal, with only a small amount of switching frequency
ripple being evident, and this result is backed up by looking at the plot
of the FFT of one of these voltages which is shown in Figure 6.31.
The clean spectra for these voltages once again re-enforces the evidence
from the spectra and waveforms of the terminal voltages in showing that
this space vector modulation technique is working for the 4-leg matrix
converter. It shows that the state of the converter switches is correct for
each of the required switching states, as the converter is producing the
correct voltages at its terminals in order to give the smooth sinusoidal
outputs across the load.
So looking now at these switching signals from the control block, Figure 6.32 shows how they change over a single clock cycle, and the effect
that they have on the output legs. The gate signals themselves are named
so that the input phase is listed rst, with the output second, so SAb is
139

the switch which connects the input phase A to output leg b. As can
be seen at the start of the cycle all the output legs are switched to input
phase C, then at the rst transition output leg a switches to input phase
B when SCa goes low, and SBa switches high. Output leg b changes
on the next transition and so it continues until all of the output legs are
switched to input phase B at the mid-point in that half-cycle before all
switching again to end up all connected to input phase A at the end of
the half-cycle. As can be seen, this is the Three Zero switching pattern
which was chosen for use in the simulations, and just goes to reconrm
that the control block is working correctly.
Further on to looking at the overall pattern of switches for the entire
converter, if just a single output leg is looked at, as in Figure 6.33, it can
be seen how the output switches between the different input voltages
as the switching state changes, which produces the overall waveform
Now that it has been conrmed that the simulated converter is working
as expected, by both checking that the internal variables are comparable
with the Matlab simulations, and also making sure that the output voltage follows the demand voltage, attention can now be focused one of the
sections which has not yet been covered in any of the simulations, the
input current. Figure 6.35 shows a plot of the input current alongside
its respective input phase voltage and it clearly shows how the input
current is exactly in phase with the input voltage, giving this converter
a unity displacement factor.
Just as for the converter output voltage looked at earlier, to be able to
tell if the input current is in fact sinusoidal under the large amount of
switching frequency noise an FFT of the input current was taken and
the result is shown in Figure 6.36.Once again, it can be seen that there
is a large fundamental current at the supply frequency, with a no other
discernible frequency spikes until the switching frequency is reached.
Figure 6.37 shows this even more clearly, where it plots the 0Hz to 15kHz
region of the FFT, but with the y-axis scale re-calculated as a percentage
of the fundamental. This plot clearly shows that there is very little low
frequency harmonic distortion within the input current.
So, with the output voltage still set at 23 Vinrms , and the load resistance
being set at 30, this gives a peak input current of
I A p eak =
2
1 207.852
Vout
= 2
= 8.48A
Vinrms R
240 30
140
(6.2.6)

which can be seen ties up well with the simulated result in Figure 6.36.
Any small difference with the expected result is due to the voltage drop
across the output inductors meaning that the load does not see the full
demand voltage across it.
One of the advantages of using a 4-leg matrix converter over a common
3x3 matrix converter is its ability to supply unbalanced loads without
causing large voltages uctuations in the output voltage, and the next
simulation looks at the situation where a single resistive load is set to
a value of 1 of the other two. Figure 6.38 shows the resultant output
3
currents from the converter, where it is easy to see that one is much larger
than the other two showing how the load is unbalanced.
The demand voltage for this simulation is identical to that used in the
previous simulations, and this is shown by the set of FFT plots shown in
Figure 6.39. This shows that even with an unbalanced load the voltages
available at the terminals of the converter remain set to their demand
values.
The effect of the unbalanced load on the input current is plotted in Figure 6.40, where it can be seen that while the input current is still in phase
with the input voltage, there is a marked difference to the input current
waveform shown for a balanced load in Figure 6.35. With the balanced
load the shape of the switched current is essentially sinusoidal, however
with the unbalanced load, there is an obvious dip in the central portion
of each positive and negative half-cycle.
This effect is shown more clearly in Figure 6.41 which shows a plot of the
FFT of the input current for the unbalanced load, and shows that as well
as the main fundamental current, there are two low order harmonics at
150Hz and 250Hz whose magnitude varies directly with the amount of
imbalance in the load. These harmonics are generated at frequencies
dependant on both the demand and supply frequencies
Harmonics = 2 f dem f supply
(6.2.7)
and it is these which lead to the distortion of the input current waveform.
These low frequency harmonics are extremely undesirable in the input
current, and this shows one of the main limitations of the 4-leg matrix
converter.
Unlike with a balanced load, an unbalanced load on a 3-phase supply
will always draw pulsating power, and because there are no energy storage components within the converter to be able to smooth out the power
141

ow through the converter, they are just passed directly through to the
supply. These are seen as the low frequency harmonics in Figure 6.41.
So, while the 4-leg matrix converter is perfectly capable of supplying an
unbalanced load, the presence of these low order harmonics in the input
current limits its use when connected to the normal mains supply.
While the results above prove that the 4-leg matrix converter works for
balanced 3-phase sets of output voltages, even when it is powering an
unbalanced load, this does not fully prove the operation of the converter.
This is because a balanced 3-phase set of demand voltages, when transformed into space, always has a value of zero, and, in all of the
Saber simulations up to this point, the converter has only been operating
with a balanced set of demand voltages. This means that it has been
operating in a very small region of its overall capabilities, which has, up
to this point been entirely within the normal 2-dimensional SVM plane.
Unfortunately, although it would certainly be an interesting avenue of
work, the active control of the 4-leg matrix converter is outside the scope
of this thesis.
However, while it is very extremely unlikely that this particular mode
of operation would ever be used, the following simulation was run to
be able to demonstrate that the converter itself works when the demand
vector trajectory leaves the plane, and so takes on non-zero values.
For this simulation run it was decided to reproduce the Matlab simulation, the results of which are shown in Figure 6.8, and see if the Saber
simulated converter would be able to produce the same results. For this
simulation the demand voltages are set as follows
Vdema =
Vdemb =
Vdemb =
Vin peak
2
Vin peak
4
Vin peak
2
cos (2 f dem (t))
cos 4 f dem (t)
2
3
cos 2 f dem (t)
4
3
where f dem is set to 100Hz, and Vin peak is set to
(6.2.8)
2240.
As to be expected, the results of the voltages developed across the load

are not particularly useful, however by looking at the FFT plots of the
phase-neutral voltages at the terminals of the converter, shown in Figure 6.42, it is then easy to see that even with these demand voltages that
the converter is able to generate them.
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Taking the results from this simulation, showing that even with a complex demand trajectory in space the converter operates as expected,
and then adding with the other simulations shown above, it proves that
the theory for the operation of a 4-leg matrix converter using space vector modulation derived in this thesis is valid and correct.
One further set of simulations was also looked at, and those were to do
with the comparison between the Two Zero and Three Zero switching
sequences. Up until this point, all of the simulations had been performed using the Three Zero switching method, as this had been assumed to be the superior switching sequence based on the results given
by Zhang [14]. In Zhang they had found that the best sequence for
switching the 4-leg inverter was where all legs were switched, and the
switching transitions were symmetrically aligned about the midpoint in
the switching period, similar to how it is shown in Figure 6.21, and this
was the starting point for both of the switching methods being investigated here.
So, from Zhang, it was thought that the best performance would be from
the method which provided the same number of switching transitions in
all 4 output phases per half-cycle, and so while the Two Zero method has
overall fewer switching transitions one of the phases will always have 2
less changes than the other 3, and so the Three Zero method was thought
to be best. Figure 6.43 shows a plot of the FFT for the output phaseneutral voltage when using the Two Zero sequence, while the FFT for
the Three Zero sequence is plotted in Figure 6.44. It should be noted
that the Three Zero spectrum shown here is different from that shown in
Figure 6.29 as the demand voltages for each is different. The reason this
needed to be done for this comparison is that as q goes up, the sum of
the switching state duty cycles I to V I approaches 1, and so the amount
of time that the Zero states are used approaches 0. As this happens the
differences between the two switching sequences shrinks and the spectra
then look identical. So, for these simulations, the q of the converter was
set to 0.5.
Looking at the two spectra it is easy to see the main differences between
them:
the group of frequencies at around the sampling frequency are
smaller for the Two Zero method
the group of frequencies at around twice the sampling frequency
are about half the magnitude in the Three Zero sequence
143

In both cases, the performance at low frequencies, well below the sampling frequency, was excellent.
These results were a little surprising as it was expected that the Three
Zero method would have the superior performance around the sampling
frequency, and it was thought that it would be higher around 2 and 3
times the sampling frequency, however, it was thought that the superior
harmonic performance throughout the entire range meant that the Three
Zero Method was kept and used for the build of the converter itself.
Once again, the results shown here back up the previous simulations,
and this is yet more proof that the derivation of the equations for Space
Vector Modulation of the 4-Leg Matrix Converter are correct.
6.2.2
Further Saber Simulation Work
Now that a basic set of simulations had been performed, which had
shown that the modulation technique was working correctly, a further
set of simulations were used to look into some of the possible issues
which could arise with the physical implementation of the converter.
6.2.2.1
The Effects of Processing Delays and Quantisation Errors
The rst stage of this investigation was to look into the effects on the
modulation process of the constraints that would placed upon it by the
use of a digital signal processor (DSP) for performing the calculations,
and a eld programmable gate array (FPGA) for controlling the switching of the devices. The actual design of these elements is described in
detail in Chapter 7, but for these simulations a number of assumptions
needed to be made about the implementation. The assumptions made
are as follows:
The switching frequency for the converter would be 12.5kHz
The FPGA clock frequency would be 50MHz
The A/D converters would have be 14 bit resolution
Each of these three assumptions introduces a different limitation into
the previously ideal nature of the simulations, and each of these will be
looked at in turn.
With the current ideal nature of the simulation, at any point in time the
software performs all the necessary calculations it needs at that time
144

point before moving onto the next time step. This means that while the
input voltages are actually sampled, the calculation of the switch timings
is all performed at the same instant the voltages are sampled, right at the
start of the switching period where they will be used. In practise with
a real DSP however, the input voltages will need to be sampled, and
the switch timings calculated, during the preceding switching period to
allow the correct switching right from the very start of the switching
period. As can be seen in Figure 6.45, there is a distinct delay between the
actual input voltage waveform and that used to calculate the switching
states. This introduces a problem which is that with a changing set of
input voltages, which we have by denition in a matrix converter, the
input voltages will be different from one sampling period to the next.
Now, while this change may not be very large with the relatively fast
switching frequency being used in this converter, there will still be an
error introduced by this.
The most straightforward method to counteract this error is to simply
calculate the difference in input voltage phase between the previous
sampling period and the current one, and then to just add this angle onto
the current input phase to give the phase at the beginning of the next
sampling period. However, this would mean that the voltages matched
at the start of the switching period, and diverged after. By adding on
another half of the calculated angle, this sets the sampled and actual
voltages to match half way through the switching period, thus minimising the error as seen in Figure 6.46.
This is the method what was initially used and the results can be seen
in Figure 6.47 showing the FFT of the output voltage with and without
compensation. As can be seen, even though the effects of this processing
delay are minor anyway, the compensation reduces these effects further
on the output voltage.
However, there is a possible problem with this approach due to the assumption that the sampled input voltage space vector rotates at a steady
speed. The problem is that as soon as there is noise on the input voltage then the instantaneous phase of that voltage no longer changes at
a steady rate, and so the simple calculation of the phase at the next
sampling point is no longer necessarily valid. This becomes especially
important once an input lter is added to the circuit, as any imbalance in
the load will cause harmonics in the input current, and thus distortion
in the input voltage to the converter. To try to counter the problem of
a noisy or distorted input voltage, another approach is required, and in
this instance a phase-locked loop (PLL) is used to track the fundamental
145

frequency component of the input voltage.
The use of a PLL means that the phase of the fundamental frequency
of the input voltage can be tracked easily tracked, and so allows the
accurate calculation of the phase of the input voltage at the next sample period despite the presence of any noise of distortion that may be
present. As can be seen from the waveforms in Figure 6.48, the output
straight from the PLL tracks the fundamental of the input voltage, and
this happens even when there is signicant distortion present.
However, because of the ability of the PLL to track the fundamental
frequency of the input, it does have a disadvantage. Depending on the
type of distortion, it can lead to slightly higher distortion levels at the
output when compared to the direct sampling method, however as will
be shown later in Section 6.2.2.3, the PLL does have other advantages.
Figures 6.49 and 6.50 show a comparison of the output voltage for the
two methods with the same noisy input signal, and in this case the output using the PLL is less distorted than that using the Delta method.
The reason for this is that as the voltage changes, the direct sampling
method takes into account the change in voltage, whereas when using
the PLL the sampled voltages are ltered, and so any change would
take a number of cycles to propagate through to the calculations. For
lower frequency distortion, where the sampled input voltage doesnt
vary greatly between sample points, the Delta method is able to track
the distortion and adjust the switching times accordingly. For higher
frequency distortion and noise, where the change in sampled input voltage is greater between sample points, the Delta method is not able to
track the distortion so well, and the PLL does a better job.
Either of these methods will work for reducing the effects of the processing delay, but the PLL has been chosen for this converter due to its
better ability to deal with noise, alongside this there are other reasons
which are described later in Section 6.2.2.3. For these simulations, the
PLL used is implemented in software, and is exactly the same as that
used in the actual design of the converter. Its design is comes from the
University of Nottinghams 3x3 matrix converter upon which this 4-leg
converter is based, and was not covered in this work, so the design of
the PLL is thus outside the scope of this thesis.
Looking next at the limitation imposed due to the clock speed of the
FPGA, and this limits the accuracy with which the switching times, calculated by the DSP, can actually be sent out to the switches. The limitation comes about because the period of the FPGA clock denes the
smallest unit of time that it is possible to use within the system. In this
146

case, with a 50MHz FPGA clock, this gives a clock period of 20ns, and
so all switching times generated need to be multiples of this value.
Now, while this is indeed a short period of time, with a sampling frequency of 12.5kHz, this only gives 4000 FPGA clock cycles for a single
switching period, and so it is this which limits the accuracy which the
switching transitions can be performed. This can somewhat mitigated
by calculating the difference between the ideal and the actual switching
points, and then adding this error into the switching times for the next
sampling period, however this is still not ideal. Thankfully though, this
effect is quite small, and the difference between the ideal and the actual
output voltages can be seen in Figure 6.51.
The nal limitation that was investigated is because of the xed word
length of the analogue to digital converters, which are used to sample the
input voltages. In this case the A/D converters are 14 bit, which means
that with a maximum input voltage of 400V the A/D converters are have
a resolution of 0.048V per bit. And so the effect of this quantisation error
is negligible on the output voltage.
Figure 6.53 shows the results from a simulation which applies all three
of these sources of error together, along with the various methods used
to eliminate them, and as can be seen the difference in the results from
the ideal is negligible.
6.2.2.2
Simulating Device Commutation
In all the simulations up to this point, all of the switching transitions

have been ideal in nature, with no attempt at commutating between
the incoming and outgoing devices. Obviously when building an actual
converter, this would not be possible and so, as discussed in Chapter 4,
one of these possible commutation techniques needs to be used. For this
converter it was decided that the 4-step commutation process would be
used.
As described in Section 4.3, the 4-step commutation process, as its name
states, commutates the current from the outgoing bi-directional switch
to the incoming one in four discrete steps. Firstly the non-conducting
outgoing device is turned off before the incoming conducting device is
turned on. By turning off the non-conducting device rst, this ensures
that there is no short-circuit current path between the incoming and
outgoing input phases. The next step in the process is to turn the conducting outgoing device off, before nally switching the non-conducting
147

incoming device on.
While this is straightforward in principle, there are a number of practical
problems which needed to be overcome before this approach could be
simulated. Firstly, the switching of each device takes a certain length
of time, and with this converter using IGBTs to do the switching they
would have the fast turn-on and slower turn-off times which are typical
for this type of device, and for the simulation the following were dened:
Ton = 50ns
To f f = 300ns
With these timings a suitable dead-time between each stage of the commutation process needs to be chosen, and in this case, taking into account the length of the turn-off period, a dead-time of 500ns was chosen. While initially this appears to be a short period of time, over the
whole commutation process this adds up to 1.5s for a single switching
transition and when the entire sample period is only 80s long, this
switching time is a signicant proportion. On top of this, depending
on the direction of current ow and the incoming and outgoing input
phase voltages, the actual switching, where the current transfers from
one bi-directional switch to the other, can occur at either the second or
third stage in the commutation process. Due to this, unless some form of
compensation is used, the actual switching instant will be either 500ns
or 1s late, which will then cause distortion in the output voltage.
On top of this issue, the length of the overall commutation process could
also limit the minimum possible pulse width, which would severely
impact on the operation of the converter, and the reduce the possible
range of output voltage that it is possible to produce.
However, it is possible to overcome both of these issues by the use of a
simple compensation process, and also by designing the commutation
within the simulation so that it can handle pulse-widths shorter than
the overall commutation length. The technique used to compensate for
the dead-time is to always start the switching process 1s early and this
allows the commutation block to sample the incoming and outgoing
phase voltages, along with the current direction. Then, depending on
which stage of the commutation process the actual voltage switching
takes place on, the commutation block can either start the process immediately, or wait for 500ns before starting the process. This ensures that
irrespective of the relative input voltages, or the current direction, the
148

actual switching point where the current commutates from one switch
to the other always takes place at the correct time.
Figures 6.54 and 6.55 show both of these switching processes in action.
In Figure 6.54 the delayed start to the commutation process can be easily
seen, ensuring that the output voltage switches between input phases
at the right point, while in Figure 6.55 the commutation process starts
immediately, also ensuring that the voltage switching happens at the
correct point.
By using this commutation it means it has almost no impact on the output voltage which is generated, and this can be seen in Figure 6.56. Unfortunately there is one part of the commutation process which cannot
easily be compensated for manner, and this is at the very start of each
SVM period, where the initial zero vector is switched onto the outputs.
If this zero vector is going to be held for less than 1s then there is not
enough time for the dead-time compensation to work correctly, and so
this will therefore limit the minimum allowed zero time during any one
switching period. By limiting the minimum zero time in this fashion, it
has a knock on effect on the maximum possible voltage transfer ratio,
which occurs when the zero-time within a switching period equals 0.
Now, the percentage of zero time in a switching period gives a direct
translation into the maximum voltage transfer ratio. So with the 3s
minimum of dead time required when using this compensation scheme,
this being 3.75%, which means that the maximum voltage transfer ratio
is reduced to 96.25% of theoretical maximum. This is true whether the
output is balanced of unbalanced.
It would however be possible to design a compensation scheme which
was able to account for this issue, but with the way that the converter
has been implemented within the Saber MAST language, this would not
be a simple task. So while it would be possible it was felt that, as the
scheme which has been implemented above was perfectly acceptable for
the purposes of this work, that this additional work was not required.
6.2.2.3
The Effects of Supply Impedance on Converter Operation
With the device commutation scheme in place and working, the next
stage in the investigation was to look at the effect that the introduction
of a typical supply inductance has on the operation of the converter. As
mentioned in Section 6.2.2.1 earlier in this chapter, this is especially important during unbalanced operation. This is where the current drawn
from the supply is not purely at the fundamental frequency of the input
149

voltage, and there are also harmonic components related to the fundamental frequency of the unbalanced output voltage.
This issue is important to investigate because the presence of these harmonic currents in the input can cause the input voltage at the converter
terminals to become distorted if there is any inductance in the supply.
Unfortunately there is always some inductance in the supply network,
and so the operation of the converter needs to be checked to ensure this
distortion does not cause a problem.
There is also another problem with having serial inductance in the supply which needs to be overcome as well, and that is down to the fundamental operation of the converter. In the initial assumptions about the
operation of the matrix converter it was stated that the input port was
voltage stiff, while the output port was current stiff. This means that at
the output of the converter, the voltage can change instantaneously from
the switching between input phases, but the current is continuous and
can not change instantaneously. The opposite is true for the input port,
where the current can instantly switch between different phases, while
the voltage cannot.
So, when considering the inductance of the supply into the converter,
it should be remembered that the current through this inductor cannot
change instantly, but this is a requirement for the correct operation of
the converter, and there are two main problems related to this. The rst
being what happens when you switch away from a input phase which is
carrying current, with the second being when you the output is drawing
current and you switch to another input phase.
The rst situation is where the converter tries to instantly switch the
output current away from one input phase to another. The inductance
in supply then tries to keep this current owing, and so the voltage at
the input to the converter could quickly rise, or fall, depending on the
direction of current ow. This rapid change in voltage across the device
could possibly become larger than the breakdown voltage, which would
then end up destroying the device, and disabling the converter.
The second situation arises where there is a no current owing in the
supply inductor in the incoming phase, so when it is switched to an output leg where current was previously owing the voltage at this point
will once again change suddenly to force current to ow. This has two
effects in this case, rstly it will distort the voltage and current at the output of the converter, and this change in voltage also has the possibility,
as before, of becoming larger than the breakdown voltage of the devices.
150

One way to counter these problems is to add a rectier circuit which sits
in parallel to the converter, and this arrangement is shown Figure 7.7.
This allows any current still owing in the supply inductance when
that phase is no longer connected to the output to just harmlessly ow
through the diodes of the rectier and into a capacitor where it can be
safely dissipated. This arrangement will also be able to supply current
in the second situation, but this can also cause some voltage distortion
at the input to the converter until the load current has fully transferred
to the supply.
Another way to counter this problem, which do not have the distortion
problems of the parallel diode bridge, is to add some parallel capacitance to the input of the converter as shown in Figure 7.8. Like the
diode bridge before, these capacitors are used to handle any current still
remaining in the input inductance once a phase has been switched out,
while also being able to supply current to an incoming phase before the
supply can take over.
Now, obviously with the capacitors arranged like this with the supply
inductances they form a passive second order low-pass lter, which in
any real application would be required to lter out the high-frequency
switching currents from the supply, and so this arrangement works well
to solve both of these issues. In a commercial application a more extensive lter than this would be used, with many more lter elements, but
for the task of investigating the behaviour of the converter the simple
arrangement with the supply inductance and input capacitance is perfectly adequate.
In the design of the actual converter, which is covered in Chapter 7, it can
be seen that both the rectier and the input capacitance are used, however the parallel diode bridge is only really there to provide protection
for the IGBTs in case of a problem with the converter. And so, for this
investigation the parallel diode rectier is ignored, and only the effects
of the input lter are looked into.
As was discussed in Section 6.2.2.1, one of the methods used to help with
the implementation issues of the converter is a phase-locked loop (PLL),
which, because it tracks the fundamental input frequency, may well have
some inuence over the operation when combined with this input lter.
So, part of the work looking into the effect of the input lter it also be to
see what difference the PLL made.
Figure 6.23 shows the Saber circuit used for the initial simulation work
with the input lter, which now includes the switch commutation but at
151

this point there is no PLL.
1m
P1
c_pwl
P1
Gate1 Sw1_4
P1
Gate1 Sw1_2
Gate2
P1
Gate1 Sw1_1
Gate2
Gate1 Sw1_3
Gate2
P2
3.3u
Gate2
P2
P2
P2
3.3u
ampl
c_pwl
drive_3p
frq
Three Phase
Motor Driver
n
a
b
c
1m
P1
P1
Gate1 Sw1_8
P1
Gate1 Sw1_6
Gate2
P1
Gate1 Sw1_5
Gate2
Gate1 Sw1_7
Gate2
P2
Gate2
P2
P2
P2
3.3u
Voltage
to
Control
Interface
Voltage
to
Control
Interface
clock_l4
LOGIC_4
CLOCK
matrix svm gen1

SAa
SAb
SAc
SAn
SBa
SBb
SBc
SBn
SCa
SCb
SCc
SCn
A
B
C
E
l e
to0
to1
to2
to3
to4
to5
to6
to7
SBx1
SBx2
to0
to1
P1
SAx
SBx
SCx
Gate1 Sw1_10
Gate2
SCx1
SCx2
to2
SAx1
SAx2
CurrDir
SBx1
SBx2
to0
to1
P2
P1
SAx
SBx
SCx
Gate1 Sw1_9
Gate2
SCx1
SCx2
to2
Commutation Control a
T_dead:500n
SAx1
SAx2
CurrDir
Commutation Control b
T_dead:500n
SBx1
SBx2
to0
to1
P2
P1
A
B
C
SAx1
SAx2
CurrDir
Voltage
to
Control
Interface
A
B
C
SAx
SBx
SCx
+
A
B
C
A
B
C
1m
SAx
SBx
SCx
Gate1 Sw1_11
Gate2
SCx1
SCx2
SAx1
SAx2
CurrDir
to2
Commutation Control c
T_dead:500n
SBx1
SBx2
to0
to1
P2
P1
Gate1 Sw1_12
Gate2
SCx1
SCx2
to2
P2
Commutation Control n
T_dead:500n
clk
gnd
Voltage
to
Control
Interface
1m
Voltage
to
Control
Interface
1m
Voltage
to
Control
Interface
1m
Voltage
to
Control
Interface
1m
gnd
5m
2.5m
1m
2.5
5m
10meg
Figure 6.23: Circuit Diagram of the 4-Leg Matrix Converter for

simulating the effects of the Input Filter
Now, assuming a typical value of 1mH for the supply inductance, then,
using equation (6.2.9) for the resonant frequency of an LC circuit, a 33F
capacitor would give a resonant/cut-off frequency of 2.9kHz, which is
well below the switching frequency.
fo =
2 LC
(6.2.9)
Figure 6.57 shows what happened to the input voltage when this circuit
was simulated with the following unbalanced load, which was chosen
to ensure that the unbalance not only resulted in giving different load
currents, but also that the displacement factor for each output phase
would also be different.
L a = 5mH
R a = 1
Lb = 2.5mH
(6.2.10)
Rb = 2.5
Lc = 1mH
Rc = 5
As can be seen in Figure 6.57, the input current, and so also the voltage
at the converter terminals is very distorted, and it appears that there is
an interaction between the lter and the converter. In this instance, as
152

a consequence of the distortion, the operation of the converter fails as
the distorted input voltage drops below that necessary to maintain the
demanded output voltage.
This interaction with the lter can be reduced and removed by lowering
the LC resonant frequency by increasing the capacitor value to 47F,
and as shown in Figure 6.58 it is possible for the converter to operate
correctly with a large enough input lter, however this introduces another problem. One of the objectives with a matrix converter is to be able
to produce an input current with a displacement factor of 1, where the
fundamental component of the input current is in phase with the supply
voltage. Now, when using a lter which does not cause any resonance
issues with the converter, the cut-off frequency is then low enough to
have a signicant effect on the phase of the fundamental component of
the input current with respect to the input voltage which can be seen in
Figure 6.58.
However, it was found that by incorporating the PLL from Section 6.2.2.1
into the converter once again, the problems with interaction with the
input lter disappear, and this is shown in Figure 6.59, which shows
the converter operating with the same input lter as was used in the
initial simulation in Figure 6.57 above, and with both using the same
unbalanced load.
The reason for this behaviour appears to be down to the basic ability
of the converter to generate the output voltages from the instantaneous
input voltages, alongside this, the converter will then produce an input
current in phase with the input voltage. So, if the input voltage seen by
the converter includes a harmonic component, then the converter will go
on to produce a input current in phase with this which also contains this
harmonic component, and this current will then cause further distortion.
So, as the unbalanced harmonic current starts to be drawn in the above
simulation, the input voltage waveform starts to deform as the harmonic
component is below the input lter cut-off frequency. Then as input
voltage deforms, the converter adjusts its switch timing to take this into
account, and by doing this adds this harmonic element into the current
which is being drawn by the converter, thus re-enforcing the voltage
distortion.
However, when the PLL is being used in the circuit, this tracks the fundamental frequency of the input and forces the converter to always perform its calculations based on the ideal PLL waveforms. So whereas
previously, the converter automatically adjusted the switching to take
into account the initial distortion, the converter using the PLL does not,
153

and therefore the does not end up re-enforcing the distortion. The downside of this is that because the converter is no longer tracking the exact set
of input voltages, but rather the ideal PLL set, then any distortion which
is present on the input to the converter can end up passing through
the converter and leading to some distortion in the output voltages.
Figure 6.60 shows the FFT of the output voltage across the load, and
it can be seen that there is slightly more low frequency distortion than in
the ideal case.
6.2.2.4
The Effects of Changing Input Frequency
Back at the beginning of Chapter 1 it was proposed that one possible

application for the 4-leg matrix converter was as part of a generatorbased standalone power supply, where the generator would be driven
by a variable speed motor, and the 4-leg matrix converter providing a
3-phase plus neutral supply. A diagram of this is shown in Figure 1.1.
For this type of generation scheme to be able to work, it needs to be
shown that the converter is able to produce a xed set of output voltages
while the input voltage and frequency is changing, as would happen
when being driven by a variable speed generator.
According to the theory set out in Chapter 5, the converter works by
taking the instantaneous input voltages and calculating the switching
vectors and times based on these. So, irrespective of the input frequency,
and as long as the input voltage meets the voltage transfer requirements,
then a changing input should not upset the operation of the converter.
To prove this a number of simulations were performed using the circuit
as would be implemented in Chapter 7, including the commutation,
PLL and input lter. Initially these simulations were preformed with
a balanced load on the output, but the nal simulation will be used to
show that using an unbalanced load does not effect the outputs.
The initial simulation was to show the effect that a changing input voltage level would have on the converter output, and the results are shown
in Figures 6.61 and 6.62. Figure 6.61 shows the changing input voltage
compared to the output, and as can be seen the output stays constant for
the entire time. Also included in Figure 6.61 is the input current, and
this shows that over the entire range the converter meets the criteria of
having a unity displacement factor. Figure 6.62 shows the output voltage
alongside its FFT, and as can be seen there is no effect from the changing
voltage.
154

The next simulation kept the voltage level steady, but changed the input
frequency instead, with the results being shown in Figures 6.63 and 6.64.
Figure 6.63 shows that as the input frequency changes there is no effect
on the output, and also shows that the converter keeps the input current
in phase with the input voltage. Figure 6.64 shows the output voltage
along with its frequency spectra, and as can be seen there is no real effect
from the changing frequency.
The next step was to combine the previous two simulations such that
both the input voltage and frequency change together, and the results
for this simulation are shown in Figures 6.65 and 6.66. In Figure 6.65
the change in both voltage and frequency can easily be seen in the input,
while the converter still holds the output steady. Also, as before, the
converter keeps the input current in phase with the input voltage. And
as before, Figure 6.66 shows the output voltage alongside its FFT, and
again, there is no effect on this despite both the changing input frequency
and voltage.
The nal simulation in this group was to change the load from being
balanced to being unbalanced. The same unbalanced load as in Section 6.2.2.3 above was used, as detailed by in (6.2.10). The results for this
simulation are shown in Figures 6.67 and 6.68, and once again, despite
the changing input conditions and the unbalanced load, the output of
the converter remains constant, with the fundamental component of the
input current still being in phase with the input voltage.
These results show that the proposed application from Chapter 1 is one
which the 4-leg matrix converter is capable of performing.
With the simulations now complete, it allowed the work to progress
onto the next stage, to build a converter to allow the technique to be
demonstrated.
155
()
156
60.0m
0.0
2.0
4.0
6.0
62.5m
65.0m
67.5m
72.5m
75.0m
77.5m
80.0m
t(s)
82.5m
85.0m
87.5m
90.0m
Figure 6.24: Plot of Control Block Internal Input Variables

50Hz Supply Frequency- 12.5kHz Sampling Frequency
70.0m
92.5m
95.0m
97.5m
0.1
isector
beta_in_bar
beta_in
(): t(s)
()
157
60.0m
0.0
2.0
4.0
6.0
8.0
10.0
12.0
70.0m
75.0m
80.0m
t(s)
85.0m
90.0m
95.0m
Figure 6.25: Plot of Control Block Internal Output Variables
100Hz Demand Frequency- 23 modulation index - 12.5kHz Sampling Frequency
65.0m
0.1
tetra
sign
prism
(): t(s)
()
158
90.0m
0.0
0.2
0.4
0.6
0.8
1.0
91.0m
93.0m
94.0m
95.0m
t(s)
96.0m
97.0m
98.0m
Figure 6.26: Plot of

Control Block Switching State Duty Cycles
92.0m
99.0m
0.1
delta_t
delta_6
delta_5
delta_4
delta_3
delta_2
delta_1
(): t(s)
(V)
159
Figure 6.27: Plot of Demand and Output Phase-neutral Voltage for Leg a
100Hz Demand Frequency- q = 23 - 12.5kHz Sampling Frequency
80.0m 81.0m 82.0m 83.0m 84.0m 85.0m 86.0m 87.0m 88.0m 89.0m 90.0m 91.0m 92.0m 93.0m 94.0m 95.0m 96.0m 97.0m 98.0m 99.0m
t(s)
600.0
300.0
0.0
300.0
600.0
0.1
Vdema
Van
(V): t(s)
(V)
160
90.0m
600.0
400.0
200.0
0.0
200.0
400.0
600.0
91.0m
93.0m
94.0m
95.0m
t(s)
96.0m
97.0m
98.0m
Figure 6.28: Plot of Output Phase Voltage for Leg a referenced to Leg n
92.0m
99.0m
0.1
Van
(V) : t(s)
(V)
161
0.0
0.0
100.0
200.0
300.0
10.0k
15.0k
20.0k
25.0k
f(Hz)
30.0k
35.0k
40.0k
45.0k
50.0k
Figure 6.29: Plot of the FFT of the Output Phase-neutral Voltage on Leg a with respect to Leg n
5.0k
fft(Van)
(V): f(Hz)
(V)
162
82.0m
84.0m
86.0m
88.0m
90.0m
t(s)
92.0m
94.0m
96.0m
98.0m
Figure 6.30: Plot of the 3 Output Phase-neutral Voltages at the load and reference to the load neutral point
80.0m
300.0
200.0
100.0
0.0
100.0
200.0
300.0
0.1
Vcn_load
Vbn_load
Van_load
(V): t(s)
(V)
163
0.0
0.0
100.0
200.0
300.0
10.0k
15.0k
20.0k
25.0k
f(Hz)
30.0k
35.0k
40.0k
45.0k
Figure 6.31: Plot of the FFT of Output Phase-neutral Voltage on Leg a at the load
the
5.0k
50.0k
fft(Van_load)
(V): f(Hz)
164
51.35m
0.0
0.0
0.0
0.0
clk
SCn
SCc
SCb
SCa
SBn
SBc
SBb
SBa
SAn
SAc
SAb
SAa
51.36m
51.38m
51.39m
51.4m
t(s)
51.41m
51.42m
51.43m
51.44m
Figure 6.32: Plot of the Gate Control Signals

100Hz Demand Frequency- q = 0.5 - 12.5kHz Sampling Frequency
51.37m
51.45m
Vn
Vc
Vb
Va
(V): t(s)
(V)
165
82.0m
400.0
200.0
0.0
200.0
400.0
SCa
SBa
SAa
82.2m
82.3m
82.4m
82.5m
t(s)
82.6m
82.7m
82.8m
82.9m
Figure 6.33: Plot showing the Switching of the Voltage on Leg a between the Input Phases
82.1m
83.0m
Va
VC
VB
VA
(V) : t(s)
(V)
166
90.0m
400.0
200.0
0.0
200.0
400.0
92.0m
93.0m
94.0m
95.0m
t(s)
96.0m
97.0m
98.0m
99.0m
Figure 6.34: Plot of Output Phase Voltages for Leg a referenced to the supply neutral
91.0m
0.1
Va
(V) : t(s)
(V)
167
400.0
200.0
0.0
200.0
400.0
60.0m
20.0
15.0
10.0
5.0
0.0
5.0
10.0
15.0
20.0
68.0m
72.0m
76.0m
80.0m
t(s)
84.0m
88.0m
92.0m
Figure 6.35: Plot of the

Input Current and Voltage for Supply Phase A
64.0m
96.0m
100m
VA
(V) : t(s)
IA
(A): t(s)
(A)
(A)
168
0.0
2.0
4.0
6.0
8.0
10.0
0.0
5.0k
15.0k
20.0k
25.0k
f(Hz)
30.0k
35.0k
40.0k
45.0k
Figure 6.36: Plot of the FFT of Input Current for Supply Phase A
10.0k
50.0k
fft(IA)
(A): f(Hz)
(A)
169
0.0
10.0
20.0
30.0
0.0
f(Hz)
10.0k
15.0k
Figure 6.37: Plot of the FFT of Input Current for Supply Phase A scaled as a % of the fundamental
5.0k
fft(IA)
(A): f(Hz)
(A)
170
60.0m
30.0
20.0
10.0
0.0
10.0
20.0
30.0
70.0m
75.0m
80.0m
t(s)
85.0m
90.0m
95.0m
Figure 6.38: Plot of the Output Currents showing an Unbalanced Load
65.0m
0.1
Ic
Ib
Ia
(A) : t(s)
(V)
(V)
(V)
171
0.0
0.0
100.0
200.0
300.0
0.0
100.0
200.0
300.0
0.0
100.0
200.0
300.0
1.0k
3.0k
4.0k
5.0k
6.0k
7.0k
8.0k
f(Hz)
9.0k
10.0k
11.0k
12.0k
13.0k
14.0k
Figure 6.39: Plot of the FFT of Output Phase-neutral Voltages with an Unbalanced Load
2.0k
15.0k
fft(Vcn)
fft(Vbn)
fft(Van)
(V): f(Hz)
(V)
172
400.0
200.0
0.0
200.0
400.0
65.0m
70.0m
75.0m
80.0m
t(s)
85.0m
90.0m
95.0m
Figure 6.40: Plot of the Input Current and Voltage for Supply Phase A with an Unbalanced Load
60.0m
20.0
15.0
10.0
5.0
0.0
5.0
10.0
15.0
20.0
100m
VA
(V) : t(s)
IA
(A): t(s)
(A)
(A)
173
0.0
1.0
2.0
3.0
4.0
5.0
0.0
1.0k
3.0k
4.0k
5.0k
6.0k
7.0k
8.0k
f(Hz)
9.0k
10.0k
11.0k
12.0k
13.0k
14.0k
Figure 6.41: Plot of the FFT of Input Current for Supply Phase A with an Unbalanced Supply
2.0k
(250.0, 0.80407)
(150.0, 0.78378)
15.0k
fft(IA)
(A): f(Hz)
(V)
(V)
(V)
174
0.0
50.0
0.0
100.0
150.0
200.0
0.0
50.0
100.0
150.0
200.0
0.0
50.0
100.0
150.0
200.0
3.0k
4.0k
5.0k
6.0k
7.0k
8.0k
f(Hz)
9.0k
10.0k
11.0k
12.0k
13.0k
14.0k
peak
Vin
15.0k
100Hz - 12.5kHz Sampling Frequency
Figure 6.42: Plot of FFT of the 3 Output Phase-neutral Voltages for Unbalanced Demands
2.0k
Vdema = Vin peak 100Hz, Vdemb = Vin peak 200Hz, Vdemb =
1.0k
fft(Vcn)
fft(Vbn)
fft(Van)
(V): f(Hz)
175
0.0
50.0
0.0
100.0
5.0k
10.0k
15.0k
20.0k
f(Hz)
25.0k
30.0k
35.0k
40.0k
45.0k
50.0k
fft(Van)
(V): f(Hz)
Figure 6.43: Plot of the FFT of the Output Phase-neutral Voltage on Leg a with respect to Leg n using the Two Zero Switching
Sequence
(V)
150.0
176
0.0
50.0
0.0
100.0
5.0k
10.0k
15.0k
20.0k
25.0k
f(Hz)
30.0k
35.0k
40.0k
45.0k
50.0k
fft(Van)
(V): f(Hz)
Figure 6.44: Plot of the FFT of the Output Phase-neutral Voltage on Leg a with respect to Leg n using the Three Zero Switching
Sequence
(V)
150.0
177
0.5
400.0
200.0
0.0
200.0
0.502
0.504
0.506
0.508
0.51
t(s)
0.512
0.514
0.516
0.518
0.52
VA Sampled
VA Input
(V) : t(s)
Figure 6.45: Plot of the Supply Voltage alongside the Sampled Voltage showing the Processing Delay within the Converter
50Hz Input Frequency - 12.5kHz Sampling Frequency
(V)
400.0
(V)
178
0.507
0.508
0.509
0.51
t(s)
0.511
0.512
0.513
0.514
VA Calc Delta
VA Input
Figure 6.46: Plot of the Supply Voltage alongside the Sampled Voltage showing the Processing Delay Compensation
0.506
400.0
200.0
0.0
200.0
400.0
(V) : t(s)
179
0.0
0.0
50.0m
0.1
0.15
0.2
0.25
0.0
50.0m
0.1
0.15
0.2
100.0 200.0 300.0 400.0 500.0 600.0 700.0 800.0 900.0 1.0k 1.1k
f(Hz)
1.2k
1.3k
1.4k
1.5k
1.6k
1.7k
1.8k
1.9k
2.0k
fft(Van) Delta Comp
% : f(Hz)
fft(Van) No comp
% : f(Hz)
Figure 6.47: Plot of the FFT of the Output Voltage, Van, with and and without compensation for the processing delay using the
Delta method
100Hz Output Frequency - 12.5kHz Sampling Frequency
0.25
(V)
(V)
180
0.502
0.504
0.506
0.508
0.51
t(s)
0.512
0.514
0.516
0.518
0.52
VA PLL
(V) : t(s)
VA Noisy
(V) : t(s)
Figure 6.48: Plot of the noisy Input Voltage, VA, alongside the PLL tracked fundamental frequency output used by the
converter
0.5
500.0
0.0
500.0
500.0
0.0
500.0
181
0.0
0.5
150.0
100.0
50.0
0.0
50.0
100.0
150.0
0.0
0.2
0.4
0.6
0.8
1.0k
0.505
2.0k
0.51
3.0k
4.0k
0.515
5.0k
0.52
6.0k
7.0k
0.525
t(s)
8.0k
f(Hz)
9.0k
0.53
10.0k
0.535
11.0k
12.0k
0.54
13.0k
15.0k
0.545
14.0k
0.55
Van Delta Noisy
(V) : t(s)
16.0k
fft(Van) Delta Noisy
% : f(Hz)
Figure 6.49: Plot of the Output Voltage, Van, and its Spectra showing the effect of Noise when using the Delta method of delay
compensation
(V)
1.0
(V)
0.0
182
1.0k
0.505
2.0k
0.51
3.0k
4.0k
0.515
5.0k
0.52
6.0k
7.0k
0.525
t(s)
8.0k
f(Hz)
9.0k
0.53
10.0k
0.535
11.0k
12.0k
0.54
13.0k
15.0k
0.545
14.0k
0.55
Van PLL Noisy
(V) : t(s)
16.0k
fft(Van) PLL Noisy
% : f(Hz)
Figure 6.50: Plot of the Output Voltage, Van, and its Spectra showing the effect of Noise when using the PLL for delay
compensation
0.5
150.0
100.0
50.0
0.0
50.0
100.0
150.0
0.0
0.2
0.4
0.6
0.8
1.0
183
0.0
0.0
50.0m
0.1
0.15
0.2
0.25
0.0
50.0m
0.1
0.15
0.2
100.0 200.0 300.0 400.0 500.0 600.0 700.0 800.0 900.0 1.0k 1.1k
f(Hz)
1.2k
1.3k
1.4k
1.5k
1.6k
1.7k
1.8k
1.9k
2.0k
fft(Van) FPGA
% : f(Hz)
fft(Van) No comp
% : f(Hz)
Figure 6.51: Plot of the FFT of the Output Voltage, Van, with and without the truncation effect of the FPGA minimum step size
0.25
184
0.0
0.0
50.0m
0.1
0.15
0.2
0.25
0.0
50.0m
0.1
0.15
0.2
100.0 200.0 300.0 400.0 500.0 600.0 700.0 800.0 900.0 1.0k 1.1k
f(Hz)
1.2k
1.3k
1.4k
1.5k
1.6k
1.7k
1.8k
1.9k
2.0k
fft(Van) FPGA Comp
% : f(Hz)
fft(Van) No comp
% : f(Hz)
Figure 6.52: Plot of the FFT of the Output Voltage, Van, showing the original along with the output which is compensated for
the truncation effect of the FPGA minimum step size
0.25
(V)
185
0.0
0.51
0.515
0.52
100.0 200.0 300.0 400.0 500.0 600.0 700.0 800.0 900.0
0.505
1.0k
f(Hz)
0.525
t(s)
1.1k
1.2k
0.53
1.3k
1.4k
0.535
1.5k
1.6k
0.54
1.7k
1.8k
0.545
1.9k
2.0k
fft(Van)
% : f(Hz)
0.55
Van
(V) : t(s)
Figure 6.53: Plot of the Output Voltage, Van, and its Spectra, showing the combined effect of the different types of
compensation
0.0
50.0m
0.1
0.15
0.2
0.25
0.5
150.0
100.0
50.0
0.0
50.0
100.0
150.0
SCa2
SCa1
SBa2
SBa1
SAa2
SAa1
SBa
SAa
186
0.50015
400.0
200.0
0.0
200.0
400.0
0.5001505
0.500151
0.5001515
0.500152
t(s)
0.5001525
0.500153
0.5001535
0.500154
VB Input
VA Input
Va Output
(V) : t(s)
Figure 6.54: Plot showing the switching sequence used for commutation going from a lower to a higher voltage input phase
(V)
SCa2
SCa1
SBa2
SBa1
SAa2
SAa1
SCa
SBa
187
0.500142
400.0
200.0
0.0
200.0
400.0
0.5001425
0.500143
0.5001435
0.500144
t(s)
0.5001445
0.500145
0.5001455
0.500146
VC Input
VB Input
Va Output
(V) : t(s)
Figure 6.55: Plot showing the switching sequence used for commutation going from a lower to a higher voltage input phase
(V)
(V)
188
0.0
0.0
50.0m
0.1
0.15
0.2
0.25
0.5
150.0
100.0
50.0
0.0
50.0
100.0
150.0
0.51
0.515
0.52
1.0k
f(Hz)
0.525
t(s)
1.1k
1.2k
0.53
1.3k
1.4k
0.535
1.5k
1.6k
0.54
1.7k
1.8k
0.545
1.9k
Figure 6.56: Plot of the FFT of the Output Voltage, Van, comparing the commutated output to the ideal
100.0 200.0 300.0 400.0 500.0 600.0 700.0 800.0 900.0
0.505
2.0k
fft(Van)
% : f(Hz)
0.55
Van - Com
(V) : t(s)
189
(A)
0.5
1.0k
0.0
1.0k
500.0
0.0
500.0
0.505
0.51
0.515
0.52
0.525
t(s)
0.53
0.535
0.54
0.545
0.55
VA Converter
(V) : t(s)
IA Supply
(A) : t(s)
VA Supply
(V) : t(s)
Figure 6.57: Plot of Input Phase A Supply Voltage and Current, along with the voltage seen at the converter, when using a
1mH/33F Input Filter with no PLL
100.0
0.0
(V)
(V)
100.0
190
40.0
20.0
0.0
0.5
500.0
0.0
500.0
500.0
0.0
500.0
0.505
0.51
0.515
0.52
0.525
t(s)
0.53
0.535
0.54
0.545
0.55
VA Converter
(V) : t(s)
IA Supply
(A) : t(s)
VA Supply
(V) : t(s)
1mH/47F Input Filter with no PLL
(A)
20.0
(V)
(V)
40.0
191
(V)
0.5
500.0
0.0
500.0
20.0
0.0
20.0
0.505
0.51
0.515
0.52
0.525
t(s)
0.53
0.535
0.54
0.545
0.55
VA Converter
(V) : t(s)
IA Supply
(A) : t(s)
VA Supply
(V) : t(s)
1mH/33F Input Filter using a PLL
500.0
0.0
(A)
(V)
500.0
(V)
Mag(V/Hz)
192
0.0
1.0k
2.0k
0.505
3.0k
0.51
4.0k
5.0k
0.515
6.0k
0.52
7.0k
8.0k
f(Hz)
0.525
t(s)
9.0k
0.53
10.0k
11.0k
0.535
12.0k
0.54
13.0k
14.0k
0.545
15.0k
fft(Van)
Mag(V/Hz) : f(Hz)
0.55
Van
(V) : t(s)
Figure 6.60: Plot of Output Voltage, Van, along with its Spectra, when using a 1mH/33F Input Filter using a PLL
0.0
10.0
20.0
30.0
40.0
50.0
0.5
60.0
40.0
20.0
0.0
20.0
40.0
60.0
193
(A)
0.15
400.0
200.0
0.0
200.0
400.0
400.0
200.0
0.0
200.0
400.0
0.175
0.2
0.225
0.25
0.275
0.3
0.325
0.35
t(s)
0.375
0.4
0.425
0.45
0.475
0.5
0.525
0.55
VA Converter
(V) : t(s)
IA Supply
(A) : t(s)
VA Supply
(V) : t(s)
Figure 6.61: Plot of Input Phase A Supply Voltage and Current, along with the voltage seen at the converter, with the peak
input voltage decreasing from 340V to 250V
20.0
0.0
(V)
(V)
20.0
(V)
194
0.0
25.0
50.0
75.0
0.0
100.0
125.0
150.0
0.15
150.0
100.0
50.0
0.0
50.0
100.0
0.2
0.225
0.25
0.275
0.3
0.325
100.0 200.0 300.0 400.0 500.0 600.0 700.0 800.0 900.0
0.175
1.0k
f(Hz)
0.35
t(s)
1.1k
0.375
1.2k
0.4
1.3k
1.4k
0.425
1.5k
0.45
1.6k
0.475
1.7k
0.5
1.8k
1.9k
0.525
2.0k
fft(Van)
(V) : f(Hz)
0.55
Van
(V) : t(s)
Figure 6.62: Plot of Output Voltage, Van, along with its Spectra, with the peak input voltage decreasing from 340V to 250V
(V)
150.0
195
(A)
0.15
400.0
200.0
0.0
200.0
400.0
400.0
200.0
0.0
200.0
400.0
0.175
0.2
0.225
0.25
0.275
0.3
0.325
0.35
t(s)
0.375
0.4
0.425
0.45
0.475
0.5
0.525
0.55
VA Converter
(V) : t(s)
IA Supply
(A) : t(s)
VA Supply
(V) : t(s)
Figure 6.63: Plot of Input Phase A Supply Voltage and Current, along with the voltage seen at the converter, with the input
frequency increasing from 50Hz to 100Hz
12.5kHz Sampling Frequency
20.0
0.0
(V)
(V)
20.0
(V)
196
0.0
25.0
50.0
75.0
0.0
100.0
125.0
150.0
0.15
150.0
100.0
50.0
0.0
50.0
100.0
0.2
0.225
0.25
0.275
0.3
0.325
100.0 200.0 300.0 400.0 500.0 600.0 700.0 800.0 900.0
0.175
1.0k
f(Hz)
0.35
t(s)
1.1k
0.375
1.2k
0.4
1.3k
1.4k
0.425
1.5k
0.45
1.6k
0.475
1.7k
0.5
1.8k
1.9k
0.525
2.0k
fft(Van)
(V) : f(Hz)
0.55
Van
(V) : t(s)
Figure 6.64: Plot of Output Voltage, Van, along with its Spectra, with the input frequency increasing from 50Hz to 100Hz
(V)
150.0
197
(A)
0.15
400.0
200.0
0.0
200.0
400.0
400.0
200.0
0.0
200.0
400.0
0.175
0.2
0.225
0.25
0.275
0.3
0.325
0.35
t(s)
0.375
0.4
0.425
0.45
0.475
0.5
0.525
0.55
VA Converter
(V) : t(s)
IA Supply
(A) : t(s)
VA Supply
(V) : t(s)
input voltage decreasing from 340V to 250V while the input frequency increases from 50Hz to 100Hz
20.0
0.0
(V)
(V)
20.0
(V)
198
0.0
25.0
50.0
75.0
0.0
100.0
125.0
150.0
0.15
150.0
100.0
50.0
0.0
50.0
100.0
0.2
0.225
0.25
0.275
0.3
0.325
100.0 200.0 300.0 400.0 500.0 600.0 700.0 800.0 900.0
0.175
1.0k
f(Hz)
0.35
t(s)
1.1k
0.375
1.2k
0.4
1.3k
1.4k
0.425
1.5k
0.45
1.6k
0.475
1.7k
0.5
1.8k
1.9k
0.525
2.0k
fft(Van)
(V) : f(Hz)
0.55
Van
(V) : t(s)
while the input frequency increases from 50Hz to 100Hz
(V)
150.0
199
40.0
20.0
0.0
0.15
500.0
0.0
500.0
500.0
0.0
500.0
0.175
0.2
0.225
0.25
0.275
0.3
0.325
0.35
t(s)
0.375
0.4
0.425
0.45
0.475
0.5
0.525
0.55
VA Converter
(V) : t(s)
IA Supply
(A) : t(s)
VA Supply
(V) : t(s)
input voltage decreasing from 340V to 250V while the input frequency increases from 50Hz to 100Hz, driving an unbalanced
load
(A)
20.0
(V)
(V)
40.0
(V)
200
0.0
10.0
20.0
30.0
40.0
50.0
60.0
0.0
0.15
75.0
50.0
25.0
0.0
25.0
50.0
0.2
0.225
0.25
0.275
0.3
0.325
100.0 200.0 300.0 400.0 500.0 600.0 700.0 800.0 900.0
0.175
1.0k
f(Hz)
0.35
t(s)
1.1k
0.375
1.2k
0.4
1.3k
1.4k
0.425
1.5k
0.45
1.6k
0.475
1.7k
0.5
1.8k
1.9k
0.525
2.0k
fft(Van)
(V) : f(Hz)
0.55
Van
(V) : t(s)
while the input frequency increases from 50Hz to 100Hz, driving an unbalanced load
(V)
75.0
C HAPTER 7
Matrix converter design and

construction
7.1
Introduction and overview
This chapter will discuss the construction of a 4-leg matrix converter in

order to be able to demonstrate that both the theoretical and simulation
work carried out in Chapters 5 and 6 is correct. As such, it should be
noted that the converter has been built with a simple open loop control
system and is initially based upon the common 3x3 matrix converter
which is in use at the University of Nottingham, which was then extended to become the 4-leg (3x4) matrix converter. Because the main
scope of this work was to derive the theory behind the 4-leg matrix
converter and its basic operation, this physical converter is the proof
of the concept, and as such any more complex control system would be
outside the scope of this work.
The proposed matrix converter would be designed to meet the following
specication:
Switching Frequency: 12.5KHz
Input Voltage: 415Vac
Input Frequency: 50Hz
Output Voltage: 0 -
3/2Vin
Output Frequency: 0 - 400Hz

Maximum Output Power: 10kW
201
C HAPTER 7: M ATRIX CONVERTER DESIGN AND CONSTRUCTION

The basic circuit of a matrix converter is essentially xed, in that it is a
matrix of bi-directional switches which connect a set of inputs directly to
a set of outputs, although the layout and type of construction can differ
widely. With the power levels involved with this build being relatively
small, it was possible to build this converter using a large multi-layered
printed circuit board, and this allowed the design of this converter to
based on an existing University of Nottingham design. As such, a large
amount of the circuit design itself had already been completed, and so
the major part of this work was in then going on to modify the existing
circuit layout to accommodate the extra output leg.
Control Circuit
Power Circuit
FPGA
DSP
Control
PC
Load
Figure 7.1: Broad Overview of the different areas in a Matrix Converter

Figure 7.1 shows how the system ts together as a whole, with each of
the major components shown, and this shows that the matrix converter
is easily separated into two main areas:
The power circuit is the main physical bulk of the converter, it
includes the printed circuit board (PCB) which holds the switching
devices and their respective gate drive circuits, the along with the
current and voltage sensing.
The control circuit is however the more complex of the two, it is
based around a digital signal processor (DSP) board, which connects through to the power circuit through a eld programmable
gate array (FPGA) daughter-board, and is also connected to a PC
to allow the converter to be controlled.
This section will now take a look at each of these areas, breaking each
one down into its major components and going into detail on the design
and operation where required.
202
7.2
Matrix Converter Power Circuit
Gate signals
from FPGA
Gate Drive
Circuit
Gate Drive
Circuit
Gate Drive
Circuit
Gate Drive
Circuit
Gate Drive
Circuit
Gate Drive
Circuit
Gate Drive
Circuit
Gate Drive
Circuit
Gate Drive
Circuit
Voltage
Sense
Gate Drive
Circuit
Gate Drive
Circuit
Gate Drive
Circuit
415V
Voltage
Sense
Sense Signals
to FPGA
Current Sense
and direction
Current Sense
and direction
Current Sense
and direction
Current Sense
and direction
Load
Figure 7.2: Block Diagram of the Matrix Converter Power Circuit

Figure 7.2 shows the general overview of this circuit, and it can be seen
that the core of the circuit is very simple, it consists of 12 bi-directional
switches arranged in three legs of four switches. For each of these switches
there is a dedicated isolated gate drive circuit, and then the output of
each of these legs passes through a current sense circuit, before being
output to the load. Additionally, there are a pair of back to back diode
rectiers and clamp circuit, while the input voltage has a separate sense
circuit as well.
The bi-directional switches
Gate drive circuits for the switches
Voltage and current sensing
Circuit protection
As stated above, within the PEMC group at the University of Nottingham there already existed a working design for a 3x3 matrix converter,
and with the 4-leg matrix converter being a extension of the standard
3x3 matrix, it provided an excellent base for the design of this converter.
This matrix design is based around a large multi-layered PCB, using
self-contained switching packs with isolated gate drive circuits, and also
including the required sensing and protection circuits for the converter.
As such the details in the sections below are a description of the need
for, and operation of that element.
203

The following subsections will look in more detail at each of the individual parts of this circuit.
7.2.1
Devices
The bi-directional switches required by this converter need to be capable

of passing current in both directions when turned on, and yet blocking
current in both directions when turned off. While the required behaviour
is possible by using GTOs, the switching times required by this converter
means they are not a practical solution in this instance. For the switching
speeds required in this circuit, where the overall switching frequency is
12.5kHz, but due to the modulation scheme used the devices themselves
switch at 25kHz there the two types of device which it would be possible
to use, and these are eld effect transistors (FETs) and IGBTs, but neither
of which fulls the bi-directional nature of the switch requirements on
its own.
However, by using FETs in a back to back arrangement, so the drains
of the devices are connected together, this allows a pair of FETs to exhibit the required behaviour, however, while this situation may work in
theory, the reverse conduction characteristics of both the body diodes
in the FETs are just not as good as the forward conduction of a discrete diode, and so for this reason anti-parallel diodes are used alongside them. The arrangement for using IGBTs in the directional switch
is exactly the same, although with no body diode, they require the antiparallel diode to operate in the required way. Finally, due to the power
level that this converter is being designed for IGBTs are favoured over
FETs due to their superior switching and conduction losses. Figure 7.3
shows a circuit diagram of one of these switches.
Figure 7.3: A Single Bi-directional Switch

The requirements for the elements of the bi-directional switch in this
circuit are the following:
204

Reverse breakdown voltage: >600V
Forward IGBT Current: over 30A
Forward Diode Current: over 30A
The actual devices used for the converter are the Semikron SK60GM123,
which are a pair of IGBTs with anti-parallel diodes in a common emitter
conguration, as shown in Figure 7.3, all held in a single package. These
are a standard device which is used within the PEMC Group at the
University of Nottingham, and are the same devices as those used in the
standard 3x3 matrix converter that this converter is based upon. These
devices are rated at 1200V and 50A, and so meet the requirements for this
converter. The data-sheet for these devices can be found in Appendix B.
7.2.2
Gate Drive Circuit
There are a number of requirements that need to be considered for a gate

drive circuit for an IGBT, as well as a specic requirement for a matrix
converter:
Current drive
Switching speed
Isolation
As with all switching power converters, the main switching devices are
only ever operated in either their fully on or fully off states, with the
gate drive circuit designed to switch between the two states as quickly as
possible. If we rst consider the requirements to fully turn an IGBT on,
this requires that the gate-emitter voltage is set to above the threshold
voltage level, and for the Semikron SK60GM123 devices used in this
project that level is typically 5.5V. However, as there is an inherent capacitance in the gate of an IGBT which needs to be charged in order for
the gate emitter voltage to rise. It is therefore a good idea to set the gate
voltage higher than is required in order to charge this capacitance more
quickly, and thus switch the device on as quickly as possible. To allow
this fast switching the gate drive needs to also be able to supply enough
current at this higher voltage, in the short period of time that is required
for the switching.
205

Alongside the need to switch on the device as quickly as possible is
the need to switch it off as quickly as possible as well, but as well as
needing to discharge the gate capacitance there is an extra complication
in switching off an IGBT, and this is the tail current. This current comes
about by the need to remove electrons from the gate/base of the IGBT as
the device switches off in order to stop the device from conducting, and
the device can continue to conduct as long as a tail current is present. So,
to make sure the device turns off as quickly as possible, the gate voltage
is taken negative with respect to the emitter.
Isolated
Ux+15V
+5V
Ux+15V
+5V
U1GND
GND
UxGND
Gate_signal_a
Gate drive
to switch a
GND
GND
U1GND
U1GND
Ux-15V
Ux-15V
UxGND
Ux+15V
+5V
Ux+15V
+5V
U1GND
GND
UxGND
Gate_signal_b
Gate drive
to switch b
GND
GND
U1GND
U1GND
Ux-15V
Ux-15V
UxGND
Figure 7.4: Circuit Diagram of the Gate Drive Circuit for a single
Bi-directional Switch
For the gate drive circuit for this project, the IGBT gate is driven from
+15V and -15V sources. Figure 7.4 shows the circuit diagram for a gate
drive for a single bi-directional switch. As can be seen there are a pair
of bipolar transistors which are driven in anti-phase to switch the gate
circuit between the two voltages, and the gate resistor is used to control
the maximum current fed into/drawn from the gate.
Alongside the specic requirements for driving the IGBT itself, the matrix converter also has specic requirement for its gate drives, and that is
that each of the gate drives needs to be isolated. This is because the gate
drive circuits must always reference the emitter voltage of the devices,
206

and as this voltage can be tied to any input phase, or even just be oating
when a device is turned off, the gate drive needs to be able to oat as
well. To achieve this the entire gate drive circuit, with its respective
15V rails, is isolated, and these can be seen in Figure 7.4 as the optoisolated driver for the gate signal, and the isolated power supply for the
15V rails.
For this circuit, the gate drive signal comes in from the FPGA control
board, this then gets inverted by a logic gate before driving the optoisolated driver. The output signal from this device is then used to drive
a pair of transistors connected between the +15V and -15V rails. The
output from this drives the IGBT gate through a small resistor.
7.2.3
Output Current Sensing
As this converter is going to be utilising the 4-step commutation sequence, as examined in Section 4.3 above, the FPGA, which generates the
control signals, needs to know at any switching instant which direction
the current is owing through each bi-directional switch. To achieve
this a current direction sensing circuit is built into the output of each
switching leg, and is made up of a pair of anti-parallel diodes. Each
pair of anti-parallel diodes are used to monitor the current direction in
their particular switching leg, with the voltage across the diodes being
positive for current ow in one direction, and negative in the other depending on which diode is conducting. This voltage is then fed into a
comparator to produce a logic level signal that is capable of being fed
back, through an isolation barrier, to the FPGA. This logic level is then
used to determine the commutation sequence required when switching
between output states. By using the diodes in this way it is possible to
detect down to very low current values so ensuring that the optimum
commutation sequence is used. Below these current values where the
circuit stops working, the current levels are so small that it makes no
real difference which commutation sequence is used.
Alongside the current direction sensing, there is also an inline current
transducer which is used for monitoring the output current from each
converter leg. This uses a device from a company called LEM which
has an isolated output which can then be fed directly out to the A/D
converter circuits on the FPGA card. These signals are then used by the
DSP to primarily protect the power circuit against any prolonged overcurrent conditions, although in more complex control schemes these currents can be used as part of the control loop.
207

Figure 7.5 shows the current sensing circuit that is used for each output
leg.
Input
from
Converter
Isolated
+5V
xcd+15V
+5V
Vcc
Current
direction
Vo
Vgnd
xcd-15V
GND
GND
Current
transducer
CTu
+15
+15V
-15
-15V
Output
to
load
Figure 7.5: Circuit Diagram of the Current Sense Circuit
7.2.4
Input Voltage Sensing
In order for Space Vector Modulation to work it is vital to know both the
direction and phase of the input voltage space vector, and to do this we
need to know each of the three input voltages. This is achieved in this
instance by the use of LEM voltage transducers. Even though the values
of all three input phases needs to be known, from the circuit diagram in
Figure 7.6, it can be seen that there are only two voltage transducers, and
these are being used to measure the two line-to-line voltages VAB and
VBC . The reason that the voltage sensing is performed in this manner is
that there is no neutral line at the input side of the converter, as the idea
behind this type of converter is to be able to generate the 3-phase plus
neutral from a balanced 3-phase supply.
So, as it is known that the input phases will form a three phase set where
VA + VB + VC = 0
(7.2.1)
then, if VAB is known and is dened by 7.2.2

VAB = VA VB
and VBC is known and is dened by 7.2.3
208
(7.2.2)

Rmeas
Voltage
transducer
Vrs
+15
+15V
-15
-15V
S'meas
Smeas
Smeas
Voltage
transducer
Vst
+15
+15V
-15
-15V
T'meas
Tmeas
Figure 7.6: Circuit Diagram of the Voltage Sensing Circuit
VBC = VB VC
(7.2.3)
then re-arranging 7.2.3 and substituting into 7.2.1 gives

VA + 2VB VBC = 0
(7.2.4)
Now doing the same with 7.2.2 gives

3VA + 2VAB VBC = 0
(7.2.5)
and by re-arranging it then gives

VA =
1
(2VAB VBC )
3
(7.2.6)
From 7.2.6 it can be seen that by just knowing these two line-to-line
voltages it is possible to calculate one of the line-to-neutral voltages, and
from there the other two line-to-neutral voltages are trivial to solve, such
that

VA

VB =
VC
1
3
(2VAB VBC )
VA VAB
VA VB
209
(7.2.7)

So, the two line-to-line voltages are all that is required to dene the
input space vector, and the output from both of these sensors is then
fed directly out to the A/D converter circuits on the FPGA card.
7.2.5
Clamp Circuit
This is a relatively simple protection circuit which gives the input and
output currents a freewheel path in the case of a device not being switched
correctly, and is the parallel diode bridge as discussed in Section 6.2.2.3.
While it helps the converter during normal commutation, it also provides some protection for the matrix converter if problems arise a commutation by operating as a voltage clamp. The circuit layout for this
is shown in Figure 7.7, and as can be seen, it is a pair of back to back
diode rectiers, one connected to the input and the other to the output.
The rectied output from these bridges is then connected to a pair of
series capacitors. If one of the switches fails for some reason, then any
current in that input or output phase will be able to ow through its
respective diode in the clamp and then into/through the capacitor. This
stops any large increase in voltage which could occur due to inductances
within the input and output circuits if an output leg was allowed to go
open circuit. If this is just a problem with a single commutation the
time would be small and so the associated voltage increase would also
be small, but if there is a larger problem then the increase in capacitor
voltage can then be used to trigger a trip within the control circuit and
the converter can be stopped. Any currents still owing in the input and
output legs can then be allowed to safely freewheel through the clamp
circuit. The associated resistor is there to provide a discharge path for the
capacitor, so that when the converter is tripped the freewheeling energy
can be safely dissipated.
Included in this circuit is another LEM voltage transducer which is used
to sense the clamp circuit voltage, the output of which is fed into a comparator. Once the clamp voltage rises above the comparators reference
voltage the output goes high and this signal is fed back into the FPGA
board and thus the DSP to enable it to stop the converter.
7.2.6
PCB Design and implementation
This is a multi-layer PCB which along with the top and bottom signal
layers also has four internal layers, three of which are shared between
the three input and three output phases, with an input and output phase
210

DC Clamp+
Voltage
transducer
M
+15
3-Phase
Input from
mains supply
+15V
-15
-15V
4-Phase
Input from
Converter output
DC Clamp-
+5V
+5V
GND
GND
GND
GND
Figure 7.7: Circuit Diagram of the Voltage Clamp used for Converter
Protection
per layer, and then another layer to allow a separate ground plane to
be used. By using the internal layers in this way, it allows as large an
amount of copper as possible to be used for connecting the phases to
and from the devices. There is the obvious advantage with having as
much copper as possible as it keeps the track resistance down and allows
higher power levels to be used, but this also has the additional benet
of allowing the tracks to be as wide as possible and this helps to reduce
the stray inductance in the design. While having any stray inductance
in the output circuit is not really an issue due to the inductors on each of
the output phases, keeping the inductance of the input circuits as low as
possible is an advantage. This is because of the nature of the switching,
where only two input phases are usually conducting, and so the input
currents are discontinuous. As such any stray inductance could cause
spikes on the input voltage.
The layout for this board is an extension of the layout for the 3x3 matrix
circuit. This layout was arranged with the input phases being connected
to the switches in columns down the board, and had the output legs
connected across the board. This arrangement was kept, and allowed
the 4th leg to be placed along the bottom edge of the PCB.
7.2.7
Input Filter
As the simulations in Section 6.2.2.3 demonstrated, the presence of impedance

in the power supply to the converter the deviates from the theoretical
ideal and as such the converter requires a number of input capacitors to
compensate for this. These capacitors combine with the supply induc211

tance to also form the lter which is required to prevent any switching
frequency components of the input current from reaching the supply,
and so causing further distortion and problems from other users of that
supply.
For this converter, the lter will simply use the supply impedance coupled with a set of three input capacitors, with the arrangement demonstrated in Figure 7.8. This same setup was used as part of the simulations, and assumes a supply impedance of approximately 1mH, and will
then use 3F capacitors to produce a resonant/cut-off frequency of just
under 3kHz.
L
C
Supply
Converter
L
C
Figure 7.8: Circuit Diagram of the Supply and Input Filter for the 4-Leg
Matrix Converter
Choosing a cut-off frequency at this point means that it is still well below
the switching frequency being used and so be able to effectively lter
it, while also trying to keep the phase shift of the lter as close to zero
over the entire input frequency range, up to 400Hz. This last point is
important as it allows the converter to have a input displacement factor
as close to unity as possible.
7.2.8
Output Inductors and Load
The nal part of the power section is the load, and this itself is broken
up into two parts, the output inductors and the load resistance.
For a matrix converter to operate it ideally requires some inductance on
each of the 4 output legs, thus giving it the current stiff characteristic.
The actual inductors used for the converter are a set of 8mH 3-phase
inductors attached to the three main output legs, with a pair of 4mH
inductors connected in series on the neutral leg. This arrangement was
limited in this way because there were no 4-phase inductors available
within the PEMC test lab, as 4-phase output inductors are relatively
212

uncommon. While this is not the ideal setup, it has been tested and
shown to be acceptable for use with this converter.
The outputs from these inductors are then taken on and connected to
the load, which for this converter it is a relatively simple setup, initially
consisting of a star connected set of three 10 resistors, with the output
legs connected to the star points, while the neutral is connected to the
centre point.
7.3
7.3.1
Matrix Converter Control

Digital Signal Processor
Due to the relatively intensive nature of the mathematics that is required

for the operation of a matrix converter every switching cycle, and with
the short time-scales that are available for performing these calculations,
a fast processor is required and a digital signal processor (DSP), with its
dedicated maths functions and parallel execution paths, is ideally suited
to this task. In this case one of the Texas Instruments TMS320C67xx
family of digital signal processors has been chosen. While there are other
processors available, this family of processors was chosen as it is widely
used within the University of Nottingham PEMC research group, and
this then also allowed the use of a previously designed FPGA daughter
board. This daughter board was necessary as even though the DSP is
fast it is still not fast enough to be able to achieve the required resolution
for the output of the switching signals to the IGBT gate drives.
In this instance the TMS320C6713 processor was used, this is because,
at the time, this was the latest generation of the TMS320C67x family. To
allow a quick and relatively easy development process the processor was
bought as part of an evaluation kit made by Spectrum Digital. This kit
has the processor mounted on a PCB with all the required memory along
with the associated peripherals that allow it to be connected directly to
a PC and used with the Texas Instruments development environment,
Code Composer Studio. Not only does this package allow the software
to be written and compiled specically for this processor, but also that
the processor can be simulated within the development environment
prior to being run directly on the hardware.
This processor runs at a clock speed of 225MHz, with 4 clock cycles
per instruction cycle, then with a sampling frequency of 12.5kHz for the
converter, this gives a maximum of 4500 instruction cycles per sampling
213

period.
4-Leg Matrix Converter DSP Software
main.c
Initialise DSP hardware

& configure memory interfaces
Initialise peripherals
& calculate ADC offset
Initialise FPGA &
start external trigger
On external interrupt
from the FPGA(12.5kHz)
matrix.c
interface.c
Initialise
communications
Start A/D Conversion

& then read results
Calcualte input voltage
space vector
Read PC Message
Process PC Message
Check sync with

PLL
Start Drive
Calcualte input space

vector from PLL output
Stop Drive
Calcualte new demand

vector
Change Demand
Capture Data
Look up switching
states
Read/Write
FPGA

Load switching states and
duty cycles into FPGA
Figure 7.9: Block Diagram for the DSP Software for the 4-Leg Matrix
Converter
The software for the DSP is broken up in the 3 main parts, as can be seen
in Figure 7.9, with these being the:
Initialisation and peripheral setup
Interface and main control loop
Matrix SVM interrupt code
The initialisation and peripheral setup code block is the rst block of
code to be run by the DSP when the application starts. This is a straightforward set of functions which are used to initialise and set up the various parts of the DSP and its evaluation board, initialising the main
variables and then setting up the FPGA. This code is just run at the start
of the program, and its nal task is to call the AwaitPCMessage which is
the main communication and control loop.
The communication and control loop is the part of the DSP software
which, as its name suggests, is where theDSP handles its communication
214

with the controlling PC, and then interprets the messages from the PC to
control the operation of the converter. There are a number of commands
which the DSP is able to perform, and these include:
Start the converter
Stop the converter
Change the demand voltage or frequency
Capture some DSP data for the PC
Read from or write to the FPGA
This is designed as an endless loop which the DSP will never leave,
except for servicing the external interrupt from the FPGA which is triggered at the start of every SVM period. There are more details about how
the DSP and PC communicate in Section 7.3.3 below.
The main core of the software for the DSP is contained within the interrupt routine which is triggered by an external pulse from the FPGA, and
it is this routine which performs all the calculations required to generate
the duty cycles and switching states.
The software for performing these calculations is very similar to that
used for the Matlab simulations and the MAST template, however, there
are a number of notable differences.
The biggest of these differences between the implementation in the simulations and that required for the actual converter is that for the simulations the time stops while all the calculations are being completed for
that time instant. This means that the sampled input voltages can be
used to calculate the required switching vectors and times and then be
immediately used during that sample period, however, with the actual
converter this cannot happen as the processing always takes a nite
amount of time. For example, the instant the new sampling period starts,
the DSP would need to know what switching state to send to the FPGA,
but at that instant the DSP has not even had change to read the input
voltages, so this rst switching state cannot be known at this point.
For this reason the DSP always needs to be calculating the switching
vectors and times for the next switching period. But to enable this to
happen the DSP needs to know the behaviour of the input voltages in
the next sampling period. To achieve this the DSP employs a software
phase locked loop, which locks an internally generated space vector to
215

the one calculated from the voltages on the input phases. By knowing
the magnitude of this vector, along with its phase and its frequency,
it makes it a relatively simple task to be able to calculate the expected
input voltages for the next sampling period. The software PLL used in
this software, is taken from the software used to control the 3x3 matrix
converter upon which the hardware design is based.
Now, for every sampling period, even though the times involved are
short, the voltages at the end of the period will be different from those
at the start. So if the input voltages are sampled at the start of a period,
as time approaches the end of the period, the input voltages will have
changed, and so the duty cycles used at that point will be slightly out.
This then means that the output voltage at this instant will be slightly
different to that expected, and that the input current vector will also be
slightly misaligned from the voltage vector, thus giving a small error,
which would be seen as a degradation in the harmonic performance of
the converter.
However, by extending the way that the output space vector from the
PLL is used, this error can be minimised. So, using the fact that the
input voltages can be predicted at some time in the future, this means
that it allows the choice of any point within the next sampling period,
for example the mid-point in the sampling period, to base the duty cycle
and switching state calculations on. Then taking this once step further again by considering the type of switching sequence being used,
it will be noticed that the switching sequence is separated into two half
cyclesseeFigure 6.21b. This, combined with being able to predict the voltages, means that instead of just performing the duty cycle and switching
state calculations once for a whole sampling period, it is possible to
do these calculations for each half-cycle separately, using the voltages
predicted at the mid-point in each half-cycle as the input reference.
Obviously, by using this approach it will double the time taken for the
DSP to perform the duty cycle and switching state calculations, and so
during the development process a check needed to be kept in place to
ensure that the time taken to execute the interrupt routine was always
less than the sampling period. During testing of the DSP software it has
been shown that the interrupt routine takes 60s to complete which is
well within the sampling period of 80s.
The next difference is how the DSP outputs the switching information
to the converter itself. In the Saber simulations these signals were sent
directly from the block performing the calculations, however, due to the
time resolution that is required for accurate switching the DSP is just
216

not fast enough, and so the FPGA is used to manage the actual gate
switching signals for the devices. However, there still needs to be some
method for the DSP to tell the FPGA what switching states and timing
to used. This task is performed by a First-In First-Out (FIFO) buffer built
into the FPGA, the DSP then loads this with the switching state and
timing information for each sampling period. There is some care which
is needed by the DSP when handling this information though, rstly to
ensure that the time for a single to switching state does not fall below a
certain value, and secondly to make sure that the total time for all the
switching states, including the zero states, for this sampling period exactly equals the length of the sampling period. Once these arrangements
are in place, the switching states with their respective timings are loaded
into the FIFO, rst to last, for both half-cycles of the sampling period.
The interrupt routine then exits, and the DSP returns to the communication and control loop to await either the next interrupt, or a command
from the PC.
The DSP software has been written in C and compiled specically for
the C6713 processor using the Texas Instruments Code Composer Studio
- Platinum Edition which is supplied with the evaluation board.
7.3.2
Field Programmable Gate Array
Due to the complex nature of the switching sequences involved with

the operation of a matrix converter, and their need for short and precise
timing within each switching sequence, a eld programmable gate array
(FPGA) is used to interface the DSP to the gate drive circuits. Using the
FPGA also provides an easy way to provide an interface between the
DSP and a number of other external functions which are required, the
most important of which is the A/D Converters, and by placing these
under the control of the FPGA, it frees up the DSP to concentrate on the
calculations.
Figure 7.10 is a block diagram of the main components of the FPGA,
which shows that it handles the following functions: A FIFO which holds the vector information
A PWM timing module which performs the timing for each vector
4 off Four-Step Commutation blocks which translate the vector information into switching signals
217

A/D Converters
A/D Converter
Control and Interface
Pulse output for DSP

external interrupt
Hardware trips
Trip
Monitor
Single Leg
4-Step Commutation
Block
Gate signals for

Leg c
Gate signals for

Leg n
PWM
Module
FIFO
FPGA/DSP Interface
Controller
Data Bus
Watchdog
Timer
Gate signals for

Leg b
Single Leg
4-Step Commutation
Block
DSP
Gate signals for

Leg a
Single Leg
4-Step Commutation
Block
Address
Bus
Single Leg
4-Step Commutation
Block
I 2C
Interface
Hardware trip
sensors
Current direction
input from converter
Figure 7.10: Block Diagram showing the main components of the FPGA
An A/D Converter module which controls the A/D converters,
and then demultiplexes the resulting data
A Watchdog timer that will trip the converter if required
A set of Hardware and software trips
The overall design of the FPGA is such that it is seen by the DSP as
a series of memory addresses, which it is able to read from and write
to, and this interface is briey described in Appendix C. By having the
interface arranged in this way, it allows the registers and functions of the
FPGA to be accessed directly by the DSP, this is greatly advantageous as
it means that no special routines are required for reading from or writing
to it, and especially so with respect to the A/D data.
The core functions of the FPGA are set up by the DSP on initialisation,
the most important here being the PWM sampling period, as this controls the interrupt that is sent to the DSP, along with providing all the
timing information for the 4 different commutation blocks. Once the
sampling period is set, the various parts of the FPGA can be initialised,
the outputs turned on, and the FPGA at this point is ready to go.
The most important function for the FPGA is that of generating the gate
control signals which go straight to the gate drive circuits on the power
board. The sequence for this originates in the previous sampling period
where the DSP has calculated the switching states and times for this
sampling period, and this data has been loaded into the FIFO buffer in
the FPGA. Then, as the new sampling period starts, the rst switching
state out of the FIFO buffer gets output by the PWM module, which is
218

then read by the commutation blocks. This information stays on the outputs of the PWM module for its specied switching time, before being
changed for the next switching state. The length of time it stays on the
outputs is controlled by the timing information which the DSP sent. This
states how many FPGA clock cycles that switching state is used for, and
with the FPGA clock running at 50MHz, this gives a possible resolution
of 20nS in the switching times.
The commutation blocks are constantly looking for changes in their inputs, which will then cause the commutation process to start. With each
commutation block looking after a single switching leg, this means that
there are only 3 possible nal output states as only a single switch in a
leg can be turned on at the same time. So, the commutation block reads
in the value from the PWM module, and if that is currently the same as
already on the outputs, it does nothing, if this value is different it then
commutates to the specied leg using the 4-step process, until once again
the output of the block is the same as the input. The only other input to
this block is from the current direction. As was shown in Section 4.3,
exactly how the 4-step process operates during a single commutation
depends on the current direction in that output leg.
This process with the DSP lling up the FIFO, and the PWM module
emptying it needs to be carefully controlled, as it is a ne balance. If the
sum of all the times the DSP places in the FIFO in a sampling period,
to be used in the next sampling period, does not equal the length of the
sampling period, the FIFO will start to under, or over, run and as this
happens, rouge switching states will sent to the outputs, so this process
has to be carefully controlled by the DSP.
Overall, the code for the FPGA is based on, and very similar to that used
by the 3x3 converter, however the extra output leg did require a number
of changes to the overall design, and these changes were made using
Actels release of the Libero FPGA design platform.
The layout for the FPGA board itself is no different to that used by
the 3x3 matrix converter, and primarily consists of a number of A/D
converters which are used for sampling the voltage and current sense
signals from the power board. Built into this circuit there are also a
number of hardware trips, with controllable trip levels via an integrated
I2 C bus which has been built into the FPGA.
219
7.3.3
Host Port Interface
In order to interface to the software running on the DSP, and thus to

control the operation of the converter, a PC needs to attached to the
DSP. Initially this was performed using the Universal Serial Bus (USB)
port built into the Spectrum Digital DSP evaluation board. This had
the advantage that there already existed a set of commands within the
DSP evaluation board that allowed the PC to communicate with the DSP,
and so it allowed quick and easy communication. There was a problem
with this method, that although this method worked for small amounts
of data, it always required the intervention by the DSP as part of the
communication process, and as the inbuilt commands used an interrupt
driven structure this meant that the DSP could be interrupted during
a time-critical part of the software, and so interfere with the operation.
This was not an issue when during the early stages of the development
work, but did start to cause problems during the later phases.
This problem was cured by using the Host Port Interface (HPI) facility
of the evaluation board which can be utilised by using a small daughterboard made by Educational DSP Ltd. This small board plugs into the
HPI port, which is one of the multi-way headers on the DSP board,
and through this board a PC is allowed direct access to the memory
on the DSP board. This then lets the PC to read and write directly
into the DSP memory space without taking up any processor time with
the communication. With this method, the only overhead in the DSP
is the time required to check if a new message/command is waiting
to be read, and to then respond appropriately, and most importantly,
as this does not need a DSP interrupt to operate, there is no chance of
the communication between the PC and DSP interfering with any of the
time-critical sections of code.
The way this interface is achieved is by having the DSP reserve an area
of memory within its memory space, which would be used specically
for the transfer of data between the PC and DSP. This area is then split
up into four regions: PC -> DSP Messages
Trip Status
Captured Data Area
The rst area, for PC -> DSP Messages, is used for the PC to send control
messages to the DSP, such as to start or stop the converter, or to change
220

the demand voltage or frequency. During the period of time when the
DSP is effectively idling, so when not performing the main interrupt
routine, the DSP sits and loops round a short section of code which
continuously checks the PC -> DSP Message area for a new message.
It will check to see if the message checksum is correct, and at that point
it will process the message.
The next memory area that the PC has access to is the Trip Register. This
is a copy of the FPGA trip register which is updated every time the DSP
restarts the idling loop, so it is continuously update
The nal memory area which is made available to the PC is the Capture
Data area, this, as its name suggests, it where the PC can read any data
which the DSP has been asked to save. The data stored in this area
depends on which of the three different commands has been sent to the
DSP by the PC.
The rst command just asks for a single snapshot of a series of the DSPs
internal variables to be saved which is then read by the PC and displayed. This is useful for quickly checking that the converter is functioning as expected and is making sane calculations.
The second, and most useful, command is for the DSP to capture a set of
its data on every interrupt cycle, over a period of time. This data is then
uploaded to the PC where, for example, the Matlab simulation les can
be run using the uploaded set of input data, and the results compared.
The third command asks for the DSP to interrogate each of the FPGA
registers in turn and save the result into the Capture Data area. This
then allows the PC to read the FPGA information, to check on register
settings and ensure that the FPGA is working correctly.
To be able to access this memory from the PC required a series of Matlab
executable (MEX) les to be written. These allow Matlab function calls
to interface with the HPI libraries supplied with the daughterboard, and
for each type of read and write function a separate MEX le is required.
7.3.4
Matlab/PC
To enable some control over the DSP, and thus the converter, a Matlab
graphical user interface (GUI) was designed that would allow the PC to
stop and start the converter, reset it, and also change the demand voltage
and frequency. During the development of the DSP software, it became
apparent that due to the complexity of the calculations, it would be
difcult to verify if the DSP was actually working correctly, so alongside
221

the command functions, a number of additional functions was added so
that the PC could request data from the DSP. This data could then used
to verify the DSP results, using the Matlab functions which has already
been designed for the simulation.
Figure 7.11 shows the main window of the interface. The graph which
is plotted in the centre of the window is from a data capture, and shows
the input voltage, demand voltage and calculated output voltage all read
from the DSP. As well as those three plots, there is a fourth set of data
plotted which is the set calculated on the PC. If the DSP is working as
expected, then the demand voltage and two calculated voltage plots
should all match.
The second plot window shows the interrupt execution time and the
sampling period plotted together, and was used during the development
of the software to ensure that the execution time for the interrupt routine
stayed well within the sampling period.
Figure 7.11: The Main Control Interface for the 4-Leg Matrix Converter
The second window in the Matlab interface, which is shown in Figure 7.12. is used to show information about the state of the FPGA registers, the outputs from the A/D converters, and of a number of other
internal DSP variables. This data is regularly sampled by the PC, and so
this window automatically updates its values.
222
Figure 7.12: The FGPA Registers Display Window
223
C HAPTER 8
Experimental Results
This chapter describes the testing which was performed on the 4-Leg
Matrix Converter described in the previous chapter. The initial testing
was all designed around ensuring that the converter was operational,
before moving on to use the converter to drive a real load, both balanced
and unbalanced.
8.1
Initial Testing
The start of the initial testing of the converter proved to be tricky as

the code for the DSP, although tested and simulated within the design
environment, was still untried with real world signals. In the end the
problems mostly due to problems with the timing between the DSP and
the FPGA, centring around the FIFO for the PWM module. However, after the initial teething troubles were overcome the converter was shown
to be working fully. One small trick that helped here was to be able to
use the onboard D/A converters on the DSP card to produce a simulated
pair of voltage signals. This allowed the testing of the phase-locked
loop and a number of other functions without needing to have sensors
connected to a mains supply all the time.
During the latter stages of the initial testing of the converter, when it was
undergoing mains level testing, it was discovered that when in the input
voltage from the variac was turned up above approximately 50% of the
mains supply it would cause a number of diodes in the protection circuit
to fail. This initially was put down at a problem with a device shorting
to one of the clamp rails, but after replacement the same problem was
re-occurring. At this point the problem is still unidentied, although it
is suspected that this might be down to problems during high frequency
224
C HAPTER 8: E XPERIMENTAL R ESULTS

spikes of current from during the commutation phase, which are then
causing the clamp voltage to rise.
However, even with this problem, it allowed the converter to function,
although a reduced voltage and power levels, and even at these lower
levels the results gained are still valid.
8.2
Balanced Load
Once initial testing had been completed, the converter was connected
to a 415V supply, through a variac, and then attached to its load, made
up of 4 8mH inductors and a star connected set of 3 10 resistors as
described in the previous chapter. The following results show results
show that the converter is working as expected.
Due to the trouble with the diode protection circuit, the converter was
being run with an input voltage of approximately 80Vrms , as such the demand voltage was set to a gure of 50Vrms and with a demand frequency
of 100Hz. The results for this test follow.
Figure 8.1 shows the set of output voltages measured across the load
resistances.
Figure 8.1: Plot of the 4-Leg Matrix Converter Output Phase-neutral

Voltages at the Load
50Vrms Demand Voltage - 100Hz Demand Frequency - 12.5kHz
Sampling Frequency
Figure 8.2 then provides a closer look at these waveforms, and it shows
that while there is high frequency switching noise, present and especially
225

noticeable at the peaks of the sine waves, the overall shape appears to be
good, and this is born out by the FFT of the output voltage on leg Van
which is shown in Figure 8.3.
Figure 8.2: Plot of the 4-Leg Matrix Converter Output Phase-neutral

Voltages at the Load
Sampling Frequency
Figure 8.3: Plot of the FFT of the Output Phase-neutral Voltage on Leg a
at the Load
Sampling Frequency
Figure 8.4 shows the an area of the FFT in Figure 8.3 which has been
zoomed in vertically 25 times. As can be seen, the switching frequency
226

noise at around 12.5kHz is at this point only at approximately 0.5% of the
magnitude of the fundamental. As will also be noted, there does appear
to be some small amount of low frequency harmonics present as well,
and these are most likely to be due to differences in the PLL-derived
input voltage and the actual input voltage.
Figure 8.4: Closeup of the FFT of the Output Phase-neutral Voltage on

Leg a at the Load
Sampling Frequency
Looking at the plots for both the spectra and waveforms for the output
voltage at the load, these both in tie in extremely well with the plots from
the Saber simulations shown in Figures 6.30 and 6.31.
Taking a step back towards the converter terminals now, Figure 8.5 shows
the FFT of the voltage at the terminals of the converter. Once again, this
waveform looks very close to the simulated waveform in Figure 8.3.
Moving onto the front end of the converter now, to look at the input
currents. These are shown in Figure 8.6, and as can be seen, these are also
nicely sinusoidal, although there is some amount of ripple in the waveform in places. These points appear to tie in with the boundaries between input current segments, however despite efforts to nd the cause
of this problem, they have remained. One suspicion was that these are
caused by the difference between the actual input voltages and the PLL
derived ones, and as can be seen in Figure 8.9 this ripple does appear to
some extent on the input voltages.
Now looking at the FFT for the input current in Figure 8.7, once again
this shows a clean spectrum. The ripple which was noted in the current
227
Figure 8.5: Plot of the FFT of the Output Phase-neutral Voltage on Leg a
at the Converter
Sampling Frequency
Figure 8.6: Plot of the 4-Leg Matrix Converter Input Currents

Sampling Frequency
waveforms can be seen as the low frequency noise, and looking more
closely at that region in Figure 8.8 it can be seen that for the input,
this ripple is of greater magnitude that the switching noise, however
in this case, the ripple is still well below 1% of the magnitude of the
fundamental.
While the input current being sinusoidal is important, it is also a re228
Figure 8.7: Plot of the FFT of the Input Current of Phase A

Sampling Frequency
Figure 8.8: Closeup of the FFT of the Input Current of Phase A

Sampling Frequency
quirement for the input current to be in phase with the input voltage,
and Figure 8.9 shows that well, and so means that while supplying a
balanced set of 3-phase voltages to a balanced load, the converter has a
unity displacement factor.
Due to the Matlab controller being able to download various sets of data
from the DSP during the converter operation, it is possible to see the
229
Figure 8.9: Plot of the 4-Leg Matrix Converter Input Current and
Voltage for Phase A
Sampling Frequency
internal state of the converter. This was originally designed to be able
to check on the correct operation, but it also allows the later storage and
plotting of the results. For these results one of the most interesting of
these is the sampled output current data for each of the three phase legs
a, b and c, with the neutral current being calculated as the sum of the
other 3 legs. Figure 8.10 shows a plot of these currents, and it can be
seen here that the current ripple which is present in the input phases,
looks to also be present here as well. This ties up with a possible problem
with how the converter is behaving around the interfaces between input
sectors and tetrahedrons, and is a problem with the implementation in
this converter rather than a problem with the theory itself.
Also of interest is the plot of the duty cycles shown in Figure 8.11. These
are a snapshot of the duty cycles from the above testing, and as can be
seen, they overall, follow the general shape of the duty cycles seen in
both the Matlab(Figure 6.15a) and Saber(Figure 6.26) simulations. The
slight differences in shape are entirely due to the relative phasing between the input frequency and the output frequency.
And nally, before moving on to look at the behaviour of the converter
under an unbalanced load condition, is the plot shown in Figure 8.12.
This shows the time it takes for the DSP to perform all the calculations
required to determine the switching vectors and times to control the matrix converter, Ti , and plots this value alongside the total time available
230
Figure 8.10: Plot of the 4-Leg Matrix Converter Output Leg Currents for
Balanced Operation
Sampling Frequency
Figure 8.11: Plot of the 4-Leg Matrix Converter Input Current and
Voltage for Phase A
Sampling Frequency
within the SVM switching period, Ts . As can be seen, the interrupt
routine takes approximately 60s to perform its calculations, leaving
around 20s left over in which to perform all its other duties. In this case
that time was taken up with communicating with the host PC and performing any commands, however in a real application this time would
also need to be used to implement whatever control strategy was being
231

used for the overall system.
When comparing this to the other types of modulation used for 4-leg
matrix converters as discussed in Section 5.11, the 60s taken by this
method does appear to be slow, especially since the Alesina/Venturini
method can be used in a converter with a 25kHz switching frequency [30],
which has a period of 40s, and it is believed that using the Fictional
DC Link [] would be able to operate even quicker than this. However,
the DSP code for this project was written to be able to operate with a
switching frequency of 12.5kHz, and as such some of the techniques
used may not be the fastest, and with the more extensive use of lookup
tables it would be possible to bring down the DSP execution time to at
least work at 25kHz.
One thing that should be noted here is that for this method, the DSP is
actually calculating two sets of switching vectors per switching period,
as it handles each half of the switching cycle separately, and this might
also explain why the execution time is longer and this should also be
taken into account.
Figure 8.12: Plot showing Ti , the time taken to process the DSP
interrupt routine, alongside the SVM Period, Ts
232
8.3
Unbalanced Load
The next set of testing featured the converter running an unbalanced

load, in this case one of the branches of the star connected resistor network was doubled in size to 20, and a number of the tests was run
again.
The rst investigation in this instance was to look at the input current,
as it was expected that this would be where the imbalance in the load
would have the greatest effect. Figure 8.13 shows this quite clearly, and
although it is broadly sinusoidal, the distortion is very evident. Looking
at the spectra of this input current in Figure 8.14 it clearly shows that
there is now a signicant amount of low frequency distortion present,
and this is shown more clearly in the close-up of that region shown in
Figure 8.15. Here it can be seen that there are two signicant harmonics,
one at 150Hz, and one at 250Hz, and these precisely match those found
during the Saber simulations.
Figure 8.13: Plot of the Input Current of Phase A with an Unbalanced

Load
Sampling Frequency
Moving to the other end of the converter now, to look at the output voltages at the converter terminals. As expected, and as veried in the Saber
simulations, there if little difference between the voltage being produced
with the unbalanced load at this point and that for the balanced load,
and this is conrmed by the FFT of the output voltage on leg c which is
233
Figure 8.14: Plot of the FFT of the Input Current of Phase A with an
Unbalanced Load
Sampling Frequency
Figure 8.15: Close-up of the FFT of the Input Current of Phase A with
an Unbalanced Load
Sampling Frequency
Looking now at the voltage that is produced across the load, and as
with the Saber simulations, the voltage waveforms were seen to be sinusoidal, which is shown in Figure 8.17 which shows the FFT of the
output voltage for leg c across the load resistor. Looking more closely at
the lower frequency range in Figure 8.18 once again shows there is very
234
Figure 8.16: Plot of the FFT of the Output Phase-neutral Voltage for Leg
c at the Converter for an Unbalanced Load
Sampling Frequency
little low frequency distortion, and once again matches very closely with
the results found in the Saber simulations, and shown in Fig 6.39.
Figure 8.17: Plot of the FFT of the Output Phase-neutral Voltage for Leg
c across the Load for an Unbalanced Load
Sampling Frequency
As with the testing of the balanced load above, the DSP was used to
capture snapshots of the converters operation, and by looking at the
235
Figure 8.18: Close-up of the FFT of the Output Phase-neutral Voltage

for Leg c across the Load for an Unbalanced Load
Sampling Frequency
output leg currents being supplied to the unbalanced load, its possible to
see that the currents in all three phase output legs are sinusoidal, which
once more ties in nicely with the results from the FFT of the voltage
across the load.
Figure 8.19: Plot of the 4-Leg Matrix Converter Output Leg Currents for
Unbalanced Load
Sampling Frequency
Unfortunately, at this point the converter suffered another failure within
236

the diode bridge, which prematurely ended the testing, however with
the results gathered up to this point, it is considered that there is enough
evidence to state the converter is operating as expected, the areas in
which it does suffer from issues are entirely due to problems with the
implementation, either in the software, or in a problem with the diode
bridge.
8.4
Summary
While the converter was working the experimental results which were
achieved were very good, even though the converter was having to operate at reduced voltages levels. These results matching up with the
simulated results to a high degree, however with the problems in the
diode bridge this did limit the testing, and even cut it short of the ideal.
However, with the results that have been achieved, taking these in conjunction with the simulation results it is reasonable to state that the converter is operating as expected. As such this proves the theory behind
the operation, and shows that the equations derived for calculating the
duty cycles and switching states are correct. As such meets the main
objective set for this work.
Unfortunately, what these results do not prove is whether the actual implementation of this converter is correct as it was just prior to these tests
that it failed once again. Having stated that, during the initial testing
the DSP was put through a large number of different tests, involving a
range of different waveforms, and although not documented here, as no
results were taken during this development work, this did show that the
DSP software was working.
237
C HAPTER 9
Conclusions
The work presented in this thesis has set out to demonstrate the proof of
the theory behind the implementation of Space Vector Modulation on a
4-Leg Matrix converter, and it is believed that with the work presented
here it has been able to do this. The aims and objectives at the start of the
project were simple, to investigate the use of space vector modulation
with the new 4-leg matrix converter, and then to derive its theory and
operation. This theory was then to be tested by both simulation and by
the construction of a demonstration converter.
This investigation started with a look at how space vector modulation
works, and has been implemented, on two related circuits, the 4-leg
inverter and matrix converter, from which the 4-leg matrix converter derives. The work then went on to show a derivation of the theory behind
the 4-leg matrix converter in Chapter 5. This derivation started with
by looking at the input current and output voltages spaces separately,
before being able to combine them in a fashion that allowed both to be
independently controlled with respect to one another.
Having completed this proof, the simulation work then became the next
step, with this forming a large quantity of the work involved in this
paper. The initial simulation work went on to rst prove itself to be
an adequate method, before moving on to demonstrate that the theory
worked perfectly, and the results then provided by further circuit simulation backed these results up further. The simulation work then moved
onto looking at more advanced concepts using the Saber package, and
with these simulations it was possible to show how the converter dealt
with a number of issues around the physical implementation of the converter.
The focus of the work then turned on to building a converter to practically demonstrate these results, by expanding on an existing design
238
C HAPTER 9: C ONCLUSIONS
of converter. While this work resulted in a converter which was capable of operation, a problem which caused a number of failures, limited the experimental results available. However it is felt that despite
these problems with the experimental converter, the results that were
obtained were more than capable of backing up the simulation results
and showing that the theory of operation for the converter was correct.
Since this work a 4-Leg Matrix converter using the derived technique
has been built and proven to be operational[36]. This evidence can only
be strengthened by papers[30, 36] which have been published since this
initial theory was published[32].
At the start of this project there had been no research published into the
operation or control of the 4-Leg Matrix converter, however interest is
starting to be seen with the number of published works increasing as
different aspects of the 4-Leg Matrix converter are investigated[29, 34
41]. It is therefore hoped that the work presented here can be seen as
being part of the beginnings of this interest.
So, despite the problems which were encountered with the build of the
matrix converter, there is sufcient evidence presented here that it is
possible to state that the derivation and implementation of Space Vector
Modulation in a Four-Leg Matrix Converter shown here is correct, and
so the work has been a success.
239
A PPENDIX A
Papers published as a result of

this work
During this work the following paper was published:
Wheeler, P.W. and Clare, J.C. and Mason, N. Space Vector Modulation
for a 4-Leg Matrix Converter Power Electronics Specialists Conference,
2005. PESC 05. IEEE 36th
240
A PPENDIX B
IGBT Datasheet
241
SK 60GM123
Absolute Maximum Ratings
Symbol Conditions
IGBT
Values
Units
SEMITOP 2
IGBT Module
SK 60GM123
Inverse Diode
Module
Preliminary Data
Features
Characteristics
Symbol Conditions
IGBT
min.
typ.
max.
Units
Typical Applications*
GM
27-06-2007 DIL
by SEMIKRON
SK 60GM123
Characteristics
Symbol Conditions
Inverse Diode
min.
typ.
max.
Units
SEMITOP 2
IGBT Module
SK 60GM123
Preliminary Data
Features
This is an electrostatic discharge sensitive device (ESDS), international standard

IEC 60747-1, Chapter IX.
* The specifications of our components may not be considered as an assurance of
component characteristics. Components have to be tested for the respective
application. Adjustments may be necessary. The use of SEMIKRON products in
life support appliances and systems is subject to prior specification and written
approval by SEMIKRON. We therefore strongly recommend prior consultation of
our personal.
Typical Applications*
GM
27-06-2007 DIL
by SEMIKRON
SK 60GM123
Fig. 1 Typ. output characteristic, inclusive RCC'+ EE'
Fig. 3 Typ. turn-on /-off energy = f (IC)
Fig. 4 Typ. turn-on /-off energy = f (RG)
Fig. 6 Typ. gate charge characteristic
27-06-2007 DIL
by SEMIKRON
SK 60GM123
Fig. 7 Typ. switching times vs. IC
Fig. 8 Typ. switching times vs. gate resistor RG
Fig. 10 CAL diode forward characteristic
27-06-2007 DIL
by SEMIKRON
SK 60GM123
UL recognized file
no. E 63 532
27-06-2007 DIL
by SEMIKRON
A PPENDIX C
FPGA Memory Locations within

the DSP Memory Space
247
DPR0 0xA0000000;
31
30
29
15
14
13
PRS
PEN
PEN
CIP
Read
Write
Read
Write
PRS
28
27
26
25
24
23
22
12
11
10
CIP
ADM
ADM
PWR
21
20
AST
19
18
17
16
PWR
RTR
MEN
SMD
SMC
SMB
SMA
SMD
SMC
SMB
SMA
18
17
16
PPD
PPD
PPD
PRS
PEN
PFL
PWR
CIP
ADM
AST
SMA
SMB
SMC
SMD
RTR
MEN
PWM_PERIOD
PWM_RESET
PWM_ENABLE
PWM_FIFO_LEVEL
Power on reset
Current Direction Input Polarity:
A2D multiplex
A2D Converter Start
State Machine A enable
State Machine B enable
State Machine C enable
State Machine D enable
Reset trip button state
Enable button state
0xFFFF (desired time - 1 clock cycle)

Active High
Active High
Active low - temporary
0 = Active Low, 1 = Active High
0 = software driven
1=pwm interupt driven.
Active High
Active High
Active High
Active High
Active High
Active low
DPR1 0xA0000100;
31
30
29
28
27
26
25
Read
Write
15
14
13
12
11
10
Read
Write
UI7
UI6
UI5
UI4
UI3
UI2
UI1
24
23
22
21
20
19
ABY
PVE
PVT
PAF
PAE
PEM
PFU
CINA
CINB
CINC
CIND
ABY
UI1-7
PVE
8
UI0
CIND
CINC
CINB
CINA
PFU
PEM
PAE
PAF
PVT
PWM_VECTOR
PWM_VECTOR_TIME
PWM_FIFO_Almost Full
PWM_FIFO_Almost Empty
PWM_FIFO_EMPTY
PWM_FIFO_FULL
Current Direction Input, PhaseA
Current Direction Input, PhaseB
Current Direction Input, PhaseC
Current Direction Input, PhaseD
A2D converters Busy
User input 1 to 7
No. of words in FIFO > 250, Active High

No. of words in FIFO < 2, Active High
Active High
Active High
Active High
Active High
Active High
Active High
1 = Busy
DPR2 0xA0000200;
31
30
Read
Write
29
28
27
26
25
24
23
22
21
20
19
T3
T3
15
14
18
17
16
T2
T2
13
12
11
10
Read
Write
T1
T1
T1
T2
T3
First delay timer register for 4-step current commutation

Second delay timer register for 4-step current commutation
Third delay timer register for 4-step current commutation
DPR3 0xA0000300;
31
Read
Write
Read
Write
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
14
13
12
11
10
AD0
AD1
15
AD0
AD1
A2D Data, Channel 0

A2D Data, Channel 1
DPR4 0xA0000400;
31
Read
Write
Read
Write
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
14
13
12
11
10
AD3
AD2
15
AD2
AD3
A2D Data, Channel 2

A2D Data, Channel 3
DPR5 0xA0000500;
31
Read
Write
Read
Write
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
14
13
12
11
10
AD5
AD4
15
AD4
AD5
A2D Data, Channel 4

A2D Data, Channel 5
DPR6 0xA0000600;
31
Read
Write
Read
Write
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
14
13
12
11
10
AD7
AD6
15
AD6
AD7
A2D Data, Channel 6

A2D Data, Channel 7
DPR7 0xA0000700;
31
Read
Write
Read
Write
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
14
13
12
11
10
AD9
AD8
15
AD8
AD9
A2D Data, Channel 8

A2D Data, Channel 9
DPR8 0xA0000800;
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Read
Write
HT23
HT22
HT21
HT20
HT19
HT18
HT17
HT16
HT15
HT14
HT13
HT12
HT11
HT10
HT9
HT8
15
14
13
12
11
10
Read
Write
HT7
HT6
HT5
HT4
HT3
HT2
HT1
HT0
ST7
ST6
ST5
ST4
ST3
ST2
ST1
ST0
ST7
ST6
ST5
ST4
ST3
ST2
ST1
ST0
22
21
20
19
18
17
16
ST0 ST7
HT0 HT23
Software Trip
Hardware Trip
Active High
Active High
HT0
HT1
HT2
HT3
HT4
HT5
HT6
HT7
HT8
HT9
HT10
HT11
HT12
HT13
HT14
HT15
PWM FIFO empty trip

Watchdog Trip
Channel 0 trip
Channel 1 trip
Channel 2 trip
Channel 3 trip
Channel 4 trip
Channel 5 trip
Channel 6 trip
Channel 7 trip
Channel 8 trip
Channel 9a trip
Channel 9b trip
not used
External trip 2
PWM FIFO Full
DPR9 0xA0000900;
31
30
29
28
Read
Write
UO3
UO2
UO1
UO0
27
WEN
UO3
UO2
UO1
UO0
WEN
WSR
15
14
13
12
Read
Write
W_PERIOD
11
26
10
25
24
23
W_PERIOD
W_PERIOD
WSR
WEN
UO0-3
Watchdog Period Register

Watchdog Service
Watchdog Enable
User Output 0-3
Period = 0xFFFF W_PERIOD

Active High
Active High
DPR10 0xA0000A00;
31
30
29
28
27
26
25
24
23
22
21
20
19
18
Read
Write
17
16
Address
15
14
Read
Write
13
12
11
10
Command
Register
I2C
Data
I2C DATA for controlling the Hardware trip limit setting via I2C digital potentiometers(MAX5478)
DPR12 0xA0000C00;
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Read
Write
TE23
TE22
TE21
TE20
TE19
TE18
TE17
TE16
TE15
TE14
TE13
TE12
TE11
TE10
TE9
TE8
TE23
TE22
TE21
TE20
TE19
TE18
TE17
TE16
TE15
TE14
TE13
TE12
TE11
TE10
TE9
TE8
15
14
13
12
11
10
Read
Write
TE7
TE6
TE5
TE4
TE3
TE2
TE1
TE0
TE7
TE6
TE5
TE4
TE3
TE2
TE1
TE0
TE = trip enable, number = hardware trip channel, 0 = enable, 1 = disabled
References
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utility power supply based on the matrix converter. In Proc. IEEE
IAS Annual Meeting 04, Seattle, 2004.
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S. Dubovsky. A three-phase inverter with a neutral leg with space
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[3] Domenico Casadei, Giovanni Serra, and Angelo Tani. Reduction
of the input current harmonic content in matrix converters under
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R EFERENCES
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of space vector modulation schemes for a four-leg voltage source
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S
principle. IEEE Trans. Appl. Ind., 82(66):163 A 168, May 1963.
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Space Vector Modulation of a

4-Leg Matrix Converter

Id like to dedicate this work to my father, David Mason,

The Matrix Converter . . . . . . . . . . . . . . . . . . . . . .

The 4-leg Inverter . . . . . . . . . . . . . . . . . . . . . . . .

The 4-leg Matrix Converter . . . . . . . . . . . . . . . . . .

Applications and Limitations . . . . . . . . . . . . . . . . .

Four-Leg Inverter Modulation

Space Vector Modulation of the 4-Leg 4-Wire Inverter . . . 13

Matrix Converter Modulation

Alesina/Venturini Optimum Method . . . . . . . . . . . . 27

Space Vector Modulation . . . . . . . . . . . . . . . . . . . . 29

Threshold 2-Step Current Commutation . . . . . . . . . . . 40

Voltage Sensed Current Commutation . . . . . . . . . . . . 42

Derivation of the Space Vector Modulation technique for the

The Input Voltage Plane . . . . . . . . . . . . . . . . . . . . 46

The Input Current Plane . . . . . . . . . . . . . . . . . . . . 48

The Output Voltage Space . . . . . . . . . . . . . . . . . . . 49

The Switching States . . . . . . . . . . . . . . . . . . . . . . 52

Output Voltage and Switching States . . . . . . . . 57

Input Current and Switching States . . . . . . . . . 60

Determining the output sector . . . . . . . . . . . . . . . . . 62

Determining the input sector . . . . . . . . . . . . . . . . . 66

Selecting the Switching States . . . . . . . . . . . . . . . . . 68

Combining the Input and Output Spaces . . . . . . . . . . 70

Calculating the Duty Cycles . . . . . . . . . . . . . . . . . . 74

5.10 Voltage Transfer Ratio . . . . . . . . . . . . . . . . . . . . . 80

Simulation of the 4-leg Matrix Converter

Simulation using Matlab . . . . . . . . . . . . . . . . . . . . 91

Simulation using Saber . . . . . . . . . . . . . . . . . . . . . 126

Saber Simulation Results . . . . . . . . . . . . . . . 136

Matrix converter design and construction

Introduction and overview . . . . . . . . . . . . . . . . . . . 201

Matrix Converter Power Circuit . . . . . . . . . . . . . . . . 203

Gate Drive Circuit . . . . . . . . . . . . . . . . . . . 205

Output Current Sensing . . . . . . . . . . . . . . . . 207

Input Voltage Sensing . . . . . . . . . . . . . . . . . 208

PCB Design and implementation . . . . . . . . . . . 210

Input Filter . . . . . . . . . . . . . . . . . . . . . . . 211

Clamp Circuit . . . . . . . . . . . . . . . . . . . . . . 210

Output Inductors and Load . . . . . . . . . . . . . . 212

Matrix Converter Control . . . . . . . . . . . . . . . . . . . 213

Field Programmable Gate Array . . . . . . . . . . . 217

Host Port Interface . . . . . . . . . . . . . . . . . . . 220

Digital Signal Processor . . . . . . . . . . . . . . . . 213

Balanced Load . . . . . . . . . . . . . . . . . . . . . . . . . . 225

Unbalanced Load . . . . . . . . . . . . . . . . . . . . . . . . 233

Initial Testing . . . . . . . . . . . . . . . . . . . . . . . . . . 224

A Papers published as a result of this work

C FPGA Memory Locations within the DSP Memory Space

An Example of a Standalone Power Supply System using

A 4-Leg Matrix Converter as part of a Standalone Power

A 3-Leg Matrix Converter . . . . . . . . . . . . . . . . . . .

A 4-Leg Matrix Converter . . . . . . . . . . . . . . . . . . .

3-Leg 4-Wire Inverter with a Split dc Neutral Connection . 11

3-Leg 4-Wire Inverter PWM . . . . . . . . . . . . . . . . . . 12

4-Leg 4-Wire Inverter . . . . . . . . . . . . . . . . . . . . . . 13

3-Leg Inverter Demand Vector . . . . . . . . . . . . . . . . . 15

4-Leg Inverter Switching Vectors . . . . . . . . . . . . . . . 17

4-Leg Inverter Demand Vector . . . . . . . . . . . . . . . . . 18

4-Leg Inverter Demand Vector Tetrahedron . . . . . . . . . 19

4-Leg Inverter Space Vector Modulation PWM Output . . . 19

4-Leg 4-Wire Inverter . . . . . . . . . . . . . . . . . . . . . . 20

2.10 4-Leg 4-Wire Inverter Carrier-based PWM . . . . . . . . . . 22