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0
1
2
3
b[7:0]
Mux
architecture arc2 of mini_ALU is
begin
with sel select
y <= a+b when 0,
a-b when 1,
a when 2,
b when 3;
end arc2;
Example
Sistemes
Digitals I
T1 - 41
1 Introduction
2 Data Communication
3 Design Units
4 Dataflow Modelling
5 Behavioural Modelling
6 Structural Modelling
Outline
5.1 Process Statement
5.2 Sequential Assignment Statements
5.3 If Statement
5.4 Signal Attributes
5.5 Case Statement
5.6 Loop Statement
5.7 Wait Statement
Sistemes
Digitals I
5. Behavioural modelling T1 - 42
A description of the behaviour of a system says nothing about
the structure or the components that make up the system.
A behavioural model is composed by a set of concurrent
processes. The behaviour of each process is described using
sequential statements.
Process
A
Process
B
Process
C
Process
D
Process
F
Process
E
Process
G
Sistemes
Digitals I
5.1 Process Statement T1 - 43
A process statement describes an independent sequential behaviour of
some portion of the design.
When an event on any of the signals included in the sensitivity_list
occurs, the statements within the process are executed sequentially (in
the order they appear). When execution ends, the process is
suspended and waits for new events.
If no sensitivity_list is present, then the process is executed repeatedly.
Items declared in the declarative_part are available for use only within
the process.
[ l abel : ] process [ (sensi t i vi t y_l i st )] [is]
[ decl ar at i ve_sect i on]
begin
sequence_of _st at ement s
end process;
syntax
This may hang the compiler
Sistemes
Digitals I
5.1 Process Statement T1 - 44
Equivalent Schematic
2-input xor gate described with as a process statement. Process is
executed each time an event occurs on any of the signals a or b.
entity pr ocst at ement is
port( a, b: in bi t ;
y: out bi t ) ;
end entity pr ocst at ement ;
architecture a of pr ocst at ement is
begin
process ( a, b)
begin
if b='0' then y <= a;
else y <= not a;
end if;
end process;
end architecture a;
Example
Sistemes
Digitals I
5.2 Sequential assignment statements T1 - 45
Variables can be declared and used only inside processes.
A new value is assigned to variable_identifier when the variable
assignment statement is executed.
The term expression may contain signals, but both sides of the
assignment must be of the same type.
Variables may be hard to synthesize!
var i abl e_i dent i f i er := expr essi on;
syntax
Sistemes
Digitals I
5.2 Sequential assignment statements T1 - 46
The syntax for both sequential and concurrent signal assignment
statements is identical.
A sequential signal assignment is executed when an event occurs on
a signal present in the sensitivity list of the process.
Sequential signal assignments are effective only at the end of process
execution.
Signals are used to exchange data between processes.
si gnal _i dent i f i er <= wavef or m;
syntax
Sistemes
Digitals I
5.2 Sequential assignment statements T1 - 47
Example
Case 1: A, B, C and D are variables that
have been declared inside a process
which contains this set of sequential
assignment statements:
A : = B+C;
D : = A+C;
A : = C+D;
When the process is suspended after
one execution, variable values are:
A=7, B=1, C=2, D=5
Case 2: A, B, C and D are signals that
have been declared outside a process
which contains this set of sequential
assignment statements:
A <= B+C;
D <= A+C;
A <= C+D;
When the process is suspended after
one execution, signal values are:
A=5, B=1, C=2, D=2
We have four integer objects with the following initial values:
A=0, B=1, C=2, D=3
Sistemes
Digitals I
5.3 If Statement T1 - 48
Selects for execution one or none of the sequences of statements.
Conditions are evaluated successively until the first true condition is
found or all conditions are evaluated as false.
If a true condition is found the corresponding sequence_of_statements is
executed. Otherwise, if the else clause is present and all previous
conditions are false then sequence_of_statements_N is executed.
if condi t i on_1 then
sequence_of _st at ement s_1
{elsif condi t i on_i then
sequence_of _st at ement s_i }
[ else
sequence_of _st at ement s_N]
end if;
syntax
Sistemes
Digitals I
5.3 If Statement T1 - 49
library i eee;
use i eee. st d_l ogi c_1164.all;
use i eee. st d_l ogi c_si gned.all;
entity i f st at ement is
port( a, b : in st d_l ogi c_vect or ( 7 downto 0) ;
op : in bi t ;
y : out st d_l ogi c_vect or ( 8 downto 0) ) ;
end i f st at ement ;
architecture a of i f st at ement is
begin
process ( op, a, b)
variable aa, bb : st d_l ogi c_vect or ( 8 downto 0) ;
begin
aa: =' 0' &a; -- 9 bit bus
bb: =' 0' &b; -- 9 bit bus
if op=' 0' then y <= aa + bb;
else y <= aa;
end if;
end process;
end a;
Example
a[7:0]
y[8:0]
op
0
1
b[7:0]
Mux
Sistemes
Digitals I
5.4 Signal Attributes T1 - 50
Attributes are values, functions, types, ranges, signals or constants
associated with data objects that provide additional information about
those objects.
Example (event attribute): sevent (being s a signal identifier) returns
t r ue when an event occurs in s.
Time s sevent
t
1
0 f al se
t
2
1 true
t
3
1 f al se
t
4
1 f al se
t
5
1 f al se
t
6
1 f al se
t
7
0 true
t
8
0 f al se
(s=1) and (sevent) =t r ue
RISING EDGE
(s=0) and (sevent) =t r ue
FALLING EDGE
s
t
t
2
t
1
t
4
t
3
t
6
t
5
t
8
t
7
0
1
EVENT EVENT
An event attribute can be used
to specify rising or falling
edges on signals.
obj ect _i dent i f i er 'at t r i but e
syntax
Sistemes
Digitals I
5.4 Signal Attributes T1 - 51
library i eee;
use i eee. st d_l ogi c_1164.all;
entity event at t r i but e is
port( cl k, nr st : in st d_l ogi c;
xi n : in st d_l ogi c_vect or ( 7 downto 0) ;
yout : out st d_l ogi c_vect or ( 7 downto 0) ) ;
end event at t r i but e;
architecture a of event at t r i but e is
begin
process( cl k, nr st )
begin
if nr st = ' 0' then
yout <= "00000000";
elsif cl k=' 1' and cl k'event then
yout <= xi n;
end if;
end process;
end architecture;
Example
8-bit register with asynchronous reset
rising edge
detection
yout will be assigned only after a
rising edge in clk is detected
asynch.
reset
Sistemes
Digitals I
5.4 Signal Attributes T1 - 52
library i eee;
use i eee. st d_l ogi c_1164.all;
entity event at t r i but e2 is
port( cl k, nr st , e: in st d_l ogi c;
xi n : in st d_l ogi c_vect or ( 7 downto 0) ;
yout : out st d_l ogi c_vect or ( 7 downto 0) ) ;
end event at t r i but e2;
architecture a of event at t r i but e2 is
begin
process( cl k, nr st )
begin
if nr st = ' 0' then
yout <= "00000000";
elsif cl k=' 1' and cl k'event then
if e=' 1' then
yout <= xi n;
end if;
end if;
end process;
end architecture;
Example
8-bit register with asynchronous reset and synchronous enable
out will be assigned only after a rising edge on
clk is detected, being e equal to 1
out will be assigned only after a rising edge on
clk is detected, being e equal to 1
synchronous enable synchronous enable
Sistemes
Digitals I
5.5 Case statement T1 - 53
A sequence_of_statements is selected from a set of choices; the value of
an expression defines the chosen alternative.
expression must be of an enumerate type or of a 1D character array type.
choices may be expressed as single values, as value ranges or as a
values list (using a vertical bar).
An others choice is allowed for the last alternative, then it covers all
values not previously evaluated.
case expr essi on is
when choi ce_1 => sequence_of _st at ement s_1
{when choi ce_i => sequence_of _st at ement s_i }
[ when others => sequence_of _st at ement s_N]
end case;
syntax
Sistemes
Digitals I
5.5 Case statement T1 - 54
library i eee;
use i eee. st d_l ogi c_1164.all;
entity casest at ement 1 is
port( a, b, c, d : in st d_l ogi c_vect or ( 7 downto 0) ;
sel : in st d_l ogi c_vect or ( 1 downto 0) ;
y : out st d_l ogi c_vect or ( 7 downto 0) ) ;
end casest at ement 1;
architecture a of casest at ement 1 is
begin
process( sel , a, b, c, d)
begin
case sel is
when "00" => y <= a;
when "01" => y <= b;
when "10" => y <= c;
when others => y <= d;
end case;
end process;
end a;
Example 4-to-1 multiplexer
a[7:0]
y[7:0]
sel[1:0]
0
1
2
others
b[7:0]
Mux
c[7:0]
d[7:0]
Sistemes
Digitals I
5.5 Case statement T1 - 55
library i eee;
use i eee. st d_l ogi c_1164.all;
entity casest at ement 2 is
port( num: in i nt eger range 0 to 15;
y : out st d_l ogi c) ;
end casest at ement 2;
architecture a of casest at ement 2 is
begin
process( num)
begin
case numis
when 0| 2| 4| 6| 8| 10| 12| 14 => y <= ' 1' ;
when ot her s => y <= ' 0' ;
end case;
end process;
end a;
Example
Even numbers detector
Sistemes
Digitals I
5.6 Loop statement T1 - 56
Loop statements execute repeatedly a sequence of statements.
There are several loop iteration schemes, but only the one shown
above is supported by Quartus II.
discrete_range specifies the number of iterations. identifier is a
constant within the sequence of statements; it is not allowed as the
target of an assignment statement.
Loop statements may be hard to synthesise.
for i dent i f i er in di scr et e_r ange loop
sequence_of _st at ement s
end loop;
syntax
Sistemes
Digitals I
library i eee;
use i eee. st d_l ogi c_1164.all;
use i eee. st d_l ogi c_unsi gned.all;
entity l oopst at ement 1 is
port( x : in st d_l ogi c_vect or ( 7 downto 0) ;
y : out st d_l ogi c_vect or ( 31 downto 0) ) ;
end l oopst at ement 1 ;
architecture a of l oopst at ement 1 is
begin
process( x)
variable yy : st d_l ogi c_vect or ( 31 downto 0) ;
variable zz : st d_l ogi c_vect or ( 39 downto 0) ;
begin
yy : = ( 0=>' 1' , others=>' 0' ) ; -- yy:="0...01"
for i in 0 to 3 loop
zz : = yy*x;
yy : = zz( 31 downt o 0) ;
end loop;
y <= yy;
end process;
end a;
5.6 Loop statement T1 - 57
Example Implementation of the 4-th power function
POF/Device I/O Pins Logic Elements
l oopst at ement 1
EPM5707144C3 40/ 116( 34%) 534/ 570( 94%)
Report file
The process described
with this statement may
be not synthesizable or
may have an inefficient
implementation
Signal stabilization time
Sistemes
Digitals I
5.7 Wait statement T1 - 58
A wait statement suspends the execution of a process. This
statement is an alternative way to sensitivity lists.
Process execution is suspended until expression becomes
true. When an event occurs on any signal contained in
expression, then expression is evaluated.
wait until expr essi on;
syntax
Sistemes
Digitals I
5.7 Wait statement T1 - 59
Example
as a process with wait statement
library i eee;
use i eee. st d_l ogi c_1164.all;
entity wai t st at ement is
port( d: in st d_l ogi c_vect or ( 7 downto 0) ;
cl k, e, cl r : in st d_l ogi c;
q: out st d_l ogi c_vect or ( 7 downto 0) ) ;
end wai t st at ement ;
architecture b of wai t st at ement is
begin
r : process
begin
wait until ( cl k'event and cl k=' 1' ) ;
if cl r = 1' then q<=( others=>' 0' ) ;
elsif e=' 1' then q<=d;
end if;
end process;
end b;
library i eee;
use i eee. st d_l ogi c_1164.all;
entity wai t st at ement is
port( d: in st d_l ogi c_vect or ( 7 downto 0) ;
cl k, e, cl r : in st d_l ogi c;
q: out st d_l ogi c_vect or ( 7 downto 0) ) ;
end wai t st at ement ;
architecture a of wai t st at ement is
begin
r : process ( cl k)
begin
if cl k'event and cl k=' 1' then
if cl r = 1' then q<=( others=>' 0' ) ;
elsif e=' 1' then q<=d; end if;
end if;
end process;
end a;
8-bit register with
synchronous reset and
synchronous enable
as a process with sensitivity list
sync_reg
d[7..0]
q[7..0]
e
clr
clk
Sistemes
Digitals I
T1 - 60
1 Introduction
2 Data Communication
3 Design Units
4 Dataflow Modelling
5 Behavioural Modelling
6 Structural Modelling
Outline
6.1 Component declaration
6.2 Component instantiation statement
6.3 Recursive generation statement
Sistemes
Digitals I
6. Structural modelling T1 - 61
Top-l evel desi gn Ent i t y
Component 1 Component 1
Desi gn Ent i t y
Component 2
Desi gn Ent i t y
Component L
Desi gn Ent i t y
D
e
c
l
a
r
a
t
i
o
n
E
n
t
i
t
y
Top-level
Architecture
Body
Conc ur r ent St at ement s of Top-l evel
Ar chi t ec t ur e
Structural descriptions are
equivalent to schematic
descriptions.
VHDL hierarchical design:
entities may be used as
components in higher-level
entity descriptions.
Components and
concurrent statements are
interconnected through
signals.
Sistemes
Digitals I
6.1 Component declaration T1 - 62
Component declarations must be in the declarations section of
architecture bodies. They declare entity interfaces that may be used in
component instantiation statements.
Components must be associated with design entities from a library or
must be bound to entities.
ports_definition is similar to an entity declaration: it specifies a name,
mode and type for each port of the component.
Component declarations may also appear in packages and become
visible through library and use clauses.
component i dent i f i er [ is]
{port( por t s_def i ni t i on) ; }
end component [ i dent i f i er ] ;
syntax
Sistemes
Digitals I
6.2 Component instantiation statement T1 - 63
It defines an individual component and associates its ports with
signals of the current design entity.
label is the name of the instance. It is used to individualize
different components of the same kind.
component_name is the identifier used in the component
declaration.
association_list associates one-by-one entity signals with
component ports.
l abel : comp_name [ port map ( associ at i on_l i st ) ] ;
syntax
Sistemes
Digitals I
T1 - 64
Example
library i eee;
use i eee. st d_l ogi c_1164. all;
entity st r uct desi gn is port(
cl k, bi t i n, cl r n : in st d_l ogi c;
q: out st d_l ogi c_vect or ( 3 downto 0) ) ;
end entity st r uct desi gn ;
architecture a of st r uct desi gn is
component df f port(
d, cl k, cl r n : in st d_l ogi c;
pr n : in st d_l ogi c :=1';
q : out st d_l ogi c) ;
end component;
signal x: st d_l ogi c_vect or ( 3 downto 0) ;
signal vcc: st d_l ogi c;
begin
f f 0: df f port map ( d=>bi t i n, cl k=>cl k, cl r n=>cl r n, q=>x( 0) ) ;
f f 1: df f port map ( cl k=>cl k, d=>x( 0) , cl r n=>cl r n, q=>x( 1) ) ;
f f 2: df f port map ( x( 1) , cl k, cl r n, vcc, x( 2) ) ;
f f 3: df f port map ( cl k=>cl k, d=>x( 2) , cl r n=>cl r n, pr n=>vcc, q=>x( 3) ) ;
q <= x; vcc <= 1 ;
end architecture a;
Equivalent Schematic
dff is a primitive
included in a
specific Quartus
II library.
4-bit serial-to-parallel shift register
D flip-flop
declaration
Different
instantiation
styles
6.2 Component instantiation statement
Sistemes
Digitals I
6.2 Component instantiation statement T1 - 65
Example
begin
f f 0: df f port map ( d=>bi t i n, cl k=>cl k, cl r n=>cl r n, q=>x( 0) ) ;
f f 1: df f port map ( cl k=>cl k, d=>x( 0) , cl r n=>cl r n, q=>x( 1) ) ;
f f 2: df f port map ( x( 1) , cl k, cl r n, vcc, x( 2) ) ;
f f 3: df f port map ( cl k=>cl k, d=>x( 2) , cl r n=>cl r n, pr n=>vcc, q=>x( 3) ) ;
q <= x; vcc <= 1 ;
end architecture a;
4-bit serial-to-parallel shift register
If a component port has a default value then it is not necessary to
include its signal assignment in the instantiation statement.
Labels (ff0, ff1 ...) allow
component
individualisation.
A component is
created when an
instantiation
statement is used.
Whenever the name of a port is not used, all
signals must appear in the instantiation, even
those with default values.
Constant values can not be used in
component instantiation statements.
Sistemes
Digitals I
6.3 Recursive generation statement T1 - 66
Generate is used to replicate concurrent statements.
A for generation scheme can describe structures with iterative patterns. The
concurrent_statements are generated repeatedly using the values of identifier
An if generation scheme selects whether the concurrent_statements are
generated or not. Selection is based on the value of expression.
l abel : for i dent i f i er in di scr et e_r ange generate
[ bl ock decl ar at i ons
begin]
concur r ent _st at ement s
end generate;
syntax
l abel : if expr essi on generate
[ bl ock decl ar at i ons
begin]
concur r ent _st at ement s
end generate;
syntax
Sistemes
Digitals I
6.3 Recursive statement generation T1 - 67
Equivalent Schematic
Example n-bit serial-in parallel-out shift register
Serial input
Generate statements are not executed, but expanded as a set of
concurrent statements.
This can provide compact descriptions of regular structures such as
memories, registers and counters.
Parallel output
Serial
output
D flip-flop
whith enable
Sistemes
Digitals I
6.3 Recursive statement generation T1 - 68
library i eee;
use i eee. st d_l ogi c_1164. all;
entity gener at ex is
generic ( n: i nt eger : =8) ;
port( cl k, nr st , s_i n, e : in st d_l ogi c;
p_out : out st d_l ogi c_vect or ( n- 1 downto 0) ;
s_out : out st d_l ogi c ) ;
end entity gener at ex ;
architecture a of gener at ex is
component df f e
port( cl k, cl r n, ena, d : in st d_l ogi c;
pr n : in st d_l ogi c :='1'; q : out st d_l ogi c) ;
end component;
signal x: st d_l ogi c_vect or ( n- 1 downto 0) ;
begin
r eg: for i in 0 to n- 1 generate
d0: if ( i =0) generate
cmp0: df f e port map ( cl k=>cl k, cl r n=>nr st , ena=>e, d=>s_i n, q=>x( 0) ) ;
end generate;
di : if ( i >0 and i <=n- 1) generate
cmpi : df f e port map ( cl k=>cl k, cl r n=>nr st , ena=>e, d=>x( i - 1) , q=>x( i ) ) ;
end generate;
p_out ( i ) <= x( i ) ;
end generate;
s_out <= x( n- 1) ;
end architecture a;
Parameterised register length.
The default value is n=8
Component
declaration
Generation loops
Sistemes
Digitals I
6.3 Recursive statement generation
cmp0: df f e port map( cl k=>cl k, d=>i nput , cl r n=>vcc, ena=>e, q=>x( 0) ;
par al l el out ( 0) <= x( 0) ;
cmpi : df f e port map( cl k=>cl k, d=>x( 0) , cl r n=>vcc, ena=>e, q=>x( 1) ) ;
par al l el out ( 1) <= x( 1) ;
cmpi : df f e port map( cl k=>cl k, d=>x( 1) , cl r n=>vcc, ena=>e, q=>x( 2) ) ;
par al l el out ( 2) <= x( 2) ;
cmpi : df f e port map( cl k=>cl k, d=>x( 2) , cl r n=>vcc, ena=>e, q=>x( 3) ) ;
par al l el out ( 3) <= x( 3) ;
cmpi : df f e port map( cl k=>cl k, d=>x( 3) , cl r n=>vcc, ena=>e, q=>x( 4) ) ;
par al l el out ( 4) <= x( 4) ;
cmpi : df f e port map( cl k=>cl k, d=>x( 4) , cl r n=>vcc, ena=>e, q=>x( 5) ) ;
par al l el out ( 5) <= x( 5) ;
cmpi : df f e port map( cl k=>cl k, d=>x( 5) , cl r n=>vcc, ena=>e, q=>x( 6) ) ;
par al l el out ( 6) <= x( 6) ;
cmpi : df f e port map( cl k=>cl k, d=>x( 6) , cl r n=>vcc, ena=>e, q=>x( 7) ) ;
par al l el out ( 7) <= x( 7) ;
T1 - 69
Example
The compiler expands the generate statements as follows: