1838 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 23, NO.

4, OCTOBER 2008
Enhanced Numerical Breaker Failure Protection
Bogdan Kasztenny, Fellow, IEEE, Vijayasarathi Muthukrishnan, Student Member, IEEE, and
Tarlochan Singh Sidhu, Fellow, IEEE
AbstractBreaker failure (BF) protection provides backup for
circuit breakers (CBs) and associated control wiring. Traditionally,
CBs are not duplicated, but monitored by BF relays when ordered
to trip. Upon a failure of a breaker to interrupt the current, the BF
relay opens adjacent breakers to isolate the problem. The total trip
time under a BF condition is often tightly t into the critical fault
clearance time as determined by systemstability. With narrowsta-
bility limits in todays power systems, coordination margins for the
operation of BF functions are becoming scarce. This imposes a re-
quirement for the fast reset time of BF protection. In its rst part,
this paper presents a novel algorithm for numerical current-based
BFfunction with a fast 0.5-cycle reset time even under severe subsi-
dence current. In the second part, the paper addressed the problem
of fast and secure recognition of binary inputs for both BF initia-
tion and BF detection based on the auxiliary breaker contacts. This
novel algorithmworks with analog representation of binary signals
and provides security under induced transients, battery ground
faults, and other interfering events.
Index TermsBattery ground faults, breaker failure (BF) ini-
tiate, breaker failure (BF) protection, contact bouncing, contact
oxidation, debouncing, subsidence current, switching transients.
I. INTRODUCTION
H
IGH and extra high voltage protection applications call
for duplicated relaying schemes. This includes dupli-
cated relays from different manufacturers or at least of different
models, separate instrument transformers, independent ac
wiring, independent dc wiring, andif possibleduplicated
trip coils in the circuit breakers. For obvious economical and
space limitation reasons, the circuit breakers (CBs) themselves
are not duplicated. Instead, CBs are monitored locally by
breaker failure (BF) relays and in the case of a failure of a given
CB to interrupt the fault current the associated BF relay opens
all surrounding breakers to isolate the problem [1].
Fault clearing time in a BF trip mode is the single most im-
portant specication for any protection system. This time must
coordinate with the critical fault clearance time as determined
by system stability. With the stability limits shrinking the total
BF trip time becomes more challenging to achieve.
The total BF trip time is stacked fromthe worst-case values of
the main protection operating time, trip time of the main breaker,
reset/response time of the BF function, and the trip times of
backup breakers. In the case of remote breakers, teleprotection
Manuscript received May 28, 2007. First published June 27, 2008; current
version published September 24, 2008. Paper no. TPWRD-00424-2007.
B. Kasztenny is with General Electric Company, Markham, ON L6E 1B3
Canada (e-mail: Bogdan.Kasztenny@ge.com).
V. Muthukrishnan and T. S. Sidhu are with The University of Western On-
tario, London, ON N6B 5A9 Canada (e-mail: vmuthukr@uwo.ca; sidhu@eng.
uwo.ca).
Color versions of one or more of the gures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identier 10.1109/TPWRD.2008.917931
time is added as well to account for the time required to send
and receive the direct transfer trip command.
With a typical BF trip time budget of 1012 power cycles, it
becomes obvious that often only one power cycle is available for
the BF reset/response time. Also, considerable security margin
is typically required given large trip zones of the BF relays and
associated consequences for the power system. This calls for
reduction in the BF reset time to well below one power cycle.
BF detection has been traditionally based on either moni-
toring auxiliary contacts of the breaker, or monitoring its cur-
rent. The former method is more economical but historically
proved to be unreliable, and todays applications depend mostly
on the current-based BF detection method [1].
However, subsidence current resulting fromsaturation of cur-
rent transformers (CTs) and large current-to-pickup ratio lead
to long reset times of simplistic overcurrent BF detectors, as ex-
plained in Section II of this paper.
In Section III, this paper presents a novel current-based BF
detector based on differentiating between an alternating pattern
of a true fault current, and a decaying pattern of a subsidence
current. The algorithm is simple to verify and implement, and
ensures a robust 0.5-cycle reset time. The algorithm has been
tested under variety of conditions including heavy CT satura-
tion and other signal distortions. A summary of test results and
sample test cases are included.
In its second part, this paper presents a novel method of pro-
cessing binary inputs of a microprocessor-based relay for crit-
ical applications such as the BF initiating signal or breaker po-
sition sensing via auxiliary contacts. The algorithm is based on
fast analog-to-digital sampling of dc voltages representing bi-
nary inputs to a relay. Provided with ne temporal information
(fast sampling) and ne vertical resolution (A/D conversion),
the new algorithm for recognizing binary inputs is both secure
and fast.
Before the algorithm is described in Section V, a noise model
for the dc voltage representing a binary input is presented rst
in Section IV. This unique work was concerned with identi-
fying signal patterns under typical legitimate and interfering
events such as contact bouncing, battery ground faults including
arcing, transients induced in the control wiring, ac coupling, and
contact oxidation.
BF protection belongs to a local backup protection strategy
compared with remote backup counting on time-coordinated
overreaching remote protection zones to open remote breakers
in order to isolate the fault. The local backup protection phi-
losophy continues to gain momentum as far-reaching distance
zones have been identied culprits of past major blackouts. This
paper supports this direction by delivering better algorithms for
numerical BF protection.
0885-8977/$25.00 2008 IEEE
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KASZTENNY et al.: ENHANCED NUMERICAL BREAKER FAILURE PROTECTION 1839
Fig. 1. Sample current waveform with signicant subsidence (sample relay
record).
II. CHALLENGES FOR CURRENT-BASED BF DETECTION
Fig. 1 presents an example of a fault current successfully in-
terrupted by a CB. The current contains a signicant dc compo-
nent with a relatively slowdecaying rate. Before it is interrupted
after several cycles required by the main protection, interposing
relays, and the breaker itself, such current may saturate the main,
auxiliary (if any) and internal relay interposing CTs. Saturated
CTs will produce a subsidence current in their secondary cir-
cuits [2].
In a CT, when the primary current is interrupted, the ux in
the CT decays from its prevailing level to its residual ux level.
This ux decay introduces a decaying unidirectional current in
the secondary of the CT even when the primary current is zero.
When the CT is driven closer to its saturation point, higher de-
gree of subsidence current is present in the secondary of the CT.
The time constant of the subsidence current depends on CT sec-
ondary circuit time constant and is typically quite long.
The decaying subsidence current signal will energize numer-
ical estimators of magnitude. Root mean square (RMS) estima-
tors will be severely affected and therefore should not be used
for BF current detection [3]. But even algorithms with good l-
tering capabilities are affected. This is due to the fact that the
decaying current contains a wide spectrum of frequencies, in-
cluding the nominal system frequency. Magnitude estimators
of a protective relayby designmeasure in that near-nom-
inal frequency band and, therefore, will see a small portion of
the decaying current as a legitimate system frequency current.
This becomes a problem because of a very large current-to-
pickup ratio resulting fromlowpickup settings typically applied
in the overcurrent detectors of BF functions. The fault current
may reach the level of 20 times the CT rated or more, while
the BF pickup/reset threshold is normally set at a fraction of
CT nominal (10% is typical). As a result, the current-to-pickup
ratio may reach 200:1, if not higher. It takes an extended period
of time for any magnitude estimator to ramp down from a fault
level to such a low reset threshold if there is a decaying subsi-
dence current present.
One approach is to hold back the magnitude estimator and re-
lease it only after the BF coordination timer expires. In numer-
ical implementations this approach is equivalent to articially
lling data windows with zeros, and using real measurements
only after the timer expires. This reduces the problem to some
extent but does not solve it because the decaying subsidence cur-
rent truly contains a small fundamental frequency component.
In a different enhancement of this approach, the measurement
is released only after the current crosses zero, taking advantage
of an observation that the decaying current would not cross zero
[4]. This has a disadvantage of potentially delaying BF opera-
tion upon actual BF. Aheavily offset current crosses zeroes once
a cycle; if such crossing is missed when the BF timer expires,
the subsequent crossover comes after one cycle delaying BF trip
by almost one cycle.
In yet another approach, one may release the magnitude es-
timator when the waveform goes through a peak value. This
would alleviate the problem of potential delay, but peak detec-
tion makes the operation susceptible to transients including tran-
sients induced in the ac wiring during system faults and other
switching operations.
Our approach is based on a simple and robust difference be-
tween the alternating pattern of the fault current and the de-
caying pattern of the subsidence current (Fig. 1).
III. FAST CURRENT-BASED BF DETECTION
A. Algorithm Description
In order to differentiate between the alternating and decaying
patterns, we look at the current through a pair of orthogonal
lters. These lters use short data windows in order not to delay
the ow of information and provide fast operation. As can be
understood better at the end of this section, the lters are not
required to lter out the decaying dc component in the fault
current, or the subsidence current after the fault interruption.
Nor are they required to remove high frequency components
from the fault current.
In this particular application we use a half-wave sine and co-
sine lters with the windows of 1/8th of a power cycle (
while sampling at )
(1a)
(1b)
and
(1c)
The scales are selected to give the lters a unity gain at the
nominal system frequency. Therefore
(1d)
The following ltering is thus performed:
(2)
Effectively, the sine component ( ) represents the current,
and the cosine component ( ) represents its time derivative.
Fig. 2 shows a trajectory of the sample current of Fig. 1 as
seen through the two orthogonal lters (1).
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1840 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 23, NO. 4, OCTOBER 2008
Fig. 2. Trajectory of the current of Fig. 1 using lters (2).
Fig. 3. Simplied fault and subsidence trajectories.
Under clean sine wave, the trajectory is a perfect circle with
the point making one full revolution in each power
cycle. This is visible in Fig. 2 as a small circle of the prefault
load current.
Signal distortions affect both orthogonal components in the
current and result in a departure of the trajectory from its ideal
circular shape. In particular, the decaying dc component in the
fault current offsets the cosine component and shifts the con-
tours along the axis. Still, the alternating nature of the fault
current is clearly visible in the trajectory as the point
keeps rotating at approximately a constant angular speed of
360 per cycle.
When the primary current is cleared and the subsidence cur-
rent is created, the trajectory changes dramatically. It stops ro-
tating, and starts moving toward the origin of the plane.
In this particular case of Fig. 2, the interruption occurred at
positive polarity of the current. Therefore, the decaying trajec-
tory moves in the second quadrant of the plane. Fig. 3 presents
a simplied version of Fig. 2 with both possible polarities of
the subsidence current. Note that the angles of subsidence tra-
jectory are always around 110120 for positive polarity and
for negative polarity. This results from a simple
observation that a positive decaying signal has a negative deriva-
tive (or else it would not decay), and the negative decaying
signal has a positive derivative (or it would not decay).
Fig. 4. Characteristics for detecting subsidence trajectories.
The exact path of decay depends on the applied lters and CT
characteristic. It does not depend on the fault or system charac-
teristics, as during the subsidence the fault is not present. The
shape of the reset trajectory does not change much. A subsi-
dence current resembles an exponential function and, thus, its
derivative is an exponential function as well as proportional to
the time constant of the decay. Note that no high frequency com-
ponents are expected during the subsidence period.
Observations from Figs. 2 and 3 allow shaping two detection
regions for our fast BF reset algorithm (Fig. 4).
During subsidence, the current vector stays within
one of the two characteristics shown.
During fault conditions, the vector stays within any of
the regions for only about 1/8th of a cycle assuming a 45
boundary line.
The characteristics of Fig. 4 are accomplished with the fol-
lowing simple equations:
(3a)
(3b)
where is an overcurrent threshold (user setting) and is the
slope of the characteristics (factory constant of about 1.0).
The subsidence current not only ceases to rotate, it has a much
lower derivative compared with its value . This obser-
vation is a direct consequence of the two signals being exponen-
tial functions tied together with the time constant of the decay
(4a)
(4b)
In other words during subsidence, the two orthogonal com-
ponents exhibit the following ratio:
(4c)
where is the radian system frequency and is the decaying
time constant of the subsidence current.
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KASZTENNY et al.: ENHANCED NUMERICAL BREAKER FAILURE PROTECTION 1841
Fig. 5. Explanation of supervisory condition (6). (a) Subsidence current.
(b) Current reversal.
As the time constant is relatively long, the ratio in (4c) is
relatively small (example, in a 60 Hz system with a 100 ms time
constant, the ratio is 0.027).
We use this observation to strengthen our algorithm. A super-
visory ag is created as follows:
(5)
where is xed at about 0.75 and is introduced to ensure
the condition is met with the current at the noise level.
Note that given (4c) and the value of the aforementioned
supervisory condition will not engage if the time constant
of the decay is very short (shorter than 0.21 of a cycle for
of 0.75). This is not a problem, however, when the decay is
that fast, the subsidence current will disappear in about half a
cycle and the algorithm will reset naturally due to the factor
in condition (5).
Current reversals create another concern for our algorithm.
During current reversals, the trajectory dramatically changes its
angular position. In particular, it may shift in the direction op-
posite the natural direction of rotation. As a result, the trajectory
may spend more time in either of the two operating regions de-
ned by (3a) and (3b) and inadvertently trigger our algorithm to
reset.
To prevent this, a simple observation is utilized that when the
fault is cleared, the fast value of is much lower than the stan-
dard full-cycle amplitude ( ). On the other hand, when the
current is reversing its phase, the fast is signicant or typi-
cally higher compared with the standard full-cycle magnitude.
Based on that, a second supervisory ag is calculated as follows:
(6)
where is an algorithm constant of 0.75 assuming a full cycle
Fourier estimator.
The meaning of condition (6) can be understood better with
reference to Fig. 5. Condition (6) narrows the two detection re-
gions of Fig. 4 in proportion to the full-cycle magnitude esti-
mate. When clearing a fault, the full-cycle magnitude is stabi-
lized and reects the fault level. As such, it satises condition
(6) and opens the detection regions fully [Fig. 5(a)]. During
a load-to-fault current reversal of the full-cycle magnitude is
small, and it narrowsvia condition (6)the detection regions
Fig. 6. Fast reset algorithm incorporated into a classical logic with full-cycle
magnitude estimation.
[Fig. 5(b)]. During reversals of the fault current, the cosine com-
ponent (current derivative) is large and will not trigger the algo-
rithm spuriously even with condition (6) satised.
The reset ag in our algorithm is asserted as follows:
(7)
Flag (7) is asserted only for short periods of time under the
rotating pattern of the current (for about 1/8th of a cycle for
of 1.0). On the other hand, ag (7) is asserted permanently
under the subsidence pattern. Therefore a simple timer is used
to differentiate between the two conditions. A security factor of
3 is assumed and we use a timer of 3/8th of a cycle: if ag (7) is
asserted for 3/8th of a cycle, the current is declared reset (RST
ag asserted). If subsequently ag (7) resets and stays dropped
out for 3/8th of a cycle, an overcurrent condition is declared and
the BF function operates (RST ag deasserted).
In reference to Fig. 6, the fast reset path dened by our al-
gorithm works as an overlay with a standard Fourier-based al-
gorithm. The full-cycle magnitude estimator is used to declare
a pickup condition for the BF overcurrent detector. Once in the
pickup state, the detector resets using the full cycle magnitude
( is a hysteresis), or via the RST condition described before.
As long as the RST condition is asserted, the detector is inhib-
ited from picking up.
B. Illustration of the Algorithm Operation
For illustration, let us explore the case of CT saturation. Se-
vere saturation will produce periods in the current waveform in
which the current is low and relatively at. This may confuse
fast BF reset algorithms.
Fig. 7 presents a case of considerable CT saturation. Note the
periods when the current is distorted. At the rst glance, these
periods resemble subsidence. After close examination, however,
one discovers that the pattern is differentthe saturated cur-
rent still increases, even if only marginally, while the true sub-
sidence current decays. This demonstrates itself in a very clear
way when looking at the current trajectory (Fig. 8). CT satura-
tion brings the trajectory closer to the origin and slows it down
in the rst or third (depending on polarity of the dc offset) quad-
rant, or in both rst and third quadrants under symmetrical sat-
uration. The subsidence places the trajectory in the second or
fourth quadrants (depending on polarity of the secondary cur-
rent when clearing the fault). This ensures very robust separa-
tion between the CT saturation and subsidence patterns. Note
that our algorithm does not respond to saturated waveform, yet
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1842 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 23, NO. 4, OCTOBER 2008
Fig. 7. Operation of the algorithm under CT saturation. (a) Current waveform,
raw RST and nal RST ags. (b) Details of the reset moment.
Fig. 8. Trajectory of the current of Fig. 7.
still resets in less than 0.5 of a cycle once the fault is cleared
[Fig. 7(b)].
C. Test Results
The algorithm has been tested using realistic waveforms as
recorded by a sample microprocessor-based relay. As such, the
test waveforms reect the behavior of the relay input circuitry
including A/Dresolution, isolating current transformers, analog
lters, and so on. The test cases include fault currents with the
following variability:
decaying dc offset;
dc time constant;
saturation of CTs;
current reversal;
articially added noise.
Transformer magnetizing inrush currents and cases of ex-
treme symmetrical CT saturation have been considered as well.
Table I summarizes the results using a sample, older genera-
TABLE I
TEST RESULTS FOR THE FAST RESET OVERCURRENT ALGORITHM
tion numerical relay for comparison. Both the algorithm and the
relay apply a BF dropout threshold of 0.1 CT nominal.
IV. NOISE MODEL FOR BINARY RELAY INPUTS
Fast and secure identication of binary states is important
for BF protection from the perspective of BF initiation and CB
position detection.
This section presents a noise model for the task of fast recog-
nition of binary inputs of a microprocessor-based relay. This in-
cludes contact bouncing, impact of ground faults in the battery
system, induced transients, contact oxidation, and ac coupling.
The nature of those interfering factors must be understood be-
fore any reliable algorithm for fast identication of the binary
inputs can be developed.
A. Contact Bouncing
Contact bouncing is a mechanical phenomenon associated
with a rapid movement of contacts of a given relay. After
making the initial connection, the moving contact can bounce
back only to be pulled in again by the armature. The exact
bouncing pattern and duration depend on the construction of
a given relay including its mechanical damping and speed of
operation, type of contact material, but also on the wetting
voltage level and connected burden.
The phenomenon is not limited to heavy-duty electromechan-
ical relays only. Mechanical output contacts on modern micro-
processor-based relays are subject to minor bouncing as well.
Quite often, their coils are overdriven for speed, which results
in contact bouncing. Solid-state outputs and fast contacts not
rated for direct operation of breaker coils behave signicantly
better.
Fig. 9(a) presents a sample case of contact bouncing.
B. Contact Oxidation
Contacts that are not hermetically sealed are exposed to at-
mospheric conditions and are subject to oxidation and accumu-
lation of dirt particles, moisture, frost, and other factors. De-
pending on the wetting voltage level, level and type of burden,
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KASZTENNY et al.: ENHANCED NUMERICAL BREAKER FAILURE PROTECTION 1843
Fig. 9. Sample transients in the dc input voltage. (a) Contact bouncing.
(b) Solid dc ground fault. (c) Momentary dc ground fault. (d) High-frequency
switching transient.
and the amount of accumulated particles, it may take some nite
time to cause breakdown of such a layer and make robust elec-
trical contact. This phenomenon is of particular concern when
using microprocessor-based relays (very low burden) to read
auxiliary contacts of breakers (pallet switches). Atraditional ap-
proach to oxidation is to apply a larger burden and drawfewtens
of milliamperes of current to burnish a dirty contact. This is
done either permanently or more typically for a short time to
limit heat dissipation on binary inputs of modern relays.
C. Ground Faults in the DC System
Ground faults in dc cabling are difcult to locate and may
exist for extended periods of time before the problem is identi-
ed and rectied. These faults can be permanent or intermitted
and, thus, involve some amount of arcing. Ground faults create
classical capacitor discharge patterns for the binary relay inputs.
The dc cabling system may total thousands of meters in a large
substation and therefore have a large total capacitance. Upon
a ground fault these capacitors charge/discharge through high
resistance of binary inputs of relays creating spurious voltage
drops across those inputs which may lead to spurious assertion
of the binary states.
Fig. 9(b) presents a sample waveform for the case of a solid
battery ground fault; and Fig. 9(c) shows a case of a momentary
(arcing) fault.
Traditionally, an intentional delay is applied to ride through
dc ground fault conditions. With large total capacitance and low
burden of modern relays, however, the required delay may be
in the range of many milliseconds slowing down some time-
critical protection applications.
The problem is particularly visible with microprocessor-
based relays. Quite often these relays aim for very high density
of binary inputs, and can afford relatively low heat dissipation
(high input resistance). Electromechanical relays naturally
burden their cables with 510 mA current, effectively damping
the capacitive discharge. Modern numerical relays often draw
only 23 mA of current. External resistors are sometimes used
to help suppress the capacitive discharge transients allowing
shorter debounce timer settings.
D. Switching Transients
Transients can be induced in the control cables either from
the primary equipment or other control cables when breaking
heavy inductive loads, such as trip coils, interposing and lockout
relays, etc. Typically these transients are of high frequency and
magnitude [Fig. 9(d)] and, therefore, can be ltered out by a
simple debouncing timer.
E. AC Coupling
Alternating current can couple into dc cabling and poten-
tially cause problems for binary inputs if they are too sensitive.
Shielding, proper spacing, and cable routing solve the problem
in combination with debounce timers.
F. Experimental Studies
A number of different output contacts have been studied in-
cluding mechanical and solid state outputs on modern micropro-
cessor-based relays, electromechanical relays, and auxiliary re-
lays. Various loads have been considered varying from a binary
input of a relay through a simulated breaker trip coil. Various
wetting voltage levels have been considered from24 Vto 125 V.
Cable capacitances have been modeled by discrete capacitors
[5]. An experimental test bed has been congured with a digital
scope to provide for high-speed capture of the dc voltage at the
input terminals to a binary relay input.
Examples in Fig. 9 have been generated using our laboratory
setup.
V. BINARY RECOGNITION ALGORITHM
Analog-to-digital converter circuits became affordable in re-
cent years nding their way into processing of binary inputs on
latest generations of protective relays. One particular solution
samples at 4 kHz and uses a 12-b converter for the 0300 Vdc
input range.
Our algorithm works with such digitized dc voltages at the
binary inputs of the relay. The solution uses a decaying pattern
of the voltage to identify the case of spurious signals during dc
battery ground faults, and randomness of the voltage to identify
cases of contact bouncing, induced switching transients and the
effect of oxidation.
First, the input dc voltage is compared with the full wet-
ting voltage
(8)
where the lower and upper limits are set approxi-
mately at 0.7 and 1.3, respectively; and is a 4 kHz sample
index.
The upper limit is applied in order to lter out some of the
switching transients that may generate voltages above the bat-
tery nominal. These transients are suppressed to a certain extent
by the relay input circuitry, but still condition (8) benets our
algorithm.
The battery voltage in (8) can be the nominal value, or can
be measured, typically at slow scan rates. The latter becomes a
common practice on the newest generation of microprocessor-
based relays. With a dynamically tracked battery voltage, the
30% limits in (8) may be narrowed down for extra security.
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1844 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 23, NO. 4, OCTOBER 2008
Next, the input voltage is processed using mean lters of two
different lengths
(9a)
(9b)
The long window average (9a) is computed on eight samples
of the 4 kHz stream( ) and, thus, covers 2 ms of data. The
short window average is computed on three samples ( ).
The long and short time averages are used to detect the expo-
nential pattern of an RC decay for ground faults in the battery
system. The following ag is asserted to detect this condition:
(10)
where is a factory constant of approximately 0.95.
The blocking condition (10) can be better understood as fol-
lows. Blocking takes place only if the long term mean is within
the validation band near the battery voltage, and is asserted
if the consecutive short-term averages become smaller (a de-
caying pattern). In addition, the newest short-term average in
the window must show some decrease compared with the oldest
sample of the raw dc voltage in the observation window.
Measuring variance in the observed voltage allows dynamic
debouncing
(11)
The second condition is asserted as follows:
(12)
where species a maximum variance (a factory constant of
approximately ).
Finally, a given binary input is declared asserted (on) if
(13)
The presented algorithm has been tested using a set of cases
generated in our laboratory setup with physical relays and loads.
Fig. 10 presents two examples. Figure (a) shows a case of bat-
tery ground fault successfully rejected by our algorithm. Figure
(b) is a case of a low-quality contact showing a combination of
bouncing and oxidation. The input is declared on in less than
3 ms after it settles on an unambiguous value.
Fig. 10. Example of operation of the binary algorithm. (a) Battery ground fault.
(b) Bouncing and oxidation.
TABLE II
TEST RESULTS FOR THE BINARY ALGORITHM UNDER TRANSIENTS
TABLE III
TEST RESULTS FOR THE BINARY ALGORITHM UNDER BOUNCING
In terms of time stamping of events, the algorithm rst iden-
ties the input and validates it for subsequent usage. In the case
of Fig. 10(b), the signal is declared on at about 12.5 ms. Next,
if the signal changed state, the algorithm reaches back and lo-
cates the true beginning of the event. In this respect, two options
are possible. Either the edge of the data window leading to sub-
sequent state validation is time stamped (9.5 ms in Fig. 10(b),
or the earliest activity in a given assumed time frame is time
stamped [3 ms in Fig. 10(b)].
Tables II and III summarize some of our test results for the
binary input algorithm.
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KASZTENNY et al.: ENHANCED NUMERICAL BREAKER FAILURE PROTECTION 1845
VI. CONCLUSION
This paper presented two algorithms for enhanced numerical
BF protection.
The fast reset algorithm for current-based BF detector is
based on differentiating between the rotating pattern of a fault
current and the decaying pattern of a subsidence current. The
algorithm is simple, yet very fast and robust. It uses few factory
constants, but they have well-dened meanings and can be
easily ne tuned in any particular implementation that follows
our approach.
The algorithm can be further enhanced by recognizing that
when the current vector stops rotating and starts decaying due
to subsidence, it actually rotates at a signicantly lower rate, but
in the opposite direction compared with an alternating current.
This reversal of the angular speed can be used to strengthen and
speed up the algorithm.
The fast recognition algorithm for binary inputs works with
digitized dc voltages. This novel approach nds its way in
modern relay implementations, yet is an unexplored topic
in terms of research and prior art. We have identied and
quantied various noise patterns that can be present in binary
input signals. Developed based on the noise characteristics, our
identication algorithm is fast and reliable.
Both algorithms have been extensively tested using actual re-
lays and their input circuitries showing consistent and robust
performance.
REFERENCES
[1] IEEE Guide for Breaker Failure Protection of Power Circuit Breakers,
IEEE Std. C37.1192005.
[2] U. D. Annakkage and P. G. McLaren, A current transformer model
based on the Jiles-Atherton theory of ferromagnetic hysteresis, IEEE
Trans. Power Del., vol. 15, no. 1, pp. 5761, Jan. 2000.
[3] N. T. Stringer and D. Waser, An innovative method of providing total
breaker failure protection, IEEE Trans. Ind. Appl., vol. 32, no. 5, pp.
10111016, Sep. 1996.
[4] H. J. Altuve, M. J. Thompson, and J. Mooney, Advances in breaker
failure protection, presented at the 33rd Western Protective Relay
Conf., Spokane, WA, 2006.
[5] AFC Cable Systems Cable Catalog, 2006. [Online]. Available: www.
afcweb.com.
Bogdan Kasztenny (M95SM98F08) is Protection and System Engi-
neering Manager for the Digital Energy business of General Electric (GE),
Markham, ON, Canada. Prior to joining GE in 1999, he was an Assistant Pro-
fessor conducting research and teaching power system courses at the Wroclaw
University of Technology, Wroclaw, Poland; Texas A&M University, College
Station, TX; and Southern Illinois University, Carbondale. Between 2000 and
2004, he was heavily involved in the development of the globally recognized
Universal Relay product line. He remains hands on and is instrumental in new
product development at GE, acting as an R&D liaison with several universities
and corporate research. He has authored more than 160 papers, conceived
numerous protection and control products, and is an inventor of several patents.
Dr. Kasztennys full-time academic career culminated with a prestigious Se-
nior Fulbright Fellowship in 1997. He received GEs Thomas Edison Award for
innovation regarding the Universal Relay product line. He is a member of the
main committee of the IEEE Power & Energy Society Power System Relaying
Committee, where he chairs or co-chairs several working groups. He is a reg-
istered Professional Engineer in the province of Ontario, an Adjunct Professor
at the University of Western Ontario, and a member of the Canadian National
Committee of CIGRE, Study Committee B5Protection and Automation.
Vijayasarathi Muthukrishnan (S05) received the B.Tech. degree from the
Pondicherry Engineering College, Pondicherry, India, in 1998 and is currently
pursuing the M.E.Sc. degree in electrical and computer engineering at the Uni-
versity of Western Ontario, London, ON, Canada.
He was a Technical Advisor and Field Engineer with GE Energy and Alstom
Ltd. from 1998 to 2005. He has supervised the commissioning of protection
systems and excitation control systems at various power stations in Asia and
Africa. His area of interests are power system protection and generator excita-
tion control.
Tarlochan Singh Sidhu (M90SM94F04) received the B.E. (Hons.) de-
gree from Punjabi University, Patiala, India, in 1979 and the M.Sc. and Ph.D.
degrees from the University of Saskatchewan, Saskatoon, SK, Canada, in 1985
and 1989, respectively.
Previously, he was with the Regional Computer Center, Chandigarh, India;
the Punjab State Electricity Board, India; and Bell-Northern Research Ltd., Ot-
tawa, ON, Canada. From 1990 to 2002, he was a Faculty Member in the Depart-
ment of Electrical Engineering, University of Saskatchewan, where he served as
Professor and Graduate Chair of the Department. Currently, he is Chair of the
Department of Electrical and Computer Engineering and Professor and Hydro
One Chair of Power Systems Engineering at the University of Western Ontario,
London, ON, Canada. His areas of research interest are power system protec-
tion, monitoring, and control.
Dr. Sidhu is a Fellow of the Institution of Electrical Engineers (U.K.) and the
Institution of Engineers (India). He is also a Registered Professional Engineer
in the Province of Ontario and a Chartered Engineer in the U.K.
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