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Libraries Guide www.xilinx.

com 201
ISE 6.3i 1-800-255-7778
CB2CLE, CB4CLE, CB8CLE, CB16CLE
R
CB2CLE, CB4CLE, CB8CLE, CB16CLE
2-, 4-, 8-, 16-Bit Loadable Cascadable Binary Counters with Clock
Enable and Asynchronous Clear
CB2CLE, CB4CLE, CB8CLE, and CB16CLE are, respectively, 2-, 4-, 8-, and 16-bit
(stage) synchronously loadable, asynchronously clearable, cascadable binary
counters. The asynchronous clear (CLR) is the highest priority input. When CLR is
High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock
enable out (CEO) go to logic level zero, independent of clock transitions. The data on
the D inputs is loaded into the counter when the load enable input (L) is High during
the Low-to-High clock transition, independent of the state of clock enable (CE). The Q
outputs increment when CE is High during the Low-to-High clock transition. The
counter ignores clock transitions when CE is Low. The TC output is High when all Q
outputs are High.
Larger counters are created by connecting the CEO output of the first stage to the CE
input of the next stage and connecting the C, L, and CLR inputs in parallel. CEO is
active (High) when TC and CE are High. The maximum length of the counter is
determined by the accumulated CE-to-TC propagation delays versus the clock period.
The clock period must be greater than n(t
CE-TC
), where n is the number of stages and
the time t
CE-TC
is the CE-to-TC propagation delay of each stage. When cascading
counters, use the CEO output if the counter uses the CE input; use the TC output if it
does not.
The counter is asynchronously cleared, output Low, when power is applied.
For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on
condition can be simulated by applying a High-level pulse on the PRLD global net.
Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-
II Pro X simulate power-on when global set/reset (GSR) is active.
GSR defaults to active-High but can be inverted by adding an inverter in front of the
GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX,
or STARTUP_VIRTEX2 symbol.
Architectures Supported
CB2CLE, CB4CLE, CB8CLE, CB16CLE
Spartan-II, Spartan-IIE No
Spartan-3 No
Virtex, Virtex-E No
Virtex-II, Virtex-II Pro, Virtex-II Pro X No
XC9500, XC9500XV, XC9500XL Macro
CoolRunner XPLA3 Macro
CoolRunner-II Macro
Q0
X4354
CB2CLE
C
CLR
CE
Q1
TC
CEO
L
D1
D0
X4358
CB4CLE
L
CE
C
D3
D2
D1
D0
Q3
Q2
Q1
Q0
CLR
CEO
TC
Q[7:0]
X4362
CB8CLE
C
CLR
CE
TC
D[7:0]
L
CEO
Q[15:0]
X4366
CB16CLE
C
CLR
CE
TC
D[15:0]
L
CEO
CB2CLE, CB4CLE, CB8CLE, CB16CLE
R
202 www.xilinx.com Libraries Guide
1-800-255-7778 ISE 6.3i
CB8CLE Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E,
Virtex-II, Virtex-II Pro, Virtex-II Pro X
Inputs Outputs
CLR L CE C Dz D0 Qz Q0 TC CEO
1 X X X X 0 0 0
0 1 X Dn Dn TC CEO
0 0 0 X X No Chg No Chg 0
0 0 1 X Inc TC CEO
z= 1 for CB2CLE; z = 3 for CB4CLE; z = 7 for CB8CLE; z = 15 for CB16CLE
TC = QzQ(z-1)Q(z-2)...Q0
CEO = TCCE
CLR
C
Q
D
FTCLEX
Q0
CE
CLR
C
Q
D
FTCLEX
Q1
CE
Q0
Q1
VCC
T
L
T
L
D0
D1
CLR
C
Q
D
FTCLEX
Q2
CE
Q2
T
L
D2
CLR
C
Q
D
FTCLEX
Q3
CE
Q3
T
L
D3
CLR
C
Q
D
FTCLEX
Q4
CE
Q4
T
L
D4
CLR
C
Q
D
FTCLEX
Q5
CE
Q5
T
L
D5
CLR
C
Q
D
FTCLEX
Q6
CE
Q6
T
L
D6
CLR
C
Q
D
FTCLEX
Q7
CE
Q7
T
L
D7
AND2
AND3
AND4
AND2
AND3
AND5
AND4
TC
CEO
AND2
L
CE
C
CLR
Q[7:0]
D[7:0]
T2
T3
T4
T5
T6
T7
X8135
OR2
OR_CE_L
CB2CLE, CB4CLE, CB8CLE, CB16CLE
R
Libraries Guide www.xilinx.com 203
ISE 6.3i 1-800-255-7778
CB2CLE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
CB8CLE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II
Usage
For HDL, these design elements are inferred rather than instantiated.
AND2
FDC
D
C
Q TC
X7780
Q0
CLR
CE
D1
AND2
VCC
AND3
XOR2
D
C
Q
Q1
CLR
FDC
AND2
CEO
Q1
Q0
AND2B1
XOR2
OR2
OR2
AND2B1
L
AND2
AND3B1
GND
OR2
AND2B1
D0
C
CLR
Q0
CB2
Q1
CB2CLE
CLR
CE CEO
C TC
Q0
CB0
Q1
CB2CLE
CLR
CE CEO
C TC
CE
AND4
Q0
CB4
Q1
CB2CLE
CLR
CE CEO
C TC
Q0
CB6
Q1
CB2CLE
CLR
CE CEO
C TC
TC
CEO
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
C
CLR
X8130
D0
D1
D0
D1
D0
D1
D0
D1
D0
D1
D2
D3
D4
D5
D6
D7
L
L
L
L
L
D[7:0] Q[7:0]
CB2CLE, CB4CLE, CB8CLE, CB16CLE
R
204 www.xilinx.com Libraries Guide
1-800-255-7778 ISE 6.3i

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