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GND 2 13 12VCC
DSP Supplies
GND 3 12 NC
• Embedded processor and I/O supplies 5VCC 4 11 NC
DRIVE2 5 10 NC
FB2 6 9 FB
NC 7 8 NC
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
Package Code
APW 7060 K : SOP-14
Operating Junction Temp. Range
Lead Free Code C : 0 to 70°C
Handling Code Handling Code
Temp. Range TU : Tube TR : Tape & Reel
Lead Free Code
Package Code
L : Lead Free Device Blank : Original Device
Notes: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte in plate
termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldiering
operations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C for
MSL classification at lead-free peak reflow temperature.
Block Diagram
5VCC 12VCC
Under UGATE
Voltage
Lockout
PW M Gate
UVLO
Control
Soft-Start
5VC C
and Fault
0.5V UVP1 Logic
LGATE
Inhibit /
Soft-Start
UVP2 FB2
C O MP
FB 0.5V 12VC C
Error
Am plifier
VREF DRIVE2
Shutdown 1.28V Linear
0.8V C ontroller
Oscillator F O SC
600kH z GND
Figure 1.
Typical Application
R4
+12 V +5V L2
C8 2. 2 1uH
C1
1uF VIN 1
1uF
13
4
VIN 2 C4
+3.3V
12VC C 5VC C C 2, C 3
+3.3V 4. 7uF
2 x 470uF
Q1
C 10
Q3 L1
470uF 14
UGATE 1uH
5
D R IVE2
VOU T1
+1.26 3 V
R 10 1 D1 C 5, C 6 /10 A
6. 8k LGA TE
2 x 470uF
U1 Q2
C9 AP W 7060 R1
470pF 590
9
FB
VOU T2 6
FB2
+2.5V/3A
R7
2. 37k R8
C 11
1. 13k GN D GN D C7
470uF R2
68nF
2
1. 02k
Q1 : APM2014N UC
Q2 : APM2014N UC
Q3 : APM2055N UC
D1 : 3A Schottky Diode
C2, C3, C5, C6, C10, C11 : 470uF/6.3V, ESR=30mΩ
Figure 2.
Thermal Characteristics
Electrical Characteristics
Unless otherwise specified, these specifications apply over 5VCC=5V, 12VCC=12V and TA= 0~70 oC. Typical
values are at TA=25oC.
APW7060
Symbol Parameter Test Conditions Unit
Min Typ Max
SUPPLY CURRENT
ICC 5VCC Supply Current LGATE Open, FB2=DRIVE2 2.5 mA
12VCC Supply Current UGATE Open 2.5 mA
UNDER VOLTAGE LOCKOUT
Rising 5VCC Threshold 12VCC=12V 4.0 4.2 4.4 V
Falling 5VCC Threshold 12VCC=12V 3.8 4.0 4.2 V
Rising 12VCC Threshold 5VCC=5V 9.6 10.3 10.8 V
Falling 12VCC Threshold 5VCC=5V 9.3 9.7 10.2 V
OSCILLATOR
FOSC Free Running Frequency 550 600 650 kHz
Ramp Upper Threshold 2.85 V
Ramp Lower Threshold 0.95 V
∆VOSC Ramp Amplitude 1.9 VP-P
REFERENCE VOLTAGE
VREF Reference Voltage 0.8 V
Over Line, Load and
System Accuracy -2 +2 %
Temperature
DRIVE2 (Pin 5) This pin provides the supply voltage to the high side
This pin provides the gate drive voltage for the linear MOSFET driver and the linear controller. A voltage no
regulator N-channel MOSFET pass transistor. It also greater than 13V can be connected to this pin. The
provides a means of compensating the linear control- voltage at this pin is monitored for undervoltage lock-
ler for applications where the user needs to optimize out (UVLO) purposes.
the regulator transient response. UGATE (Pin 14)
FB2 (Pin 6) This pin provides gate drive for the high-side MOSFET.
Connect this pin to the output (VOUT2) of the linear
regulator via a proper sized resistor divider. The volt-
age at this pin is regulated to 0.8V and the VOUT2 is
determined using the following formula :
R7
VOUT2=0.8V x (1+ R8 )
Typical Characteristics
630
0.808
620
0.804
610
0.800 600
590
0.796
580
0.792
570
0.788
560
0.784 550
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
IOUT = 0A -> 10A IOUT = 0A -> 10A -> 0A IOUT = 10A -> 0A
VOUT1 VOUT1
VOUT1
VUGATE VUGATE
10A
IOUT1
IOUT1
0A IOUT1
Ch1 : VOUT1, 100mV/Div, DC, Ch1 : VOUT1, 100mV/Div, DC, Ch1 : VOUT1, 100mV/Div, DC,
Offset = 1.25V Offset = 1.25V Offset = 1.25V
Ch2 : VUGATE, 10V/Div, DC Ax1 : IOUT1, 5A/Div Ch2 : VUGATE, 10V/Div, DC
Ax1 : IOUT1, 5A/Div Time : 100µS/Div Ax1 : IOUT1, 5A/Div
Time : 5µS/Div BW = 20MHz Time : 5µS/Div
BW = 20MHz BW = 20MHz
IOUT = 0.2A -> 3A IOUT = 0.2A -> 3A -> 0.2A IOUT = 3A -> 0.2A
VOUT2 VOUT2
VOUT2
3A
IOUT2
IOUT2
0.2A
IOUT2
Ch1 : VOUT2, 50mV/Div, DC, Ch1 : VOUT2, 50mV/Div, DC, Ch1 : VOUT2, 50mV/Div, DC,
Offset = 2.50V Offset = 2.50V Offset = 2.50V
Ax1 : IOUT2, 1A/Div Ax1 : IOUT2, 1A/Div Ax1 : IOUT2, 1A/Div
Time : 1µS/Div Time : 50µS/Div Time : 1µS/Div
BW = 20MHz BW = 20MHz BW = 20MHz
3. Powering ON / OFF
VOUT2 VOUT2
VOUT1 VOUT1
VLGATE VLGATE
Application Information
Soft Start Maximum Output Voltage of Linear Controller
Soft start can be initiated in several ways. One way is The maximum drive voltage at DRIVE2 is determined
when the input bias supply to the 5VCC and 12VCC by the applied voltage at 12VCC pin. Since this pin
is above 4.2V and 10.2V respectively. The other way drives an external N-channel pass MOSFET, there-
is when the part comes out of shutdown. In both ways, fore the maximum output voltage of the linear regula-
the soft start cycle will last for 2ms. During this period, tor is dependent upon the required gate-to-source volt-
the reference to the error amplifier of the PWM con- age to sustain the load current.
troller and linear controller will gradually slew up to its
final value of 0.8V. This effectively will force both out- VOUT2MAX = 12VCC - VGSpass
put voltages to track this reference ramp rate. Hence
both outputs will reach regulation at the same time.
Figure 3 illustrates this graphically. Component Selection Guidelines
Application Information
Inductor Selection PUPPER = Iout2 (1+ TC)(RDS(ON))D + (0.5)(Iout)(VIN)(tsw)FS
The inductance of the inductor is determined by the
output voltage requirement. The larger the inductance, PLOWER = Iout2 (1+ TC)(RDS(ON))(1-D)
the lower the inductor’s current ripple. This will trans-
late into lower output ripple voltage. The ripple current where IOUT is the load current
and ripple voltage can be approximated by: TC is the temperature dependency of RDS(ON)
FS is the switching frequency
V OUT
VIN - VOUT tsw is the switching interval
IRIPPLE = ×
Fs× L V IN D is the duty cycle
Application Information
where Iout is the maximum load current • The ground return of CIN must return to the combine
Vout2 is the nominal output voltage COUT (-) terminal.
• Capacitor CHFis to improve noise performance and
In some applications, heatsink maybe required to help
a small 1uF ceramic capacitor will be sufficient. Place
maintain the junction temperature of the MOSFET be-
this capacitor close of the drain of Q1.
low its maximum rating.
• Inductor L1 should be connected closely to the
V DS PHASE node.
• Bypass capacitors, CBP, should be placed as close
to the 5VCC and 12VCC pins.
drain and source of MOSFET
VIN
Voltage across
CHF
5VCC
5VCC
CBP
GND
+
GND CIN
CBP
t sw Time 12VCC
12VCC
Figure 4. Switching waveform across MOSFET UGATE
Q1 Q2 COUT
Layout Considerations LGATE
+
In high power switching regulator, a correct layout is APW7060
PHASE
important to ensure proper operation of the regulator. L1 VOUT
In general, interconnecting impedances should be mini-
mized by using short, wide printed circuit traces. Sig- Figure 5. Recommended Layout Diagram
nal and power grounds are to be kept separate and
finally combined using ground plane construction or
single point grounding. Figure 5 illustrates the layout,
with bold lines indicating high current paths. Compo-
nents along the bold lines should be placed close
together. Below is a checklist for your layout:
• Keep the switching nodes (UGATE, LGATE and
the PHASE) away from sensitive small signal nodes
since these nodes are fast moving signals. There
fore keep traces to these nodes as short as
possible.
• Decoupling capacitor CIN provides the bulk capaci
tance and needs to be placed close to the drain of
Q1.
Copyright ANPEC Electronics Corp. 12 www.anpec.com.tw
Rev. A.5 - Mar., 2005
APW7060
Package Information
SOP – 14 (150mil)
0 . 01 5 x 4 5
H
E
A
0 . 0 10
A
A1
Ee B
Millimeters Inches
Dim
Min. Max. Min. Max.
A 1.477 1.732 0.058 0.068
A1 0.102 0.255 0.004 0.010
B 0.331 0.509 0.013 0.020
C 0.191 0.2496 0.0075 0.0098
D 8.558 8.762 0.336 0.344
E 3.82 3.999 0.150 0.157
e 1.274 0.050
H 5.808 6.215 0.228 0.244
L 0.382 1.274 0.015 0.050
θ° 0° 8° 0° 8°
Physical Specifications
Terminal Material Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb
Lead Solderability Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
Packaging 2500 devices per reel
TP tp
Critical Zone
T L to T P
Ram p-up
TL
tL
Temperature
Tsm ax
Tsm in
Ram p-down
ts
Preheat
25
t 25 °C to Peak
Tim e
Classificatin Reflow Profiles
Sn-Pb Eutectic Assembly Pb-Free Assembly
Profile Feature
Large Body Small Body Large Body Small Body
Average ramp-up rate
3°C/second max. 3°C/second max.
(TL to TP)
Preheat
- Temperature Min (Tsmin) 100°C 150°C
- Temperature Mix (Tsmax) 150°C 200°C
- Time (min to max)(ts) 60-120 seconds 60-180 seconds
Tsmax to TL
3°C/second max
- Ramp-up Rate
Tsmax to TL
- Temperature(TL) 183°C 217°C
- Time (tL) 60-150 seconds 60-150 seconds
Peak Temperature(Tp) 225 +0/-5°C 240 +0/-5°C 245 +0/-5°C 250 +0/-5°C
Time within 5°C of actual Peak
10-30 seconds 10-30 seconds 10-30 seconds 20-40 seconds
Temperature(tp)
Ramp-down Rate 6°C/second max. 6°C/second max.
Time 25°C to Peak Temperature 6 minutes max. 8 minutes max.
Note: All temperatures refer to topside of the package. Measured on the body surface.
Copyright ANPEC Electronics Corp. 14 www.anpec.com.tw
Rev. A.5 - Mar., 2005
APW7060
Po P D
E
P1
F
W
Ao D1 Ko
T2
J
C
A B
T1
Application A B C J T1 T2 W P E
13.0 + 0.5 16.0 ± 0.3
330REF 100REF 2 ± 0.5 16.5REF 2.5 ± 025 8 1.75
- 0.2
SOP-14
F D D1 Po P1 Ao Ko t
(150mil)
7.5 φ0.50 + φ1.50 4.0 2.0 6.5 2.10 0.3±0.05
0.1 (MIN)
(mm)
Customer Service
Anpec Electronics Corp.
Head Office :
5F, No. 2 Li-Hsin Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
7F, No. 137, Lane 235, Pac Chiao Rd.,
Hsin Tien City, Taipei Hsien, Taiwan, R. O. C.
Tel : 886-2-89191368
Fax : 886-2-89191369