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Anupama KR & Meetha.V.


The LPC23xx series operates at 72MHz with up to 512KB of zero-wait state on-chip flash. More
significant is its ability to simultaneously run the application, USB FS, CAN, and Ethernet. This
is mainly achieved by the industry's only 2 AHB bus architecture in an ARM7-based MCU.
Members of the LPC 23xx Processor Family

Peripherals of LPC 23xx The ones indicated in green are covered as part of recorded lecture
the ones in red are self-study topics
ARM7TDMI-S processor, running at up to 72 MHz.
Up to 512 kB on-chip Flash Program Memory with In-System Programming (ISP) and
In-Application Programming (IAP) capabilities.
Up to 64 kB of SRAM on the ARM local bus for high performance CPU access.
16 kB Static RAM for Ethernet interface. Can also be used as general purpose SRAM.
8 kB Static RAM for general purpose or USB interface.
Dual AHB system
Advanced Vectored Interrupt Controller.
General Purpose DMA controller (GPDMA) on AHB that can be used with the SSP
serial interfaces, the I2S port, and the SD/MMC card port, as well as for memory-to-
memory transfers.
Serial Interfaces:
Ethernet MAC with associated DMA controller.
On LPC2364/66/68, LPC2378, LPC2387, LPC2388: USB 2.0 device controller
with on-chip PHY and associated DMA controller.
On LPC2388: USB Host/OTG controller.
Four UARTs with IrDA support, all with FIFO. These reside on the APB bus.
SPI controller, residing on the APB bus.
Two SSP controllers with FIFO and multi-protocol capabilities.
Three I2C interfaces reside on the APB bus. The second and third I2C interfaces
are expansion I2C interfaces with standard port pins rather than special open-
drain I2C pins.
I2S (Inter-IC Sound) interface for digital audio input or output, residing on the
APB bus. The I2S interface can be used with the GPDMA.
On LPC2364/66/68, LPC2378, LPC2387, LPC2388: Two CAN channels with
Acceptance Filter/FullCAN mode residing on the APB bus.

Other APB Peripherals:
On LPC2367/68, LPC2377/78, LPC2387, LPC2388: Secure Digital (SD) /
MultiMediaCard (MMC) memory card interface.
Up to 70 (100 pin packages) or 104 (144 pin packages) general purpose I/O
10 bit A/D converter with input multiplexing among 6 pins (100 pin packages)
or 8 pins (144 pin packages).
10 bit D/A converter.
Four general purpose timers with two capture inputs each and up to four
compare output pins each. Each timer block has an external count input.
One PWM/Timer block with support for three-phase motor control. The PWM
has two external count inputs.
Real-Time Clock (RTC) with separate power pin; clock source can be the RTC
oscillator or the APB clock.
Watchdog Timer. The watchdog timer can be clocked from the internal RC
oscillator, the RTC oscillator, or the APB clock.
Block Diagram of LPC 23xx

Important Tips for Self Study
Remember your aim is to understand the working of the microcontroller o that it can
be used for design
Understand the capability of every I/O module in LPC23xx and its limitation- for
e.g. if your looking at the timer try to understand the following
o Modes of Operation
o Where each mode can be used
o Mode supports autoreload or not ?
o Maximum frequency that can be generated
o Minimum Frequency that can be generated
o Frequency Resolution