LFSR Tutorial

Linear feedback shift-registers (LFSR) and
Pseudo-random binary sequences (PRBS)

D. W. Hawkins (dwh@ovro.caltech.edu)
California Institute of Technology,
Owens Valley Radio Observatory.
May 17, 2011
Contents
1 Introduction 3
2 Terminology 4
2.1 Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Polynomial notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 LFSR and PRBS properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.5 LFSR transition matrices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.6 Parallel generation of PRBS sequences . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3 Correlation 19
3.1 1-bit PRBS cyclic correlation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2 1-bit PRBS non-cyclic correlation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3 Multi-bit PRBS cyclic correlation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.4 Multi-bit PRBS non-cyclic correlation . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4 FPGA components 35
4.1 LFSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.2 Parallel output PRBS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.3 Digital noise source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5 Transceiver synchronization hardware tests 40
5.1 Stratix IV GX Development Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.2 Word alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.3 Multiple channel alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6 Digital noise source hardware tests 41
6.1 Stratix II DSP Development Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.2 1-bit PRBS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.3 Digital noise source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
LFSRs and PRBSs May 17, 2011
1 Introduction
Linear feedback shift-registers (LFSRs) are the logic circuits used to create pseudo-random binary
sequences (PRBSs). An LFSR circuit consists of a set of M registers and feedback taps that deter-
mine the sequence of states that the LFSR transitions through. The feedback taps are described by
a modulo-2 polynomial. A primitive polynomial generates a maximal length sequence (m-sequence),
where the LFSR transitions through 2
M
1 states before repeating (there is a single unused LFSR
state). The PRBS is the binary output of the LFSR. The binary sequence is described as pseudo-
random, as the sequence is deterministic, yet it has the correlation properties of a random sequence.
LFSRs and PRBSs are widely used in digital systems; in SONET the PRBS7 sequence is used
for data spreading (each data bit is modulated by a PRBS bit), while in code division multiple
access (CDMA) radio communications (and cellular phone systems), PRBS sequences are used to
generate spread-spectrum data (each data bit is modulated by a sequence of PRBS bits) and for
synchronization (base stations transmit known PRBS codes) [3, 10], PRBS sequences are used for
bit-error-rate (BER) testing of high-speed serial links [5, 9], and PRBS sequences are used as sources
of random noise, eg., as digital noise sources, and for unbiased binary rounding (p26 [11]).
This document shows how LFSRs can be used to implement both serial and parallel output
(multiple bits) PRBS sequences in Field Programmable Gate Arrays (FPGAs). The pseudo-random
noise properties of binary and parallel output PRBS sequences are investigated (and constraints un-
der which they can be applied determined). Example applications of PRBS sequences are provided;
high-speed transceiver testing and digital noise source generation (for use in digital signal processing
component testing).
Additional resources on LFSRs and PRBSs can be found on Wikipedia [12] under the topics linear
feedback shift register, pseudo-random binary sequence, and pseudo-random number generator. The
classic engineering text The Art of Electronics, by Horowitz and Hill discusses LFSRs/PRBSs in
Chapter 9 (p655 [4]). Xilinx discusses LFSRs and PRBSs in the documentation for their LFSR core
DS257 [13], and in application notes XAPP052 [1], XAPP210 [2], and XAPP211 [6]. The paper
Pseudo noise sequences for engineers, by Mutagi [7], and the communications engineering books by
Haykin [3] and Rouphael [10], also discuss applications.
3
2 Terminology
2.1 Topology
Figure 1 shows the two common LFSR topologies; Fibonacci and Galois. The two topologies are
related by a transpose operation. Figure 1 shows the transpose sequence; the Fibonacci form in
Figure 1(a), is converted to the Galois form by reversing the direction of signal ow, converting
summing nodes to junctions, and junctions to summing nodes, yielding the circuit in Figure 1(b),
which is then redrawn in Figure 1(c) to have the same shift direction as Figure 1(a). Section 2.5
shows how the state transitions of the Fibonacci and Galois forms can be described in terms of
transition matrices, and that the transition matrices are related by a matrix transpose operation.
The summing junctions shown in Figure 1 are modulo-2 adders, typically implemented using
XOR gates. The summing nodes can alternatively be implemented using XNOR gates (resulting
in an inversion of the sum). The invalid state for an XOR gate-based LFSR is the all-zeros state;
due to the fact that if the shift-register is loaded with zeros, the modulo-2 sums are also zero, so
the LFSR never changes state. An XNOR gate-based LFSR produces the complimentary (inverted)
sequence to that of an XOR gate-based design, with an invalid state of all-ones.
Figure 1 shows an interesting dierence between the Fibonacci and Galois topologies; the Fi-
bonacci form has a potentially long combinatorial path through the summing junctions (potentially
requiring a wide input XOR gate), whereas the Galois form has registers on the output of every
summing junction. This implies that the Galois topology would be preferred in an FPGA imple-
mentation. However, the primitive polynomials for LFSRs generally only have two, four, or six
feedback taps, which can be implemented by one (or a few) FPGA logic elements, so there is really
no implementation advantage to either topology. For a parallel output PRBS, the circuit becomes a
more complex system of multiple-input sums with registered outputs for either form, so again, there
is no advantage to either topology.
4
t
N-1
X
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Shift direction
Incrementing tap numbers
Shift direction
Shift direction
Shift direction
PRBS
output
PRBS
output
(a)
(b)
(c)
Figure 1: Linear feedback shift register (LFSR) topologies; (a) Fibonacci, (b) Fibonacci transposed
to give Galois, and (c) Galois redrawn to have the shift direction the same as in (a).
5
2.2 Polynomial notation
LFSR feedback taps are described by a modulo-2 polynomial. Maximal length sequences are gen-
erated by primitive polynomials. There are several polynomial notations; tap form, function form,
and binary form (which can also be represented in decimal or hexadecimal). Figure 1 shows the two
LFSR topologies, with polynomial feedback taps indicated by the X
n
terms. Figure 2 shows LFSR
circuits for the SONET 7-bit LFSR (PRBS7) sequence with the polynomial; tap form [7, 6], func-
tional form X
7
+X
6
+1, and binary form 1100_0001b = C1h = 193. Table 1 shows the contents of
the LFSR registers for a Fibonacci sequence with a generic initial seed for the rst 24 clocks, while
Table 2 shows the entire PRBS7 sequence for an initial all-ones seed. Primitive polynomials occur in
mirror pairs, eg., the PRBS7 polynomial in Figure 2 has the mirror polynomial [7, 1], X
7
+X
1
+1,
1000_0011b = 83h = 131, where the reason for the mirror terminology is most easily seen in the
binary form; the mirror polynomials are related by a bit-reversal. The mirror polynomial generates
the PRBS sequence in the reverse order.
There is a lot of ambiguity in LFSR and PRBS references with regard to the use of polynomials
and their corresponding hardware implementation. There are multiple sources of ambiguity, eg., in
Figure 1 there is the denition of the tap indexes relative to the shift direction, in Figure 2, there is
the denition of the shift-register indexes relative to the tap indexes. If either of these denitions is
changed (reversed), a dierent LFSR is realized. In addition, the fact that the LFSR polynomials
exist in mirrored pairs (reversing the sequence), compounds the potential for ambiguity. The tap
and register indexing convention used in this document (and associated code), as shown in Figure 1
and Figure 2 allows the same polynomial to be used to dene both Fibonacci and Galois forms, with
either form producing the same PRBS sequence.
The MATLAB Communications Toolbox primpoly function can be used to generate primitive
polynomials for LFSR widths of 2 to 16. There are generally multiple primitive polynomials for a
given bit width, eg., for a PRBS5 sequence
>> dec2bin(primpoly(5,all,nodisplay))
100101
101001
101111
110111
111011
111101
These polynomials can be sorted into their mirror pairs, i.e.,
100101 = X^5 + X^2 + 1
101001 = X^5 + X^3 + 1
101111 = X^5 + X^3 + X^2 + X^1 + 1
111101 = X^5 + X^4 + X^3 + X^2 + 1
110111 = X^5 + X^4 + X^2 + X^1 + 1
111011 = X^5 + X^4 + X^3 + X^1 + 1
Note how the primitive polynomials can be described with an even number of taps (an even number
of terms in X
n
, n ,= 0). Lists of primitive polynomials for LFSRs generally contain polynomials
with the minimum number of terms, eg., the taps for PRBS5 would be listed as [5, 2] or [5, 3]. Xilinx
Application Note XAPP052 [1], and the Xilinx LFSR core DS257 [13] list polynomial taps for LFSR
widths of 2 to 168. Horowitz and Hill (p657 [4]) list the polynomials with LFSR widths between 3
and 39 that require only a pair of feedback taps (the tap values match the Xilinx references).
6
X
6
X
7
X
0
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6
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0
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output
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Figure 2: PRBS7 LFSR topologies for generator polynomial X
7
+X
6
+1; (a) Fibonacci, (b) Fibonacci
transposed to give Galois, and (c) Galois redrawn to have the shift direction the same as in (a).
Code associated with this tutorial uses the register numbering convention shown in (a) and (c).
7
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1
1
0
0
1
1
1
6
7
1
1
7
0
0
0
1
1
0
0
0
C
0
4
9
0
0
1
0
1
0
1
1
5
1
8
1
1
0
1
0
1
1
0
5
6
0
1
1
3
0
1
1
0
0
1
1
3
3
1
1
8
0
0
0
0
1
1
0
0
6
0
5
0
1
0
0
1
0
1
0
4
A
0
8
2
1
1
0
1
0
1
1
6
B
1
1
1
4
0
0
1
1
0
0
1
1
9
1
1
9
1
0
0
0
0
1
1
4
3
1
5
1
1
1
0
0
1
0
1
6
5
1
8
3
0
1
1
0
1
0
1
3
5
1
1
1
5
1
0
0
1
1
0
0
4
C
0
2
0
0
1
0
0
0
0
1
2
1
1
5
2
1
1
1
0
0
1
0
7
2
0
8
4
1
0
1
1
0
1
0
5
A
0
1
1
6
0
1
0
0
1
1
0
2
6
0
2
1
1
0
1
0
0
0
0
5
0
0
5
3
1
1
1
1
0
0
1
7
9
1
8
5
1
1
0
1
1
0
1
6
D
1
1
1
7
1
0
1
0
0
1
1
5
3
1
2
2
0
1
0
1
0
0
0
2
8
0
5
4
1
1
1
1
1
0
0
7
C
0
8
6
1
1
1
0
1
1
0
7
6
0
1
1
8
0
1
0
1
0
0
1
2
9
1
2
3
0
0
1
0
1
0
0
1
4
0
5
5
0
1
1
1
1
1
0
3
E
0
8
7
1
1
1
1
0
1
1
7
B
1
1
1
9
1
0
1
0
1
0
0
5
4
0
2
4
0
0
0
1
0
1
0
0
A
0
5
6
1
0
1
1
1
1
1
5
F
1
8
8
0
1
1
1
1
0
1
3
D
1
1
2
0
0
1
0
1
0
1
0
2
A
0
2
5
1
0
0
0
1
0
1
4
5
1
5
7
0
1
0
1
1
1
1
2
F
1
8
9
1
0
1
1
1
1
0
5
E
0
1
2
1
1
0
1
0
1
0
1
5
5
1
2
6
1
1
0
0
0
1
0
6
2
0
5
8
0
0
1
0
1
1
1
1
7
1
9
0
1
1
0
1
1
1
1
6
F
1
1
2
2
1
1
0
1
0
1
0
6
A
0
2
7
1
1
1
0
0
0
1
7
1
1
5
9
0
0
0
1
0
1
1
0
B
1
9
1
0
1
1
0
1
1
1
3
7
1
1
2
3
1
1
1
0
1
0
1
7
5
1
2
8
1
1
1
1
0
0
0
7
8
0
6
0
0
0
0
0
1
0
1
0
5
1
9
2
0
0
1
1
0
1
1
1
B
1
1
2
4
1
1
1
1
0
1
0
7
A
0
2
9
0
1
1
1
1
0
0
3
C
0
6
1
1
0
0
0
0
1
0
4
2
0
9
3
0
0
0
1
1
0
1
0
D
1
1
2
5
1
1
1
1
1
0
1
7
D
1
3
0
0
0
1
1
1
1
0
1
E
0
6
2
1
1
0
0
0
0
1
6
1
1
9
4
1
0
0
0
1
1
0
4
6
0
1
2
6
1
1
1
1
1
1
0
7
E
0
3
1
1
0
0
1
1
1
1
4
F
1
6
3
1
1
1
0
0
0
0
7
0
0
9
5
1
1
0
0
0
1
1
6
3
1
9
2.3 LFSR and PRBS properties
The following summarizes some of the interesting properties of LFSRs and PRBSs;
Fibonacci and Galois topologies are transposes of each other; they both produce the same
PRBS sequence (with a relative time shift). For example, see the PRBS5 sequence generators
in Figures 3 and 4 and Tables 3 and 4.
Mirror polynomials produce time-reversed PRBS sequences. For example, see the PRBS5
sequence generators in Figures 3 and 4 and Tables 3 and 4.
Maximum length sequences always have an even number of feedback taps, i.e., the binary
polynomial has an odd number of bits. Many large LFSRs can be implemented with 2 or 4
feedback taps; so there is really no issue regarding the synthesis of wide-input XOR gates in
hardware for the Fibonacci topology.
The implementation of an LFSR depends on the denition of tap locations relative to the shift-
register direction. If a generator and receiver are implemented using dierent conventions, then
the PRBS sequences will be time-reversed relative to each other (due to the mirror polynomial
relationship).
The modulo-2 sum of two time-shifted versions of the same PRBS sequence is another time-
shifted version of the same PRBS sequence.
The modulo-2 summing nodes in an LFSR are typically implemented using XOR gates. The
nodes can alternatively be implemented using XNOR gates. An XNOR gate based LFSR
will generate the inverted sequence relative to its XOR equivalent (when started with a seed
equivalent to the compliment of the XOR seed). For example, if the LFSRs in Figures 3 and 4,
with the sequences given in Tables 3 and 4, were implemented using XNOR gates, and were
initialized with 00000b at reset, then the LFSR states and PRBS output sequence would be
complimented.
In a PRBS sequence of length 2
M
1, the number of 1s is one greater than the number of
0s (due to the invalid all-zeros state). This distribution represents an even chance for either
state, eg., simulation of a coin toss with an even chance for either heads or tails.
Horowitz and Hill (p657 [4]), Mutagi [7], Haykin (Ch. 9 [3]), and Rouphael (p71 [10]) contain
details on these properties and others.
2.4 Conventions
The following summarizes the conventions used in this document;
LFSR shift-registers use right-shifting, with the shift-register bits numbered from the MSB
(left) down to the LSB (right), with the PRBS output coming from the LSB. The registers in
LFSR shift-register of width M, are indexed in C and VHDL code from M1 down to 0, while
in MATLAB code, the indices are M down to 1 (due to MATLABs indexing convention).
The Fibonacci form has tap numbers that increment with the shift direction (see Figure 1(a)),
i.e., in opposition to the register numbering convention.
The Galois form has tap numbers that decrement with the shift direction (see Figure 1(c)),
i.e., in the same direction as the register numbering convention.
The same generator polynomial is used to describe an LFSR implementation regardless of its
topology (due to the denition of the tap ordering in Figure 1).
10
X
2
X
5
X
0
X
2
X
5
X
0
PRBS
output
PRBS
output
f
4
f
3
f
2
f
1
f
0
g
4
g
2
g
1
g
0
g
3
(a)
(b)
5
+ X
2
+ 1; (a) Fibonacci and
(b) Galois. The LFSR states and PRBS sequence are shown in Table 3. The PRBS sequences
produced by the Fibonacci and Galois form are equivalent, however, the sequences are time shifted,
eg., in Table 3, the Galois sequence starts at sample index 3 of the Fibonacci sequence. The mirror
polynomial in Figure 4 and Table 4 produces the time-reversed PRBS sequence.
X
3
X
5
X
0
X
3
X
5
X
0
PRBS
output
PRBS
output
f
4
f
3
f
2
f
1
f
0
g
4
g
2
g
1
g
0
g
3
(a)
(b)
5
+ X
3
+ 1; (a) Fibonacci and
(b) Galois. The LFSR states and PRBS sequence are shown in Table 4. The PRBS sequences
produced by the Fibonacci and Galois form are equivalent, however, the sequences are time shifted,
eg., in Table 4, the Galois sequence starts at sample index 2 of the Fibonacci sequence. The mirror
polynomial in Figure 3 and Table 3 produces the time-reversed PRBS sequence.
11
Table 3: PRBS5 sequence for taps [5,2], X
5
+X
2
+ 1, 100101b.
Sample
Fibonacci Galois
Index LFSR state PRBS LFSR state PRBS
binary hex output binary hex output
0 11111 1F 1 11111 1F 1
1 01111 0F 1 11101 1D 1
2 00111 07 1 11100 1C 0
3 10011 13 1 01110 0E 0
4 11001 19 1 00111 07 1
5 01100 0C 0 10001 11 1
6 10110 16 0 11010 1A 0
7 01011 0B 1 01101 0D 1
8 00101 05 1 10100 14 0
9 10010 12 0 01010 0A 0
10 01001 09 1 00101 05 1
11 00100 04 0 10000 10 0
12 00010 02 0 01000 08 0
13 00001 01 1 00100 04 0
14 10000 10 0 00010 02 0
15 01000 08 0 00001 01 1
16 10100 14 0 10010 12 0
17 01010 0A 0 01001 09 1
18 10101 15 1 10110 16 0
19 11010 1A 0 01011 0B 1
20 11101 1D 1 10111 17 1
21 01110 0E 0 11001 19 1
22 10111 17 1 11110 1E 0
23 11011 1B 1 01111 0F 1
24 01101 0D 1 10101 15 1
25 00110 06 0 11000 18 0
26 00011 03 1 01100 0C 0
27 10001 11 1 00110 06 0
28 11000 18 0 00011 03 1
29 11100 1C 0 10011 13 1
30 11110 1E 0 11011 1B 1
12
Table 4: PRBS5 sequence for taps [5,3], X
5
+X
3
+ 1, 101001b.
Sample
Fibonacci Galois
Index LFSR state PRBS LFSR state PRBS
binary hex output binary hex output
0 11111 1F 1 11111 1F 1
1 01111 0F 1 11011 1B 1
2 00111 07 1 11001 19 1
3 00011 03 1 11000 18 0
4 10001 11 1 01100 0C 0
5 11000 18 0 00110 06 0
6 01100 0C 0 00011 03 1
7 10110 16 0 10101 15 1
8 11011 1B 1 11110 1E 0
9 11101 1D 1 01111 0F 1
10 01110 0E 0 10011 13 1
11 10111 17 1 11101 1D 1
12 01011 0B 1 11010 1A 0
13 10101 15 1 01101 0D 1
14 01010 0A 0 10010 12 0
15 00101 05 1 01001 09 1
16 00010 02 0 10000 10 0
17 00001 01 1 01000 08 0
18 10000 10 0 00100 04 0
19 01000 08 0 00010 02 0
20 00100 04 0 00001 01 1
21 10010 12 0 10100 14 0
22 01001 09 1 01010 0A 0
23 10100 14 0 00101 05 1
24 11010 1A 0 10110 16 0
25 01101 0D 1 01011 0B 1
26 00110 06 0 10001 11 1
27 10011 13 1 11100 1C 0
28 11001 19 1 01110 0E 0
29 11100 1C 0 00111 07 1
30 11110 1E 0 10111 17 1
13
2.5 LFSR transition matrices
Figure 2 shows the LFSR topologies for a PRBS7 sequence generator with taps [7,6], generator
polynomial X
7
+ X
6
+ 1, and binary polynomial 1100_0001b. The operation of the LFSR can be
described in terms of a state machine where the register contents are the current state, and the
feedback connections determine the next state. The transition matrix for the Fibonacci form shown
in Figure 2(a) is
_
_
f
0
(n + 1)
f
1
(n + 1)
f
2
(n + 1)
f
3
(n + 1)
f
4
(n + 1)
f
5
(n + 1)
f
6
(n + 1)
_
_
=
_
_
0 1 0 0 0 0 0
0 0 1 0 0 0 0
0 0 0 1 0 0 0
0 0 0 0 1 0 0
0 0 0 0 0 1 0
0 0 0 0 0 0 1
1 1 0 0 0 0 0
_
_
_
_
f
0
(n)
f
1
(n)
f
2
(n)
f
3
(n)
f
4
(n)
f
5
(n)
f
6
(n)
_
_
(1)
where the matrix can be seen to contain an identity matrix (in blue) for the simple register-to-register
connections, and the sum feedback connection (in red). The transpose form shown in Figure 2(b)
is constructed by reversing the direction of signal ow, converting summing nodes into junctions,
and junctions into summing nodes. The transition matrix for the transposed Fibonacci form in
Figure 2(b) is
_
_
f
0
(n + 1)
f
1
(n + 1)
f
2
(n + 1)
f
3
(n + 1)
f
4
(n + 1)
f
5
(n + 1)
f
6
(n + 1)
_
_
=
_
_
0 0 0 0 0 0 1
1 0 0 0 0 0 1
0 1 0 0 0 0 0
0 0 1 0 0 0 0
0 0 0 1 0 0 0
0 0 0 0 1 0 0
0 0 0 0 0 1 0
_
_
_
_
f
0
(n)
f
1
(n)
f
2
(n)
f
3
(n)
f
4
(n)
f
5
(n)
f
6
(n)
_
_
(2)
where it can be seen that the transition matrix is the transpose of the matrix in (1). The Galois form
of the PRBS7 generator shown in Figure 2(c), is the transpose form of the Fibonacci, redrawn so
that the shift-register is right-shifting, and the registers are renumbered so that they are in the same
order as the Fibonacci form in Figure 2(a). The transition matrix for the Galois form in Figure 2(c)
is
_
_
g
0
(n + 1)
g
1
(n + 1)
g
2
(n + 1)
g
3
(n + 1)
g
4
(n + 1)
g
5
(n + 1)
g
6
(n + 1)
_
_
=
_
_
0 1 0 0 0 0 0
0 0 1 0 0 0 0
0 0 0 1 0 0 0
0 0 0 0 1 0 0
0 0 0 0 0 1 0
1 0 0 0 0 0 1
1 0 0 0 0 0 0
_
_
_
_
g
0
(n)
g
1
(n)
g
2
(n)
g
3
(n)
g
4
(n)
g
5
(n)
g
6
(n)
_
_
(3)
where the renumbering of the registers obscures the transpose relationship between the two forms.
The renumbering of the registers between Figure 2(a) and (c) was performed so that the code
associated with this tutorial could implement both Fibonacci and Galois topologies using right-
shifting registers, with the PRBS output from the LFSR being the LSB (bit 0). This convention
corresponds to the use of the right-shift operator on integer data types in C code, and allows
the display of the state register for either topology using a hexadecimal value that corresponds
directly to the registers shown in the gure, rather than having to perform a mental bit-reversal for
Fibonacci versus Galois LFSR state values. The hexadecimal values generated using C code and
MATLAB code can be compared directly to hexadecimal state values in Modelsim simulations of
VHDL implementations of LFSRs. The LFSR register numbering convention also corresponds to
the sequence that the PRBS bits are output, i.e., at serial time index 0, the PRBS output bit is the
LFSR register 0 content, at time index 1, the PRBS output bit is the content of LFSR register 1,
14
and so on. The correspondence between the PRBS output bit indexing, and the LFSR indexing can
be seen in Table 1, where the rst 7 PRBS output bits correspond to the initial 7-bit LFSR register
contents. This feature is exploited in serial-link bit-error-rate testing, by using the received PRBS
bits to initialize the receiver comparison PRBS generator; if there are no bit errors, any sequence of
7-bits received from the transmitter can be used to initialize the receiver LFSR, and from that point
on, both transmit and receive PRBS sequences should be identical. The LFSR and PRBS output
bit numbering convention also helps in understanding the parallel generation of PRBS sequences
discussed next.
15
2.6 Parallel generation of PRBS sequences
The LFSR circuits shown in Figure 1 generate a 1-bit PRBS output per clock period, eg., the
PRBS7 sequence shown in Table 2. In applications such as high-speed serial link testing and digital
noise generation, multiple PRBS bits are required per clock period. The papers by Mutagi [7] and
OReilly [8] discuss the series-parallel generation of m-sequences, however, those references only
discuss the case where the parallel output width is smaller than the LFSR width. This section
presents a generalized approach, where the number of output PRBS bits is independent of the
LFSR width.
Table 5 shows an example of what is desired from an 8-bit parallel output PRBS generator for
the 1-bit PRBS7 sequence shown in Table 2. The 127-bit PRBS7 sequence can be packed into 8-bit
values to create 15 8-bits plus 7-bits, or equivalently 16 8-bits minus 1-bit. Since the last 8-bit
value is short 1-bit, the 127-bit sequence can be repeated, and a dierent set of 8-bit values will be
produced (shifted by 1-bit relative to the rst sequence). The 127-bit sequence can be reused 8 times
to produce 127 8-bit values. Table 5 shows the 127-bit PRBS7 sequence repeated 8 times, and
packed into 8-bit values from LSB-to-MSB. The initial 8-bits of each repeated sequence are marked
in red; you can see how the 8-bit value shifts 1-bit at the boundary of each 127-bit repetition until
after the 127th 8-bit value, the sequence repeats again.
To determine the logic necessary to implement a parallel output PRBS, it is necessary to look
at the state transitions and output from an LFSR with a 1-bit PRBS output. Table 1 shows the
shift-register contents based on an arbitrary initial LFSR seed value. The sequence of PRBS output
samples from the LFSR LSB, i.e., p(n) = f
0
(n), where f
0
is the last column in the table, can be
written in matrix form as;
_
_
p
0
(n)
p
1
(n)
p
2
(n)
p
3
(n)
p
4
(n)
p
5
(n)
p
6
(n)
p
7
(n)
p
0
(n + 1)
p
1
(n + 1)
p
2
(n + 1)
p
3
(n + 1)
p
4
(n + 1)
p
5
(n + 1)
p
6
(n + 1)
p
7
(n + 1)
p
0
(n + 2)
p
1
(n + 2)
p
2
(n + 2)
p
3
(n + 2)
p
4
(n + 2)
p
5
(n + 2)
p
6
(n + 2)
p
7
(n + 2)
_
_
=
_
_
p(n)
p(n + 1)
p(n + 2)
p(n + 3)
p(n + 4)
p(n + 5)
p(n + 6)
p(n + 7)
p(n + 8)
p(n + 9)
p(n + 10)
p(n + 11)
p(n + 12)
p(n + 13)
p(n + 14)
p(n + 15)
p(n + 16)
p(n + 17)
p(n + 18)
p(n + 19)
p(n + 20)
p(n + 21)
p(n + 22)
p(n + 23)
_
_
=
_
_
1 0 0 0 0 0 0
0 1 0 0 0 0 0
0 0 1 0 0 0 0
0 0 0 1 0 0 0
0 0 0 0 1 0 0
0 0 0 0 0 1 0
0 0 0 0 0 0 1
1 1 0 0 0 0 0
0 1 1 0 0 0 0
0 0 1 1 0 0 0
0 0 0 1 1 0 0
0 0 0 0 1 1 0
0 0 0 0 0 1 1
1 1 0 0 0 0 1
1 0 1 0 0 0 0
0 1 0 1 0 0 0
0 0 1 0 1 0 0
0 0 0 1 0 1 0
0 0 0 0 1 0 1
1 1 0 0 0 1 0
0 1 1 0 0 0 1
1 1 1 1 0 0 0
0 1 1 1 1 0 0
0 0 1 1 1 1 0
_
_
_
_
f
0
(n)
f
1
(n)
f
2
(n)
f
3
(n)
f
4
(n)
f
5
(n)
f
6
(n)
_
_
(4)
where the serial output p(n) has been grouped into blocks of 8-bits, p
m
(n), for m = 0, . . . , 7. The
p
m
(n) samples are the parallel output samples for an 8-bit parallel output PRBS7 generator. The
16
PRBS output transition matrix consists of the identity matrix in the rst 7 7 locations, indicating
that the rst 7 PRBS output samples are given by the initial contents of the LFSR registers
1
. The
row following the identity matrix is the rst sample generated by LFSR XOR feedback. That XOR
sum was registered into LFSR register f
0
six clocks earlier (see sample index 1 in Table 1), and by
sample index 7, the XOR sum has propagated to the LFSR output register. Subsequent samples are
generated in the same manner. The transition matrix can be extended for the length of the PRBS
sequence, and then the matrix repeats.
Hardware generation of parallel output PRBS sequences requires an algorithm based on the
LFSR width and polynomial. This algorithm must automate the construction of the transition
matrix. The transition matrix can be calculated via (at least) two methods; matrix multiplication
and matrix row sums. In the matrix multiplication method, the transition matrix T is constructed
from rows 1 to 8 of the transition matrix, i.e.,
T =
_
_
0 1 0 0 0 0 0
0 0 1 0 0 0 0
0 0 0 1 0 0 0
0 0 0 0 1 0 0
0 0 0 0 0 1 0
0 0 0 0 0 0 1
1 1 0 0 0 0 0
_
_
(5)
This transition matrix denes the output samples p(n+1) to p(n+8). The transition matrix raised
to the power of m, i.e., T
m
, (using modulo-2 arithmetic) denes the connections for p(n + m) to
p(n +m+ 7), eg.,
T
8
=
_
_
0 1 1 0 0 0 0
0 0 1 1 0 0 0
0 0 0 1 1 0 0
0 0 0 0 1 1 0
0 0 0 0 0 1 1
1 1 0 0 0 0 1
1 0 1 0 0 0 0
_
_
(6)
which matches the 7 7 entries starting at p(n + 8) in the output transition matrix in (4). The
complete transition matrix can be constructed in blocks of 7 rows using the matrix multiplication
technique. However, there is a simpler technique; matrix row sums.
The transition matrix rows following the identity matrix rows in (4) can be formed as the modulo-
2 sum of previous rows. The rows that need to be summed are given by the bits set in the binary
generator polynomial. For example, the PRBS7 binary generator polynomial is 11000001b, where
bits 0, 6, and 7 are set. The calculation for the output transition row for p(n +m) for m > 6 is
p(n +m) = p(n +m7) p(n +m6) (7)
where the new row is calculated as the modulo-2 sum of the rows 6 and 7 samples earlier. Bit 0 does
not enter into the sum; think of it as the current row or as the initialization of the new row with
zeros. This summing of two previous rows can be seen in the PRBS output column (f
0
) in Table 1.
The generation of the transition matrix by summing previous rows can be encoded in a hardware
description language much simpler than matrix multiplication. Section 4 discusses how the matrix
row summing technique is used to create a parallel output PRBS generator component that can be
congured for arbitrary LFSR width and PRBS output width.
1
The LFSR register numbering scheme was selected so that the output sample and register indexes would match.
17
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18
3 Correlation
This section investigates the correlation properties of 1-bit PRBS sequences, and parallel output
PRBS sequences. The analsys shows how PRBS sequences can be used to generate white noise (a
random noise signal with uniform power spectral density).
The auto-correlation of an N-sample sequence x[n] is
r
xx
[k] =
N1
n=0
x[n]x[n k] (8)
where in hardware, the delays x[nk] can be implemented using registers, i.e., a delay line containing
earlier samples, hence the minus sign in front of k. The auto-correlation response is symmetric about
the zeroth lag, so in a hardware implementation only the zeroth and positive samples of the auto-
correlation need to be calculated. If the auto-correlation response is calculated using the discrete
Fourier transform, then as discussed next, the sequence length N depends on whether cyclic or
non-cyclic correlation is desired, and once the calculation is complete, the range of lags k can be
reduced to the samples of interest.
There are two main correlation properties of interest when analyzing PRBS sequences; cyclic
(periodic) correlation and non-cyclic (non-periodic) correlation. The cyclic correlation of the PRBS
sequence from an LFSR of width M is performed on N-samples, where N is a multiple of the
sequence length, i.e., N = R(2
M
1), where R is the number of repetitions of the sequence. The
cyclic auto-correlation of a PRBS sequence can be implemented using the discrete Fourier transform
via the following steps; given the PRBS samples x[n], for n = 0, 1, . . . , N 1, calculate the discrete
Fourier transform (via the FFT) of the sequence, i.e.,
X[m] =
N1
n=0
x[n] exp
_
j2mn
N
_
for m = 0, 1, . . . , N 1 (9)
then calculate the power-spectrum via
R
xx
[m] = [X[m][
2
(10)
The auto-correlation is the inverse discrete Fourier transform of the power-spectrum, i.e.,
r
xx
[k] =
1
N
N1
k=0
R
xx
[m] exp
_
j2km
N
_
(11)
where three explicit variables have been used; n for the sample index, m for the frequency channel
index, and k for the lag index.
The calculation of the power-spectrum via multiplication in the frequency domain results in
a cyclic convolution of the N samples in the time-domain. The samples in the auto-correlation
response can be displayed versus the lag indices k = 0, 1, . . . , N 1, or the response can be FFT
shifted into positive and negative lags, where for N odd k = (N1)/2, . . . , 1, 0, 1, . . . , (N1)/2,
and for N even k = N/2, . . . , 1, 0, 1, . . . , N/2 1 (the correlation response is cyclic, so these two
choices for k simply represent dierent starting points in the cyclic response).
The non-cyclic correlation of a PRBS sequence is typically performed on N samples taken from a
much larger sequence length, i.e., N (2
M
1). The discrete correlation of an N-sample sequence
with another N-sample sequence has a correlation response with (2N 1)-samples. The calculation
of this discrete correlation using the FFT requires that each N-sample sequence be padded with
zeros to a total length of at least (2N 1) (the next power-of-2 length is typically used). The non-
cyclic auto-correlation of the PRBS sequence is calculated via calculation of the power-spectrum as
19
Table 6: 1-bit PRBS cyclic auto-correlation.
Lag Sample sequence weights Correlation
k x[n k], n = 0, . . . , 7

x[n]x[n k]
0 1 1 1 -1 -1 1 -1 7
1 1 1 -1 -1 1 -1 1 -1
2 1 -1 -1 1 -1 1 1 -1
3 -1 -1 1 -1 1 1 1 -1
4 -1 1 -1 1 1 1 -1 -1
5 1 -1 1 1 1 -1 -1 -1
6 1 -1 1 1 1 -1 -1 -1
used for the cyclic correlation, however, the addition of the zero padding avoids cyclic aliasing of
the lag response. The zero padding does however result in a triangular weighting in the number
of samples that contribute to each correlation sum, eg., the lag k = 0 response is the sum of the
product of the two N-sample sequences, with N samples contributing to the sum, whereas, the lag
k = 1 response in the sum of the product of the two N-sample sequences shifted left or right by 1
sample, causing only (N 1)-samples in the two sequences to overlap, resulting in (N 1)-samples
contributing to the total sum (with the edge samples multiplied by zeros in the zero padding). The
number of overlapping samples in the N-sample sequences reduces linearly with the lag oset. The
reduction in samples in the non-cyclic correlation response results in lag dependent statistics.
3.1 1-bit PRBS cyclic correlation
The output from an LFSR is referred to as a pseudo-random binary sequence, where the term
pseudo-random refers to the fact that although the sequence has the characteristics of a random
sequence, it is in fact of nite length and fully deterministic.
A white noise signal is a signal with a uniform power-spectrum response, and a delta-function
auto-correlation response. A 1-bit PRBS has these features, however, the features are subject to how
the responses are calculated; the number of samples in the sequence being analyzed, and whether
cyclic or non-cyclic correlation is used.
The cyclic auto-correlation response of a 1-bit PRBS sequence x[n], of length (2
M
1), is a cyclic
delta-function, i.e.,
r
xx
[k] =
_
2
M
1 for k = 0 and k modulo (2
M
1) = 0
1 for k otherwise
(12)
where the correlation is not of the binary PRBS codes, but of the PRBS binary weights, where the
binary codes 0 and 1 are mapped to weights of -1 and +1 respectively. The mapping from binary
code to weight can also use the polar convention, where a PRBS output binary code b, maps to the
weight exp(jb) = (1)
b
, i.e., 0 maps to +1, and 1 maps to -1.
Table 6 shows an example of a 3-bit Fibonacci LFSR with polynomial X
3
+ X
2
+ 1 (binary
polynomial 1101b = 13) and an initial seed of 111b. The LFSR produces the 7-bit repeating PRBS
output binary sequence 1, 1, 1, 0, 0, 1, 0, which maps to the binary weights shown in the table.
Table 6 shows the terms used to calculate the auto-correlation sums for lags k = 0 through 6, with
the auto-correlation response repeating for k modulo 7.
20
The auto-correlation response in (12) has a delta-function response like a white noise source,
however, there is no statistical variation in the lag response. The cyclic auto-correlation of a PRBS
sequence has a main correlation peak of (2
M
1), and the lags away from the peak are all -1. The
lags away from the peak are all -1 due to the fact that a (2
M
1) length PRBS sequence has a total
of 2
(M1)
1s and 2
(M1)
1 0s, i.e., there is one less zero. For all but the zeroth lag, the
cyclic correlation results in (2
M
2) products with an even number of +1 and -1 terms which cancel
in the correlation sum, however, there is always one remaining product equal to -1, resulting in a
nal correlation sum of -1.
The power-spectrum of the PRBS sequence is the discrete Fourier transform of the auto-correlation
response, i.e.,
R
xx
[m] =
_
1 for m = 0 and m modulo (2
M
1) = 0
2
M
for m otherwise
(13)
where the Fourier transform was calculated using the fact that the lag response is even-symmetric,
so the power-spectrum will be real-valued, i.e.,
R
xx
[m] = r
xx
[0] +
N1
k=0
r
xx
[k] cos
_
2km
N
_
= (2
M
1)
N1
k=0
cos
_
2km
N
_
(14)
and the cosine sums
N1
k=0
cos
_
2km
N
_
=
_
N 1 for m = 0
1 for m = 1, . . . , N 1
(15)
and the cyclic Fourier transform length N = (2
M
1).
Figure 5 shows the cyclic correlation response for the 5-bit Fibonacci LFSR with polynomial
X
5
+X
3
+1 (binary polynomial 101001b), i.e., the PRBS sequence shown in Table 4 for the LFSR
in Figure 4. Figure 5 also shows the cyclic correlation response for the PRBS sequence repeated
three times; time-domain repetition of the sequence causes frequency-domain sampling.
Repetition of the PRBS sequence in the time-domain is equivalent to a convolution of the 31-
sample PRBS sequence with a series of unity-height impulses (delta-functions) spaced by 31 samples.
Convolution in the time-domain is equivalent to multiplication in the frequency domain. The Fourier
transform of the series of time-domain impulses is a series of frequency-domain impulses, with a
frequency channel spacing equivalent to the number of repetitions. The discrete Fourier transform
pair for the sampling function (the general name of the sequence of impulses) is
h[n] =
R1
r=0
(n rP) H[k] = R
M1
m=0
(k mR) (16)
where P = (2
M
1) is the PRBS sequence length, R is the number of repetitions, the discrete
Fourier transform length is N = RP, and n, k = 0, . . . , N 1.
The three repetitions of the 31-sample PRBS sequence shown in Figure 5(d), results in the
three peaked auto-correlation response in Figure 5(e), and the sampled power-spectrum response
in Figure 5(f). The three repetitions of the PRBS sequence in the time-domain results in a power-
spectrum that is sampled every three frequency samples. The power-spectrum in Figure 5(f) was
normalized by R
2
to scale the peak magnitude back to 2
M
, while the lag response in Figure 5(e)
was normalized by R to scale the correlation peaks back to (2
M
1). The scaling is required due to
the increase in the Fourier transform length by the factor R.
21
Figure 6 shows the eect of oversampling the PRBS response. In Figure 6(a), each sample in
the 31-sample PRBS sequence is duplicated four times (as consecutive samples). The repetition
of samples is analogous to the convolution of the original samples with a rect-function at four
times the original sampling rate. The time-domain oversampling and convolution cause frequency
domain expansion and multiplication of the frequency response with a sinc-function, resulting in
the response in Figure 6(c). Figure 6(d), (e), and (f) show the results of duplication of the samples,
and repetition of the duplicated sequence, i.e., the sinc-function frequency-domain response due
to duplication in Figure 6(c), becomes a sampled sinc-function response in Figure 6(f). The lag
responses in Figures 6(b) and (e) were normalized by D and RD respectively, while the power-
spectra in Figures 6(c) and (f) were normalized by D
2
and (RD)
2
respectively.
These repetition and duplication eects are not simply mathematical curiosities, but are observed
in practice, when sampling PRBS sequences generated by digital-to-analog converters (DACs) using
analog-to-digital converters (ADCs) and spectrum analyzers, as shown in Section 6.
3.2 1-bit PRBS non-cyclic correlation
Figure 7 shows the non-cyclic auto-correlation lag responses for the PRBS sequences obtained from
LFSRs of widths M = 5-bits to 10-bits. The PRBS sequences were correlated using the FFT. The
FFT length was the next power-of-two above the correlated sequence length; for a PRBS sequence
length of P = 2
M
1, the correlated sequence length is (2P 1) = 2
(M+1)
3, so the FFT length
is the next power-of-2 above this, i.e., N = 2
(M+1)
. Figure 7 shows all 2
(M+1)
samples of the
correlation response. In Figure 7, the variation in the lag response for lags near the peak (the zeroth
lag) is small, then the lag variation increases (the lag response bulges), and then decreases again at
the extreme lags. This response is due to the number of samples that contribute to the correlation
sums. The lags near the zeroth lag are calculated from sums that include almost all of the samples
in the PRBS sequence and hence the response of those lags is close to that of the cyclic correlation
response. The lags further from the main peak have less samples contributing to their sums, so their
amplitudes are decreased due to the triangular weighting discussed at the beginning of this section.
A PRBS sequence can be used as a uniform noise source if the number of samples correlated is
much smaller than the sequence length. The correlation of fewer samples eliminates the reduction in
variance of the lags near the zeroth lags seen in Figure 7, as those samples then become calculated
from a partial PRBS sequence.
The expected correlation statistics for a 1-bit uniform noise source are now determined. A PRBS
sequence with binary codes n = 0, 1, code weights w[n] = 1, +1, and the probability of each
code occurring P[n] = 0.5, 0.5, a sample x drawn from this distribution has an expected value of
x
= x) =
n
w[n]P[n] = 0 (17)
and variance of
2
x
= x
2
) x)
2
=
n
w
2
[n]P[n] = 1 (18)
i.e., the variable x is zero mean, with a variance of 1. The zeroth lag correlation statistics, are the
statistics of the power in the sequence x, dening the variable r = x
2
, the power has an expected
value of
r
= r) = x
2
) =
n
w
2
[n]P[n] = 1 (19)
and variance of
2
r
= r
2
) r)
2
= x
4
) x
2
)
2
=
n
w
4
[n]P[n] 1 = 0 (20)
22
0 5 10 15 20 25 30
1.5
1
0.5
0
0.5
1
1.5
Sample
W
e
i
g
h
t
15 10 5 0 5 10 15
5
0
5
10
15
20
25
30
35
Lag
C
o
r
r
e
l
a
t
i
o
n
15 10 5 0 5 10 15
5
0
5
10
15
20
25
30
35
Frequency channel
M
a
g
n
i
t
u
d
e
0 20 40 60 80
1.5
1
0.5
0
0.5
1
1.5
Sample
W
e
i
g
h
t
40 30 20 10 0 10 20 30 40
5
0
5
10
15
20
25
30
35
Lag
C
o
r
r
e
l
a
t
i
o
n
40 30 20 10 0 10 20 30 40
5
0
5
10
15
20
25
30
35
Frequency channel
M
a
g
n
i
t
u
d
e
(a)
(b)
(c)
(d)
(e)
(f)
Figure 5: PRBS5 cyclic correlation response for; a single instance of the 31-sample sequence (a)
samples, (b) auto-correlation, and (c) power-spectrum, three repeats of the sequence (d) samples, (e)
auto-correlation, and (f) power-spectrum. Time-domain repetition of the sequence causes frequency-
domain sampling.
23
0 20 40 60 80 100 120
1.5
1
0.5
0
0.5
1
1.5
Sample
W
e
i
g
h
t
60 40 20 0 20 40 60
5
0
5
10
15
20
25
30
35
Lag
C
o
r
r
e
l
a
t
i
o
n
60 40 20 0 20 40 60
5
0
5
10
15
20
25
30
35
Frequency channel
M
a
g
n
i
t
u
d
e
0 50 100 150 200 250 300 350
1.5
1
0.5
0
0.5
1
1.5
Sample
W
e
i
g
h
t
150 100 50 0 50 100 150
5
0
5
10
15
20
25
30
35
Lag
C
o
r
r
e
l
a
t
i
o
n
150 100 50 0 50 100 150
5
0
5
10
15
20
25
30
35
Frequency channel
M
a
g
n
i
t
u
d
e
(a)
(b)
(c)
(d)
(e)
(f)
Figure 6: PRBS5 cyclic correlation response for; four duplicate samples of the 31-sample sequence (a)
samples, (b) auto-correlation, and (c) power-spectrum, three repeats of the four duplicate samples
sequence (d) samples, (e) auto-correlation, and (f) power-spectrum. Time-domain duplication of
each sample causes frequency-domain multiplication with a sinc-response.
24
i.e., the power x
2
has an expected value of 1, with no variance. This makes sense, given that the
sequence of samples x has weights of -1 and +1, so the sequence of power samples x
2
is only the
weight 1.
The lag correlation statistics for other than the zeroth lag, are the statistics of the cross-power
between two samples x and y drawn from the PRBS sequence. Ideally these two samples are
uncorrelated so the probability of getting any particular combination of the weights -1 or 1 is 0.25,
i.e., given the binary code n for sample x and m for sample y, P[m, n] = 0.25, for m = 0, 1 and
n = 0, 1. The cross-power variable, r = xy, has an expected value of
r
= r) = xy) =
n
w[m]w[n]P[m, n] = 0 (21)
and variance of
2
r
= r
2
) r)
2
= (xy)
2
) xy)
2
=
n
(w[m]w[n])
2
P[m, n] = 1 (22)
i.e., the cross-power xy has an expected value of 0, with a variance of 1. This makes sense, given
that you expect the uncorrelated signals to be randomly giving a product of -1 or +1.
The statistics of a PRBS sequence being used as uniform noise source can be tested by taking
blocks of N
t
samples from the sequence, performing correlation via the FFT, and then inverse
transforming to obtain a correlation estimate. Averaging N
a
estimates together causes the power
distribution statistics to approach that of a normally distributed variable. The correlation statistics
for the averages are
r
xx
[k] =
_
_
^
_
N
t
,
N
t
N
a
_
for k = 0
^
_
0,
N
t
N
a
_
1
[k[
N
t
__
for k = 1, . . . , N
t
/2
(23)
where the notation ^(,
2
), indicates a normally distributed random variable with mean and
variance
2
, and the term (1[k[/N
t
) is due to the triangular weighting of the (non-cyclic) correlation
sums. Normalizing the correlation averages by the number of samples in each estimate gives the
correlation coecient form
xx
[k] =
_
_
^
_
1,
1
N
t
N
a
_
for k = 0
^
_
0,
1
N
t
N
a
_
1
[k[
N
t
__
for k = 1, . . . , N
t
/2
(24)
Figure 8 shows correlation coecient response for a 31-bit LFSR based PRBS noise source for lags 0
to N
t
/2. The lag response matches expectations; with no variance of the zeroth lag, and a downward
ramp in the variance for the lags away from the zeroth lag. The lag variance was normalized by
1/(N
t
N
a
) to scale the values to near unity.
The LFSR width for a PRBS-based noise source is determined by the number of uncorrelated
samples required. For example, the correlations shown in Figure 8 required N
t
N
a
N
e
=
128 100 2000 = 25600000 samples, so an LFSR width of at least ceil(log 2(25600000)) = 25-
bits is required. The plots were generated using the PRBS output from a 31-bit LFSR, as the
PRBS sequence can be generated and written to a binary le once, and that le reused for multiple
simulations.
25
30 20 10 0 10 20 30
0.2
0
0.2
0.4
0.6
0.8
1
Lag
C
o
r
r
e
l
a
t
i
o
n

c
o
e
f
f
i
c
i
e
n
t
60 40 20 0 20 40 60
0.2
0
0.2
0.4
0.6
0.8
1
Lag
C
o
r
r
e
l
a
t
i
o
n

c
o
e
f
f
i
c
i
e
n
t
100 50 0 50 100
0.2
0
0.2
0.4
0.6
0.8
1
Lag
C
o
r
r
e
l
a
t
i
o
n

c
o
e
f
f
i
c
i
e
n
t
200 100 0 100 200
0.2
0
0.2
0.4
0.6
0.8
1
Lag
C
o
r
r
e
l
a
t
i
o
n

c
o
e
f
f
i
c
i
e
n
t
500 0 500
0.2
0
0.2
0.4
0.6
0.8
1
Lag
C
o
r
r
e
l
a
t
i
o
n

c
o
e
f
f
i
c
i
e
n
t
1000 500 0 500 1000
0.2
0
0.2
0.4
0.6
0.8
1
Lag
C
o
r
r
e
l
a
t
i
o
n

c
o
e
f
f
i
c
i
e
n
t
(a)
(b)
(c)
(d)
(e)
(f)
Figure 7: PRBS5 non-cyclic correlation lags responses for LFSR widths of; (a) 5-bits, (b) 6-bits, (c)
7-bits, (d) 8-bits, (e) 9-bits, and (f) 10-bits.
26
0
20
40
60
20
40
60
80
100
0
0.2
0.4
0.6
0.8
1
Estimate
Lag
C
o
r
r
e
l
a
t
i
o
n
0 10 20 30 40 50 60
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Lag
N
o
r
m
a
l
i
z
e
d

v
a
r
i
a
n
c
e
(a)
(b)
Figure 8: PRBS31 1-bit uniform distribution auto-correlation statistics for a N
t
= 128 samples
per correlation, N
a
= 100 averages per estimate, and N
e
= 2000 estimates; (a) auto-correlation
lag response for the rst 100 estimates and (b) normalized lag variance estimated from the 2000
auto-correlation estimates.
27
20 15 10 5 0 5 10 15 20
0
5
10
15
20
25
30
35
Signed integer value
O
c
c
u
r
r
e
n
c
e
20 15 10 5 0 5 10 15 20
0
50
100
150
O
c
c
u
r
r
e
n
c
e
(a) (b)
Figure 9: PRBS 5-bit uniform distribution histogram for; (a) 1023 5-bit samples from the 5-bit
LFSR [10,3] and (b) 4096 5-bit samples from the 15-bit LFSR [15,1].
3.3 Multi-bit PRBS cyclic correlation
The sequence of bits in a PRBS sequence can be packed into parallel words (or generated directly
as parallel words), and interpreted as signed integer values. Figure 9 shows the histogram for 5-bit
signed integer samples (-16 to 15) constructed from the PRBS bits from the 10-bit LFSR with taps
[10,3] and from the 15-bit LFSR with taps [15,1]. For the histogram in Figure 9(a), the 1023 sample
PRBS sequence was repeated 5 times and used to generate 1023 5-bits samples. A 5-bit signed
integer has 32 possible codes, so each column in the histogram is expected to have 32 occurrences
(with one column having one less sample, since there were only 1023 samples). For the histogram in
Figure 9(b), the 4096 5-bit samples were generated from 20480 samples from the PRBS sequence
of length 32767, i.e., not all PRBS bits were used and the sequence was not repeated. The expected
level of the histogram columns is 128.
If the samples in a PRBS sequence are repeated when constructing parallel data, then although
the parallel data values are unique, the values are correlated, due to the parallel values being related
by a parallel data bit-shift. For example, Table 5 shows the construction of 8-bit words from a
repeated PRBS7 sequence. The values of the rst and second 16 bytes in the table are unique,
however, the bits within the bytes are not (since the PRBS sequence bits are repeated); the 7
least-signicant-bits in each byte of the second 16 byte sequence are equivalent to the 7 most-
signicant-bits of the rst 16 byte sequence. This pattern continues with a 1-bit shift for every
repetition of the PRBS sequence. This pattern results in correlation between the parallel values (or
anti-correlation depending on the value of the sign bits).
Figures 10 and 11 show the cyclic correlation of 8-bit values constructed from the repetition of the
5-bit LFSR PRBS sequences used in the 1-bit cyclic correlation responses in Figures 5 and 6. The
sample sequences in Figures 10(a) and (c), and Figures 11(a) and (c) were normalized to fractional
integer format, i.e., 1.0 to 1.0. The negative spikes in the correlation responses in Figures 10(b) and
(e), and Figures 11(b) and (e) are due to the sample-to-sample correlation caused by repeating the
PRBS sequence. The correlation spikes cause ripple in the power-spectra, as seen in Figures 10(c)
and (f), Figures 10(c) and (f).
Although the correlation responses in Figures 10 and 11 are not useful for use as a white noise
source, they do have one redeeming feature; if you are trying to synchronize to a PRBS source, and
are receiving a parallel PRBS data words, the correlation of the parallel samples, rather than a 1-bit
correlation, does have a lag response with a main peak. The main peak is at least twice as high as
any other peaks, so a detection threshold could be used to detect only the main peak.
28
0 5 10 15 20 25 30
1.5
1
0.5
0
0.5
1
1.5
Sample
W
e
i
g
h
t
15 10 5 0 5 10 15
10
5
0
5
10
15
20
25
30
35
Lag
C
o
r
r
e
l
a
t
i
o
n
15 10 5 0 5 10 15
5
0
5
10
15
20
25
30
35
40
45
50
Frequency channel
M
a
g
n
i
t
u
d
e
0 20 40 60 80
1.5
1
0.5
0
0.5
1
1.5
Sample
W
e
i
g
h
t
40 30 20 10 0 10 20 30 40
10
5
0
5
10
15
20
25
30
35
Lag
C
o
r
r
e
l
a
t
i
o
n
40 30 20 10 0 10 20 30 40
5
0
5
10
15
20
25
30
35
40
45
50
Frequency channel
M
a
g
n
i
t
u
d
e
(a)
(b)
(c)
(d)
(e)
(f)
Figure 10: PRBS5 8-bit cyclic correlation response for; a single instance of the 8-bit 31-sample
sequence (a) samples, (b) auto-correlation, and (c) power-spectrum, three repeats of the sequence
(d) samples, (e) auto-correlation, and (f) power-spectrum. Time-domain repetition of the sequence
causes frequency-domain sampling.
29
0 20 40 60 80 100 120
1.5
1
0.5
0
0.5
1
1.5
Sample
W
e
i
g
h
t
60 40 20 0 20 40 60
10
5
0
5
10
15
20
25
30
35
Lag
C
o
r
r
e
l
a
t
i
o
n
60 40 20 0 20 40 60
5
0
5
10
15
20
25
30
35
40
45
50
Frequency channel
M
a
g
n
i
t
u
d
e
0 50 100 150 200 250 300 350
1.5
1
0.5
0
0.5
1
1.5
Sample
W
e
i
g
h
t
150 100 50 0 50 100 150
10
5
0
5
10
15
20
25
30
35
Lag
C
o
r
r
e
l
a
t
i
o
n
150 100 50 0 50 100 150
5
0
5
10
15
20
25
30
35
40
45
50
Frequency channel
M
a
g
n
i
t
u
d
e
(a)
(b)
(c)
(d)
(e)
(f)
Figure 11: PRBS5 8-bit cyclic correlation response for; four duplicate samples of the 8-bit 31-
sample sequence (a) samples, (b) auto-correlation, and (c) power-spectrum, three repeats of the four
duplicate samples sequence (d) samples, (e) auto-correlation, and (f) power-spectrum. Time-domain
duplication of each sample causes frequency-domain multiplication with a sinc-response.
30
3.4 Multi-bit PRBS non-cyclic correlation
The expected statistics for a B-bit uniform noise source can be determined using the uniform prob-
ability distribution function,
f(x) =
_
_
1
b
for [x[
b
2
0 for x otherwise
(25)
A sample x drawn from this distribution has an expected value of
x
= x) =
_ b
2
b
2
xf(x)dx =
1
b
_
x
2
2
_
b
2
b
2
= 0 (26)
and variance of
2
x
= x
2
) x)
2
=
_ b
2
b
2
x
2
f(x)dx =
1
b
_
x
3
3
_
b
2
b
2
=
b
2
12
(27)
A PRBS parallel output B-bit value normalized to fractional integer format has a uniform distribu-
tion over the range -1.0 to 1.0 (b = 2.0). A variable x drawn from this distribution has a zero mean,
and a variance of
2
x
= 1/3.
The zeroth lag correlation statistics, are the statistics of the power in the sequence x, dening
the variable r = x
2
, the power has an expected value of
r
= r) = x
2
) =
2
x
(28)
and variance of
2
r
= r
2
) r)
2
= x
4
) x
2
)
2
=
1
b
_
x
5
5
_
b
2
b
2
_
1
b
_
x
3
3
_
b
2
b
2
_2
=
4
5
4
x
(29)
The lag correlation statistics for other than the zeroth lag, are the statistics of the cross-power
between two samples x and y drawn from the uniform distribution. Ideally these two samples are
uncorrelated so the probability of getting any particular combination of the binary values has a zero
mean, and variance of
4
x
.
The statistics of a PRBS sequence being used as uniform noise source can be tested by construct-
ing blocks of N
t
B-bit samples from the sequence, performing correlation via the FFT, and then
inverse transforming to obtain a correlation estimate. Averaging N
a
estimates together causes the
power distribution statistics to approach that of a normally distributed variable. The correlation
statistics for the averages are
r
xx
[k] =
_
_
^
_
N
t
2
x
,
4
5
N
t
N
a
4
x
_
for k = 0
^
_
0,
N
t
N
a
_
1
[k[
N
t
_
4
x
_
for k = 1, . . . , N
t
/2
(30)
Normalizing the correlation averages by the number of samples in each estimate, and by the expected
variance
2
x
, gives the correlation coecient form
xx
[k] =
_
_
^
_
1,
4
5
1
N
t
N
a
_
for k = 0
^
_
0,
1
N
t
N
a
_
1
[k[
N
t
__
for k = 1, . . . , N
t
/2
(31)
31
Figure 12 shows correlation coecient response for a 31-bit LFSR based PRBS uniform noise source
for lags 0 to N
t
/2. The lag response matches expectations; with a zeroth lag variance of 0.8, and
a downward ramp in the variance for the lags away from the zeroth lag. The lag variance was
normalized by 1/(N
t
N
a
) to scale the values to near unity.
The probability distribution of the sum of a set of random variables is the convolution of the
individual probability distributions. Hence, the sum of two uniform distribution variables has a
triangular distribution, and the sum of four or more variables has a distribution with a bell-shaped
curve similar to that of a Gaussian distribution. The shape of the distributions can be determined
using the Fourier transform, i.e., the Fourier transform of the uniform distribution is a sinc-function,
the Fourier transform of the sum of two uniform distribution samples is a sinc
2
function, and the
Fourier transform of the sum of four uniform distribution samples is a sinc
4
function. A Gaussian
distributed noise source can be modeled using the sum of four or more uniform distribution samples.
The variance of the sum sample, is the sum of the variances of the individual samples, i.e., the
variance of N
s
sample sum is N
s
2
x
= N
s
/3. The sum of N
s
samples results in bit-growth of
log
2
(N
s
), eg., 1-bit for a sum of two samples, 2-bits for a sum of four samples. Normalizing the sums
by N
s
and requantizing the sum to B-bits
2
results summed samples having a variance of 1/(3N
s
).
The optimal input power-level for a Gaussian signal in fractional integer power format is a variance
of around 0.25, or a loading-factor of 10 log
10
(0.25) = 12dB. If four uniform samples are averaged,
the input loading factor of the signal is 10 log
10
(1/12) = 10.8dB, i.e., slightly higher than optimal,
and for eight samples averaged the input loading factor is -13.8dB. Figure 13 shows correlation
coecient response for a 31-bit LFSR based PRBS Gaussian noise source for lags 0 to N
t
/2. The
normalized zeroth lag variance for a true Gaussian signal is 2 (Chi-square power distribution), the
approximate Gaussian distribution has a zeroth lag variance of approximately 1.8 (a not quite
Chi-square power distribution). This minor dierence has no eect on the power spectra generated
using the Gaussian approximated noise source as the input test signal.
The LFSR width for a PRBS-based noise source is determined by the number of uncorrelated
samples required. For example, the 8-bit uniform distribution correlations shown in Figure 12
required B N
t
N
a
N
e
= 8 128 100 2000 = 204800000 samples, so an LFSR width of
at least 28-bits is required. The 8-bit Gaussian distribution shown in Figure 13 summed four 8-bit
PRBS parallel samples to produce each sample with approximate Gaussian statistics, so required
an LFSR width of at least 30-bits. The plots were generated using the PRBS output from a 31-bit
LFSR. An FPGA can implement parallel output PRBS sequences with very long repeat periods,
with few resources. For example, a 64-bit LFSR clocked at 250MHz generating 32-bit parallel PRBS
output data (so that four samples can be summed to model an 8-bit Gaussian noise source) has a
repeat period of 73 years.
2
The B-bit sum sample could also be generated as the Ns sample sum of (B log
2
(Ns))-bit samples. However,
the histograms of sums of B-bit samples looked better (more Gaussian).
32
0
20
40
60
20
40
60
80
100
0
0.2
0.4
0.6
0.8
1
Estimate
Lag
C
o
r
r
e
l
a
t
i
o
n
0 10 20 30 40 50 60
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Lag
N
o
r
m
a
l
i
z
e
d

v
a
r
i
a
n
c
e
(a)
(b)
Figure 12: PRBS31 8-bit uniform distribution auto-correlation statistics for a N
t
= 128 samples
per correlation, N
a
e
= 2000 estimates; (a) auto-correlation
lag response for the rst 100 estimates and (b) normalized lag variance estimated from the 2000
auto-correlation estimates.
33
0
20
40
60
20
40
60
80
100
0
0.2
0.4
0.6
0.8
1
Estimate
Lag
C
o
r
r
e
l
a
t
i
o
n
0 10 20 30 40 50 60
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Lag
N
o
r
m
a
l
i
z
e
d

v
a
r
i
a
n
c
e
(a)
(b)
Figure 13: PRBS31 8-bit Gaussian distribution approximation auto-correlation statistics for a N
t
=
128 samples per correlation, N
a
e
= 2000 estimates; (a) auto-
correlation lag response for the rst 100 estimates and (b) normalized lag variance estimated from
the 2000 auto-correlation estimates. The Gaussian distribution is approximated by summing four
PRBS 8-bit uniform distribution samples, and requantizing the sum to 8-bits.
34
Table 7: LFSR package, lfsr pkg.vhd, functions.
Function and Description
lfsr polynomial(w)
Returns the default primitive polynomial for an LFSR of width w. The polynomial is en-
coded using the VHDL data type std_logic_vector(w downto 0), i.e., the polynomial
is of width w+1.
lfsr binary string to polynomial(s)
Converts a string containing binary characters, 0 and 1, or underscore, _, to polynomial
format with a width equal to the number of binary characters in the string, eg., a PRBS7
polynomial can be generated using the string "1100_0001".
lfsr hex string to polynomial(s,w)
Converts a string containing hexadecimal characters, 0 through F, or underscore, _, to
polynomial format of width w (which is one larger than the LFSR width), eg., a PRBS7
polynomial can be generated using the string "C1" with a width of 8 bits.
lfsr tap string to polynomial(s,w)
Converts a string containing a comma separated list of decimal valued taps to polynomial
format of width w (one larger than the LFSR width), eg., a PRBS7 polynomial can be
generated using the tap notation "[7,6]", or "7,6" (the order of the taps in the list
does not matter) and a width of 8 bits.
4 FPGA components
The VHDL code associated with this tutorial contains three major components; an LFSR component,
a parallel output PRBS component, and a digital noise component. These components are used
in the hardware tests in Sections 5 and 6 to construct more complex designs. The LFSR package,
lfsr_pkg.vhd, provides convenience functions for dening LFSR polynomials. The package contains
the procedures shown in Table 7. The LFSR polynomials are encoded using the VHDL data type
std_logic_vector, so that arbitrary width LFSRs can be generated.
35
Table 8: LFSR component, lfsr.vhd, generics and ports.
Generic Description
WIDTH LFSR width. The number of LFSR states is 2**WIDTH-1.
POLYNOMIAL The LFSR generator polynomial. Default polynomials are provided by
lfsr_polynomial() in lfsr_pkg.vhd.
TOPOLOGY LFSR topology; FIBONACCI or GALOIS.
INVERT Generate an inverted LFSR state and PRBS output.
Port Description
rstN Reset (active low).
clk Clock.
load Load the LFSR seed value.
seed LFSR seed value.
enable Enable the LFSR.
data The LFSR state and PRBS output. The PRBS output is typically taken from
the LSB, i.e., data(0).
4.1 LFSR
The LFSR component, lfsr.vhd, implements the circuits shown in Figure 1. Table 8 shows the
component generics and ports. The LFSR testbench, lfsr_tb.vhd, compares the LFSR PRBS
output to a PRBS sequence stored in a binary le generated by MATLAB or C-code.
36
Table 9: Parallel output PRBS component, prbs.vhd, generics and ports.
Generic Description
LFSR WIDTH LFSR width. The number of LFSR states is 2**LFSR_WIDTH-1.
PRBS WIDTH Parallel PRBS output width, i.e., the number of PRBS bits to generate per
clock period.
Port Description
clk Clock.
lfsr q The LFSR state.
prbs q The parallel PRBS output.
4.2 Parallel output PRBS
The parallel output PRBS component, prbs.vhd, implements multiple PRBS bits per clock pe-
riod. Table 9 shows the component generics and ports. The PRBS testbench, prbs_tb.vhd, uses
the serial output LFSR component and a serial-to-parallel shift register to conrm that the par-
allel output PRBS sequence matches the LFSR binary sequence. The PRBS spreader testbench,
prbs_spreader_tb.vhd, shows how transmit and receive PRBS generators can be synchronized,
and then used to modulate and demodulate a data stream.
The parallel output PRBS VHDL component is implemented based on the transition matrix
discussed in Section 2.6. The VHDL uses functions to initialize a constant transition matrix based
on the LFSR polynomial and the parallel output width. The transition matrix column length is
twice the length of the PRBS output width, so that the transition matrix can be used to initialize
the parallel output registers (the LFSR reset seed and derived PRBS bits) on reset and when a
seed is loaded, and to calculate the next state when the component is enabled. The component
can implement PRBS widths from as small as 1-bit, i.e., an LFSR, to widths larger than the LFSR
width or the entire PRBS sequence length, eg., a PRBS7 polynomial can be used along with a
128-bit output width, resulting in the parallel output containing the entire 127-bit PRBS sequence
plus 1-bit every clock period.
37
Table 10: Digital noise component, noise.vhd, generics and ports.
Generic Description
LFSR WIDTH LFSR width. The number of LFSR states is 2**LFSR_WIDTH-1.
NOISE TYPE Noise type; UNIFORM or GAUSSIAN.
NOISE SUM Number of uniform noise samples to sum for GAUSSIAN noise.
NOISE WIDTH Output noise width.
Port Description
clk Clock.
q Output noise.
4.3 Digital noise source
The digital noise component, noise.vhd, uses the parallel output PRBS component to generate
uniform or Gaussian (like) noise samples. Table 10 shows the component generics and ports.
For uniform noise, the component uses a NOISE_WIDTH-bits parallel output PRBS to generate a
signed uniform noise sample of width NOISE_WIDTH-bits. For Gaussian noise, the component uses
a NOISE_SUM NOISE_WIDTH-bits parallel output PRBS, sums NOISE_SUM signed samples of width
NOISE_WIDTH-bits together using a pipelined adder tree, and then convergent rounds the sum to
generate a signed Gaussian (like) noise sample of width NOISE_WIDTH-bits. The digital noise source
testbench, noise_tb.vhd, can be used to write uniform and Gaussian noise samples to a text le
for analysis. Figure 14 shows the histogram and power spectra for a PRBS31-based digital noise
source (processed using the MATLAB script noise_tb.m). Section 3.4 has details on the correlation
properties of the digital noise source.
38
1 0.5 0 0.5 1
0
500
1000
1500
2000
2500
Fractional integer value
O
c
c
u
r
r
e
n
c
e
0 0.1 0.2 0.3 0.4 0.5
30
25
20
15
10
5
0
5
10
Normalized frequency
M
a
g
n
i
t
u
d
e

(
d
B
)
1 0.5 0 0.5 1
0
1000
2000
3000
4000
5000
6000
Fractional integer value
O
c
c
u
r
r
e
n
c
e
0 0.1 0.2 0.3 0.4 0.5
30
25
20
15
10
5
0
5
10
Normalized frequency
M
a
g
n
i
t
u
d
e

(
d
B
)
(a) (b)
(c) (d)
Figure 14: Digital noise source with 16-bit output (PRBS [31,28]). Uniform noise (a) sample
histogram and (b) power spectra, with a loading factor of 10 log
10
(1/3) = 4.8dB. Gaussian noise
(c) sample histogram and (d) power spectra, with a loading factor of 10 log
10
(1/12) = 10.8dB
(where the Gaussian was approximated as the sum of four uniform samples). The histograms were
calculated from 100 1024 samples and sorted into 50 bins. The PSD were calculated by averaging
100 1024-sample PSD estimates.
39
5 Transceiver synchronization hardware tests
PRBS sequences are used for bit-error-rate (BER) testing of high-speed serializer/deserializer
(SERDES) links. High-speed serial links are characterized by logic operating in two clock domains;
the low-speed parallel clock domain and the high-speed serial clock domain. PRBS bits need to be
generated in parallel in the low-speed clock domain. The parallel PRBS data is then sent to the
transmit serializer, where data is parallel-to-serial converted for high-speed transmission; the high-
speed serial data is the 1-bit PRBS. The high-speed serial data is captured by the receive deserializer,
where data is serial-to-parallel converted. The received parallel PRBS data is then tested for bit
errors, against the expected PRBS pattern. The receiver synchronizes the receive PRBS to the
transmit PRBS, by using the rst received parallel PRBS pattern as the receiver PRBS seed. On
subsequent low-speed clocks, if there are no bit errors over the serial link, the transmit and receive
PRBS patterns should match, i.e., the bit-wise XOR of the two patterns should be all zeros. The
BER of a serial link is implemented at the receiver by counting the number of bits set in the output
of the bit-wise XOR; if there are no errors, then no bits get set, and the BER count remains zero.
. To test FPGA SERDES links at dierent SERDES widths, it is necessary to generate multiple
PRBS bits per clock in the parallel clock domain. For example, a SERDES channel operating with
a 16-bit FPGA fabric interface (parallel clock domain) at 156.25MHz would send 16-bit data to the
transmit channel for transmission at 16156.25MHz = 2500Mbps, data would then be received and
deserialized to 16-bit data at 156.25MHz.
5.1 Stratix IV GX Development Kit
5.2 Word alignment
5.3 Multiple channel alignment
40
6 Digital noise source hardware tests
This section contains hardware test results from the digital noise source component discussed in
Section 4. The test results were obtained using the Altera Stratix II DSP development kit.
6.1 Stratix II DSP Development Kit
The Stratix II DSP Development kit features;
Stratix II EP2S60 device
3
.
Two Analog Devices AD9433 12-bit 125MHz ADCs.
Two Texas Instruments (Burr-Brown) DAC904 14-bit 165MHz DACs.
100MHz oscillator.
The board has jumper options for clocking the ADCs and DACs from the 100MHz oscillator,
or from FPGA PLL outputs. These tests used the oscillator option, i.e., the ADC clock select
6-pin headers J3 and J4 had jumpers installed across pins 3 and 4, and the DAC clock select
8-pin headers J18 and J19 had jumpers installed across pins 5 and 6.
The ADC9433 inputs are driven by a balun that has its inputs reversed (to aid in PCB routing).
This causes the ADC signal to be inverted relative to the DAC output. The analysis scripts
used in these tests invert the ADC data prior to writing data capture les.
The DAC904 data bus pin names (and schematic net names) D1 through D14 correspond to
binary bits 13 down to 0, i.e., the reverse of the pin names. The design VHDL code numbers the
bits in the DAC buses d(13 downto 0), and the pin assignments script assigns the appropriate
(reverse-order) pins.
The DAC output voltage range is not well-matched to the ADC input voltage range; the test
results show that the full-scale output from the DAC corresponds to about half the input range
of the ADC.
3
The board used for these tests contained an EP2S60F1020C4ES engineering sample.
41
6.2 1-bit PRBS
The analysis in Section 3 showed that a repeating PRBS sequence results in sampling of the fre-
quency domain, and that an oversampled PRBS sequence has a sinc-like frequency response, i.e., the
spectrum of a PRBS is an impulsive sinc-function. The spacing between the frequency domain sam-
pling impulses in the power spectrum calculated using an FFT is equal to the number of repetitions,
i.e., given a sequence length P, repeated R times, the FFT length is N = RP, and the impulses
are spaced every R frequency channels. In normalized frequency units, this spacing is equivalent to
R/(RP) = 1/P, and in Hz the spacing is f
s
/P (where f
s
is the DAC sampling frequency), i.e., the
impulses are located at the repetition frequency of the PRBS sequence. For dense sampling of the
frequency domain, the sequence length P should be long. However, to view the impulsive sampling
eect over a wide bandwidth, the sequence length P should be short.
The 1-bit PRBS output for a 5-bit LFSR with taps [5,3] was was used to generate a 14-bit
DAC word that toggled between the DAC full-scale values of 0000h and 3FFFh. The DAC was
clocked at 100MHz. Figure 15 shows an oscilloscope trace and AD9433 ADC samples for 500ns of
the repeating 31 sample (310ns) sequence. The oscilloscope trace in Figure 15(a) was obtained using
a LeCroy LC584AXL oscilloscope. The DAC output (oscilloscope input) was terminated to 50,
and the 200MHz scope bandwidth limit was enabled. The oscilloscope waveform amplitude was
600mV
pp
. The ADC trace in Figure 15(b) toggles between ADC codes of around 800. The 12-bit
ADC input voltage range is -1.0V to 1.0V, so codes of 800 correspond to voltages of 390mV, or
780mV
pp
. The dierence in voltages observed between the two measurements is most likely due to
a termination impedance mismatch; the ADC input termination appears to be 100, rather than
50 (the schematic uses a pair of 50 terminations, whereas the data sheet recommends 25).
Figure 16 shows the DAC output power spectrum for DC to 200MHz (over-sampled), and for
Nyquist-rate sampling of DC to 50MHz (by the ADC). The frequency-domain sampling impulses
are spaced every 100MHz/31 = 3.2258MHz. The spectrum in Figure 16(b) was obtained using an
Anritsu Spectrum Master MS2721A portable spectrum analyzer, while the spectrum in Figure 16(d)
was calculated from AD9433 ADC samples; FPGA RAM was used to capture 8192 samples, of which
8184 samples were used (264 repetitions of the 31-sample PRBS sequence).
42
0 10 20 30 40 50
1000
800
600
400
200
0
200
400
600
800
1000
Sample
A
m
p
l
i
t
u
d
e

(
A
D
C

c
o
d
e
)
(a)
(b)
Figure 15: PRBS [5,3] 1-bit sequence samples; (a) oscilloscope trace and (b) AD9433 analog-to-
digital converter samples (sampling at 100MHz). The repeat period of the PRBS5 sequence is 31
samples, or 100MHz/31 = 3.2258MHz; as shown by the markers on the oscilloscope trace in (a).
43
0 50 100 150 200
90
80
70
60
50
40
30
20
10
0
Frequency (MHz)
P
o
w
e
r

(
d
B
m
)
0 50 100 150 200
90
80
70
60
50
40
30
20
10
0
Frequency (MHz)
P
o
w
e
r

(
d
B
m
)
0 10 20 30 40 50
90
80
70
60
50
40
30
20
10
0
Frequency (MHz)
P
o
w
e
r

(
d
B
m
)
0 10 20 30 40 50
90
80
70
60
50
40
30
20
10
0
Frequency (MHz)
P
o
w
e
r

(
d
B
m
)
(a) (b)
(c) (d)
Figure 16: PRBS [5,3] 1-bit sequence power spectra; (a) ideal oversampled spectra and (b) mea-
sured oversampled spectra (Anritsu spectrum analyzer), and (c) ideal Nyquist-sampled spectra and
(d) measured Nyquist-sampled spectra (AD9433 ADC). The frequency spacing of the impulses is
100MHz/31 = 3.2258MHz.
44
6.3 Digital noise source
The digital noise source was congured for 14-bit uniform noise (using a 31-bit LFSR with taps
[31,28]). The digital noise output was driven to the DSP kit 14-bit DAC as a straight-binary code
(the format expected by the DAC)
4
. The DAC output was then either connected directly to the 12-
bit ADC on the DSP kit, or low-pass ltered and connected to the ADC. Figure 17 shows the uniform
noise source results. The DAC output voltage can only exercise half the ADC input voltage range.
The ADC histograms show that there are no missing codes (within the voltage range exercised).
The spectrum analyzer spectrum in Figure 17(c) shows how the DAC generates signal frequencies
far beyond its 100MHz clock frequency, and far beyond the ADC Nyquist bandwidth of 50MHz.
The spectrum analyzer spectrum in Figure 17(f) shows that the 50MHz low-pass lter supplied with
the DSP kit does not suppress the signal adequately above 50MHz; signicant aliasing occurs. The
histogram in Figure 17(a) shows the uniform nature of the PRBS source, while Figure 17(d) shows
how ltering the signal changes its response to Gaussian.
The digital noise source was then congured for 14-bit Gaussian noise (using the sum of four
samples of uniform noise). Figure 18 shows the noise source response for the direct DAC-to-ADC
connection and for the 50MHz low-pass ltered connection. The power in the Gaussian noise source
is 6dB lower than that of the uniform noise source, as expected, since the averaging of four samples
reduces the variance by a factor of 4.
The power units on the ADC spectra and Anritsu spectra dier; the ADC spectra are in units of
fractional integer power (power relative to an RMS of one at ADC full-scale), whereas the Anritsu
plots are in dBm. The main point of the Anritsu plots is to show that the ADC spectra contain
aliased power.
4
The signed output of the digital noise source was converted to unsigned by inverting the most-signicant bit.
45
2000 1500 1000 500 0 500 1000 1500 2000
0
20
40
60
80
100
120
140
160
180
200
O
c
c
u
r
r
e
n
c
e
0 10 20 30 40 50
50
45
40
35
30
25
20
15
10
5
0
Frequency (MHz)
P
o
w
e
r

(
d
B
)
0 50 100 150 200
80
70
60
50
40
30
20
10
0
Frequency (MHz)
P
o
w
e
r

(
d
B
m
)
2000 1500 1000 500 0 500 1000 1500 2000
0
50
100
150
200
250
300
O
c
c
u
r
r
e
n
c
e
0 10 20 30 40 50
50
45
40
35
30
25
20
15
10
5
0
Frequency (MHz)
P
o
w
e
r

(
d
B
)
0 50 100 150 200
80
70
60
50
40
30
20
10
0
Frequency (MHz)
P
o
w
e
r

(
d
B
m
)
(a)
(b)
(c)
(d)
(e)
(f)
Figure 17: Digital noise source Uniform noise response. Direct DAC-to-ADC connection; (a) 12-bit
ADC samples histogram, (b) ADC power spectrum, (c) Anritsu power spectrum. 50MHz low-pass
lter between the DAC and ADC; (d) 12-bit ADC samples histogram, (e) ADC power spectrum, (f)
Anritsu power spectrum.
46
2000 1500 1000 500 0 500 1000 1500 2000
0
50
100
150
200
250
300
350
400
450
O
c
c
u
r
r
e
n
c
e
0 10 20 30 40 50
50
45
40
35
30
25
20
15
10
5
0
Frequency (MHz)
P
o
w
e
r

(
d
B
)
0 50 100 150 200
80
70
60
50
40
30
20
10
0
Frequency (MHz)
P
o
w
e
r

(
d
B
m
)
2000 1500 1000 500 0 500 1000 1500 2000
0
100
200
300
400
500
600
O
c
c
u
r
r
e
n
c
e
0 10 20 30 40 50
50
45
40
35
30
25
20
15
10
5
0
Frequency (MHz)
P
o
w
e
r

(
d
B
)
0 50 100 150 200
80
70
60
50
40
30
20
10
0
Frequency (MHz)
P
o
w
e
r

(
d
B
m
)
(a)
(b)
(c)
(d)
(e)
(f)
Figure 18: Digital noise source Gaussian noise response. Direct DAC-to-ADC connection; (a) 12-bit
ADC samples histogram, (b) ADC power spectrum, (c) Anritsu power spectrum. 50MHz low-pass
lter between the DAC and ADC; (d) 12-bit ADC samples histogram, (e) ADC power spectrum, (f)
Anritsu power spectrum.
47
References
[1] P. Alfke. XAPP052: Ecient shift regisiters, LFSR counters, and long pseudo-random sequence
generators (v1.1). Xilinx Application Note, 1996. (http://www.xilinx.com, xapp052.pdf).
[2] M. George and P. Alfke. XAPP210: Linear feedback shift registers in Virtex devices (v1.3).
Xilinx Application Note, 2007. (http://www.xilinx.com, xapp210.pdf).
[3] S. Haykin. Communication Systems. Wiley, 3rd edition, 1994.
[4] P. Horowitz and W. Hill. The Art of Electronics. Cambridge University Press, 2nd edition,
1989.
[5] D. Huangi and M. Matera. XAPP661: RocketIO Transceiver Bit-Error Rate Tester (v2.0.2).
Xilinx Application Note, 2004. (http://www.xilinx.com, xapp661.pdf).
[6] A. Miller and M. Gulotta. XAPP211: PN generators using the SRL macro (v1.2). Xilinx
Application Note, 2004. (http://www.xilinx.com, xapp211.pdf).
[7] R. N. Mutagi. Pseudo noise sequences for engineers. Electronics & Communications Engineering
Journal, 8(2):7987, April 1996.
[8] J. J. OReilly. Series-parallel generation of m-sequences. The Radio and Electronic Engineer,
45(4):171176, April 1975.
[9] D. Riccardi and P. Novellini. XAPP884: An Attribute-Programmable PRBS Generator and
Checker (v1.0). Xilinx Application Note, 2011. (http://www.xilinx.com, xapp884.pdf).
[10] T. J. Rouphael. RF and Digital Signal Processing for Software-Dened Radio: A Multi-Standard
Multi-Mode Approach. Newnes, 2009.
[11] H. Tarn, K. Neilson, R. Uribe, and D. Hawke. XAPP1018: Designing Ecient Wireless Digital
Up and Down Converters Leveraging CORE Generator and System Generator (v1.0). Xilinx
Application Note, 2007. (http://www.xilinx.com, xapp1018.pdf).
[12] Wikipedia. Wikipedia, the free encyclopedia, 2011.
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(http://www.xilinx.com/, lfsr.pdf).
48

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