Opa 2333

0.
1-Hz TO 10-Hz NOISE

5
0
0

n
V
/
d
i
v
1 s/div
1
2
3
5
4
V+
-IN
OUT
V-
+IN
OPA333
SOT23-5
1
2
3
5
4
V+
OUT
+IN
V-
-IN
OPA333
SC70-5
1
2
3
4
8
7
6
5
V+
OUT B
-IN B
+IN B
OUT A
-IN A
+IN A
V-
Exposed
Thermal
Die Pad
on
Underside
OPA2333
DFN-8 (SON-8)
O P A 3 3 3
O P A 2 3 3 3
www.ti.com SBOS351D MARCH 2006 REVISED NOVEMBER 2013
1 .8 - V , m i c r o P owe r , C M O S O p e r a tion a l A mp l if ie r s , Z e r o- D r if t S e r ie s
C he ck f or S a mp l e s : O P A 3 3 3 , O P A 2 3 3 3
1 FEA TURES D ES C RIP TIO N
The OPA333 series of CMOS operational amplifiers
2 Low O f f s e t V ol ta ge : 1 0 V (ma x)
use a proprietary auto-calibration technique to
Z e r o D r if t: 0.05 V /C (ma x)
simultaneously provide very low offset voltage (10
0.01 - Hz to 1 0- Hz Nois e : 1 .1 V
P P V, max) and near-zero drift over time and
temperature. These miniature, high-precision, low
Quie s ce n t C ur r e n t: 1 7 A
quiescent current amplifiers offer high-impedance
S in gl e - S up p l y O p e r a tion
inputs that have a common-mode range 100 mV
S up p l y V ol ta ge : 1 .8 V to 5.5 V
beyond the rails, and rail-to-rail output that swings
within 50 mV of the rails. Single or dual supplies as
Ra il - to- Ra il In p ut/O utp ut
low as +1.8 V (0.9 V) and up to +5.5 V (2.75 V)
m i c r o S ize P a cka ge s : S C 70 a n d S O T2 3
can be used. These devices are optimized for low-
voltage, single-supply operation.
A P P LIC A TIO NS
The OPA333 family offers excellent CMRR without
Tr a n s duce r s
the crossover associated with traditional
Te mp e r a tur e M e a s ur e me n ts
complementary input stages. This design results in
superior performance for driving analog-to-digital
El e ctr on ic S ca l e s
converters (ADCs) without degradation of differential
M e dica l In s tr ume n ta tion
linearity.
Ba tte r y- P owe r e d In s tr ume n ts
The OPA333 (single version) is available in the
Ha n dhe l d Te s t Equip me n t
SC70-5, SOT23-5, and SO-8 packages. The
OPA2333 (dual version) is offered in DFN-8 (3 mm
3 mm), MSOP-8, and SO-8 packages. All versions
are specified for operation from40C to +125C.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright 20062013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
O P A 3 3 3
O P A 2 3 3 3
SBOS351D MARCH 2006 REVISED NOVEMBER 2013 www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range fromsubtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
O RD ERING INFO RM A TIO N
(1 )
(1) For the most current package and ordering information see the Package Option Addendumat the end of this document, or visit the
device product folder at www.ti.com.
A BS O LUTE M A XIM UM RA TINGS
(1 )
V A LUE UNIT
Supply +7 V
Voltage
Signal input terminals
(2)
0.3 to (V+) +0.3 V
Signal input terminals
(2)
10 mA
Curent
Output short-circuit
(3)
Continuous mA
Operating, T
A
40 to +150 C
Temperature Storage, T
stg
65 to +150 C
J unction, T
J
+150 C
Human body model (HBM) 4000 V
Electrostatic discharge (ESD) ratings Charged device model (CDM) 1000 V
Machine model (MM) 400 V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximumconditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.3 V beyond the supply rails should
be current limited to 10 mA or less.
(3) Short-circuit to ground, one amplifier per package.
2 Submit Documentation Feedback Copyright 20062013, Texas Instruments Incorporated
Product Folder Links: OPA333 OPA2333
O P A 3 3 3
O P A 2 3 3 3
ELEC TRIC A L C HA RA C TERIS TIC S : V
S
= +1 .8 V to +5.5 V
At T
A
=+25C, R
L
=10 k connected to V
S
/ 2, V
CM
=V
S
/ 2, and V
OUT
=V
S
/ 2, unless otherwise noted.
P A RA M ETER TES T C O ND ITIO NS M IN TYP M A X UNIT
O FFS ET V O LTA GE
V
OS
Input offset voltage V
S
=+5 V 2 10 V
dV
OS
/dT Input offset voltage drift T
A
=40C to +125C 0.02 0.05 V/C
PSRR Power-supply rejection ratio V
S
=+1.8 V to +5.5 V, T
A
=40C to +125C 1 5 V/V
Long-termstability
(1)
See note
(1)
V
Channel separation, dc 0.1 V/V
INP UT BIA S C URRENT
70 200 pA
I
B
Input bias current
T
A
=40C to +125C 150 pA
I
OS
Input offset current 140 400 pA
NO IS E
f =0.01 Hz to 1 Hz 0.3 V
PP
Input voltage noise
f =0.1 Hz to 10 Hz 1.1 V
PP
i
n
Input current noise f =10 Hz 100 fA/Hz
INP UT V O LTA GE
V
CM
Common-mode voltage range (V) 0.1 (V+) +0.1 V
(V) 0.1 V <V
CM
<(V+) +0.1 V,
CMRR Common-mode rejection ratio 106 130 dB
T
A
=40C to +125C
INP UT C A P A C ITA NC E
Differential 2 pF
Common-mode 4 pF
O P EN- LO O P GA IN
(V) +100 mV <V
O
<(V+) 100 mV,
A
OL
Open-loop voltage gain 106 130 dB
R
L
=10 k, T
A
=40C to +125C
FREQUENC Y RES P O NS E
GBW Gain-bandwidth product C
L
=100 pF 350 kHz
SR Slewrate G =+1 0.16 V/s
O UTP UT
R
L
=10 k 30 50 mV
Voltage output swing fromrail
R
L
=10 k, T
A
=40C to +125C 70 mV
I
SC
Short-circuit current 5 mA
C
L
Capacitive load drive See Typical Characteristics
Open-loop output impedance f =350 kHz, I
O
=0 A 2 k
P O WER S UP P LY
V
S
Specified voltage range 1.8 5.5 V
I
O
=0 A 17 25 A
I
Q
Quiescent current per amplifier
T
A
=40C to +125C 28 A
Turn-on time V
S
=+5 V 100 s
TEM P ERA TURE
Specified range 40 +125 C
T
A
Operating range 40 +150 C
T
stg
Storage range 65 +150 C
(1) 300-hour life test at +150C demonstrated randomly distributed variation of approximately 1 V.
Copyright 20062013, Texas Instruments Incorporated Submit Documentation Feedback 3
O P A 3 3 3
O P A 2 3 3 3
THERM A L INFO RM A TIO N: O P A 3 3 3
O P A 3 3 3
THERM A L M ETRIC
(1 )
D (S O IC ) D BV (S O T2 3 ) D C K (S C 70) UNITS
8 P INS 5 P INS 5 P INS
J A
J unction-to-ambient thermal resistance 140.1 220.8 298.4
J Ctop
J unction-to-case (top) thermal resistance 89.8 97.5 65.4
J B
J unction-to-board thermal resistance 80.6 61.7 97.1
C/W
J T
J unction-to-top characterization parameter 28.7 7.6 0.8
J B
J unction-to-board characterization parameter 80.1 61.1 95.5
J Cbot
J unction-to-case (bottom) thermal resistance N/A N/A N/A
(1) For more information about traditional and newthermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
THERM A L INFO RM A TIO N: O P A 2 3 3 3
O P A 2 3 3 3
THERM A L M ETRIC
(1 )
D (S O IC ) D GK (M S O P ) D RB (D FN) UNITS
8 P INS 8 P INS 8 P INS
J A
J unction-to-ambient thermal resistance 124.0 180.3 46.7
J Ctop
J unction-to-case (top) thermal resistance 73.7 48.1 26.3
J B
J unction-to-board thermal resistance 64.4 100.9 22.2
C/W
J T
J unction-to-top characterization parameter 18.0 2.4 1.6
J B
J unction-to-board characterization parameter 63.9 99.3 22.3
J Cbot
J unction-to-case (bottom) thermal resistance N/A N/A 10.1
(1) For more information about traditional and newthermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
1
2
3
4
8
7
6
5
V+
OUT B
-IN B
+IN B
OUT A
-IN A
+IN A
V-
Exposed
Thermal
Die Pad
on
Underside
(2)
1
2
3
4
8
7
6
5
V+
OUT B
-IN B
+IN B
OUT A
-IN A
+IN A
V-
A
B
1
2
3
4
8
7
6
5
NC
(1)
V+
OUT
NC
(1)
NC
(1)
-IN
+IN
V-
1
2
3
5
4
V+
OUT
+IN
V-
-IN
1
2
3
5
4
V+
-IN
OUT
V-
+IN
O P A 3 3 3
O P A 2 3 3 3
P IN C O NFIGURA TIO NS : O P A 3 3 3
D BV P A C KA GE
D C K P A C KA GE
S O T2 3 - 5
S C 70- 5
(TO P V IEW)
(TO P V IEW)
D P A C KA GE
S O - 8
(TO P V IEW)
(1) NC denotes no internal connection.
P IN C O NFIGURA TIO NS : O P A 2 3 3 3
D RB P A C KA GE D A ND D GK P A C KA GES
D FN- 8 (S O N- 8 ) S O - 8 A ND M S O P - 8 (V S S O P - 8 )
(TO P V IEW) (TO P V IEW)
(2) Connect thermal die pad to V.
O P A 3 3 3
O P A 2 3 3 3
TYP IC A L C HA RA C TERIS TIC S
Ta bl e 1 . Lis t of Typ ica l C ha r a cte r is tics
TITLE FIGURE
OFFSET VOLTAGE PRODUCTION DISTRIBUTION Figure 1
OFFSET VOLTAGE DRIFT PRODUCTION DISTRIBUTION Figure 2
OPEN-LOOP GAIN vs FREQUENCY Figure 3
COMMON-MODE REJ ECTION RATIO vs FREQUENCY Figure 4
POWER-SUPPLY REJ ECTION RATIO vs FREQUENCY Figure 5
OUTPUT VOLTAGE SWING vs OUTPUT CURRENT Figure 6
INPUT BIAS CURRENT vs COMMON-MODE VOLTAGE Figure 7
INPUT BIAS CURRENT vs TEMPERATURE Figure 8
QUIESCENT CURRENT vs TEMPERATURE Figure 9
LARGE-SIGNAL STEP RESPONSE Figure 10
SMALL-SIGNAL STEP RESPONSE Figure 11
POSITIVE OVERVOLTAGE RECOVERY Figure 12
NEGATIVE OVERVOLTAGE RECOVERY Figure 13
SETTLING TIME vs CLOSED-LOOP GAIN Figure 14
SMALL-SIGNAL OVERSHOOT vs LOAD CAPACITANCE Figure 15
0.1-Hz TO 10-Hz NOISE Figure 16
CURRENT AND VOLTAGE NOISE SPECTRAL DENSITY vs FREQUENCY Figure 17
O
u
t
p
u
t

S
w
i
n
g

(
V
)
0
3
2
1
0
-1
-2
-3
1
Output Current (mA)
10 7 8 9 6 5 4 3 2
- 40 C
- 40 C
- 40 C
+25 C
+25 C
+25 C
+125 C
+125 C
V = 2.75 V
S
V = 0.9 V
S
P
S
R
R

(
d
B
)
1
120
100
80
60
40
20
0
10k 100k 1k 100 10
Frequency (Hz)
1M
+PSRR
-PSRR
A
(
d
B
)
O
L
10
120
100
80
60
40
20
0
-20
P
h
a
s
e

(
)
250
200
150
100
50
0
-50
-100
100k 10k 1k 100
Frequency (Hz)
1M
Phase
Gain
C
M
R
R

(
d
B
)
1
140
120
100
80
60
40
20
0
100k 10k 1k 100 10
Frequency (Hz)
1M
P
o
p
u
l
a
t
i
o
n
0
0
.
0
0
2
5
0
.
0
0
5
0
0
.
0
0
7
5
0
.
0
1
0
0
0
.
0
1
2
5
0
.
0
1
5
0
0
.
0
1
7
5
0
.
0
2
0
0
0
.
0
2
2
5
0
.
0
2
5
0
0
.
0
2
7
5
0
.
0
3
0
0
0
.
0
3
2
5
0
.
0
3
5
0
0
.
0
3
7
5
0
.
0
4
0
0
0
.
0
4
2
5
0
.
0
4
5
0
0
.
0
4
7
5
0
.
0
5
0
0
Offset Voltage Drift ( V/ C) m
P
o
p
u
l
a
t
i
o
n
-
1
0
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2
-
1
0
1
2 3 4 5 6 7 8 9
1
0
Offset Voltage ( V) m
O P A 3 3 3
O P A 2 3 3 3
TYP IC A L C HA RA C TERIS TIC S
At T
A
=+25C, V
S
=+5 V, and C
L
=0 pF, unless otherwise noted.
Figur e 1 . O FFS ET V O LTA GE P RO D UC TIO N D IS TRIBUTIO N Figur e 2 . O FFS ET V O LTA GE D RIFT P RO D UC TIO N
D IS TRIBUTIO N
Figur e 3 . O P EN- LO O P GA IN vs FREQUENC Y Figur e 4. C O M M O N- M O D E REJEC TIO N RA TIO vs
FREQUENC Y
Figur e 5. P O WER- S UP P LY REJEC TIO N RA TIO vs Figur e 6. O UTP UT V O LTA GE S WING vs O UTP UT C URRENT
FREQUENC Y
2

V
/
d
i
v
0
1

V
/
d
i
v
0
Input
Output
10 kW
1 kW
OPA333
+2.5 V
-2.5 V
Time (50 s/div) m
O
u
t
p
u
t

V
o
l
t
a
g
e

(
5
0

m
V
/
d
i
v
)
Time (5 s/div) m
G = +1
R = 10 kW
L
I
(
A
)
m
Q
-50
25
20
15
10
5
0
-25
Temperature ( C)
125 100 75 50 25 0
V = 1.8 V
S
V = 5.5 V
S
O
u
t
p
u
t

V
o
l
t
a
g
e

(
1

V
/
d
i
v
)
Time (50 s/div) m
G = 1
R = 10 kW
L
I
(
p
A
)
B
-50
200
150
100
50
0
-50
-100
-150
-200
-25
Temperature ( C)
125 100 75 50 25 0
V = 5.5 V
S
V = 1.8 V
S -I
B
-I
B
+I
B
+I
B
I
(
p
A
)
B
0
100
80
60
40
20
0
-20
-40
-60
-80
-100
1
Common-Mode Voltage (V)
5 4 3 2
-I
B
+I
B
O P A 3 3 3
O P A 2 3 3 3
TYP IC A L C HA RA C TERIS TIC S (con tin ue d)
At T
A
=+25C, V
S
=+5 V, and C
L
Figur e 7. INP UT BIA S C URRENT vs C O M M O N- M O D E Figur e 8 . INP UT BIA S C URRENT vs TEM P ERA TURE
V O LTA GE
Figur e 9. QUIES C ENT C URRENT vs TEM P ERA TURE Figur e 1 0. LA RGE- S IGNA L S TEP RES P O NS E
Figur e 1 1 . S M A LL- S IGNA L S TEP RES P O NS E Figur e 1 2 . P O S ITIV E O V ERV O LTA GE REC O V ERY
V
o
l
t
a
g
e

N
o
i
s
e

(
n
V
/
)
H
z
1
1000
100
10
C
u
r
r
e
n
t

N
o
i
s
e

(
f
A
/
)
H
z
1000
100
10
1k 100 10
Frequency (Hz)
10k
Current Noise
Voltage Noise
Continues with no 1/f (flicker) noise.
O
v
e
r
s
h
o
o
t

(
%
)
10
40
35
30
25
20
15
10
5
0
100
Load Capacitance (pF)
1000
5
0
0
n
V
/
d
i
v
1s/div
S
e
t
t
l
i
n
g
T
i
m
e

(
s
)
m
1
600
500
400
300
200
100
0
10
Gain (dB)
100
0.001%
0.01%
4-V Step
2

V
/
d
i
v
0
1

V
/
d
i
v
0
Time (50 s/div) m
Input
Output
10 kW
1 kW
OPA333
+2.5 V
-2.5 V
O P A 3 3 3
O P A 2 3 3 3
TYP IC A L C HA RA C TERIS TIC S (con tin ue d)
At T
A
=+25C, V
S
=+5 V, and C
L
Figur e 1 3 . NEGA TIV E O V ERV O LTA GE REC O V ERY Figur e 1 4. S ETTLING TIM E vs C LO S ED - LO O P GA IN
Figur e 1 5. S M A LL- S IGNA L O V ERS HO O T Figur e 1 6. 0.1 - Hz TO 1 0- Hz NO IS E
vs LO A D C A P A C ITA NC E
Figur e 1 7. C URRENT A ND V O LTA GE NO IS E S P EC TRA L D ENS ITY vs FREQUENC Y
5 kW
OPA333
10 mA max
+5 V
V
IN
V
OUT
I
OVERLOAD
Current-limiting resistor
required if input voltage
exceeds supply rails by
0.5 V.
O P A 3 3 3
O P A 2 3 3 3
D ETA ILED D ES C RIP TIO N
The OPA333 and OPA2333 are unity-gain stable and free from unexpected output phase reversal. These
devices use a proprietary auto-calibration technique to provide lowoffset voltage and very lowdrift over time and
temperature. For lowest offset voltage and precision performance, optimize circuit layout and mechanical
conditions. Avoid temperature gradients that create thermoelectric (Seebeck) effects in the thermocouple
junctions formed fromconnecting dissimilar conductors. Cancel these thermally-generated potentials by assuring
they are equal on both input terminals. Other layout and design considerations include:
Use lowthermoelectric-coefficient conditions (avoid dissimilar metals).
Thermally isolate components frompower supplies or other heat sources.
Shield op amp and input circuitry fromair currents, such as cooling fans.
Following these guidelines reduces the likelihood of junctions being at different temperatures, which can cause
thermoelectric voltages of 0.1 V/C or higher, depending on materials used.
O P ERA TING V O LTA GE
The OPA333 and OPA2333 op amps operate over a power-supply range of +1.8 V to +5.5 V (0.9 V to 2.75 V).
Parameters that vary over supply voltage or temperature are shown in the Typical Characteristics section.
C A UTIO N
Supply voltages higher than +7 V (absolute maximum) can permanently damage the
device.
INP UT V O LTA GE
The OPA333 and OPA2333 input common-mode voltage range extends 0.1 V beyond the supply rails. The
OPA333 is designed to cover the full range without the troublesome transition region found in some other rail-to-
rail amplifiers.
Typically, input bias current is approximately 70 pA; however, input voltages exceeding the power supplies can
cause excessive current to flow into or out of the input pins. Momentary voltages greater than the power supply
can be tolerated if the input current is limited to 10 mA. This limitation is easily accomplished with an input
resistor, as shown in Figure 18.
Figur e 1 8 . In p ut C ur r e n t P r ote ction
V
OUT
R = 20 kW
P
Op Amp V = GND -
OPA333
V
IN
V+ = +5 V
-5 V
Additional
Negative
Supply
O P A 3 3 3
O P A 2 3 3 3
INTERNA L O FFS ET C O RREC TIO N
The OPA333 and OPA2333 op amps use an auto-calibration technique with a time-continuous, 350-kHz op amp
in the signal path. This amplifier is zero-corrected every 8 s using a proprietary technique. Upon power-up, the
amplifier requires approximately 100 s to achieve specified V
OS
accuracy. This design has no aliasing or flicker
noise.
A C HIEV ING O UTP UT S WING TO THE O P A M P NEGA TIV E RA IL
Some applications require output voltage swings from0 V to a positive full-scale voltage (such as +2.5 V) with
excellent accuracy. With most single-supply op amps, problems arise when the output signal approaches 0 V,
near the lower output swing limit of a single-supply op amp. A good, single-supply op amp may swing close to
single-supply ground, but will not reach ground. The output of the OPA333 and OPA2333 can be made to swing
to, or slightly below, ground on a single-supply power source. This swing is acheived with the use of the use of
another resistor and an additional, more negative power supply than the op amp negative supply. A pull-down
resistor can be connected between the output and the additional negative supply to pull the output down below
the value that the output would otherwise achieve, as shown in Figure 19.
Figur e 1 9. V
O UT
Ra n ge to Gr oun d
The OPA333 and OPA2333 have an output stage that allows the output voltage to be pulled to the negative
supply rail, or slightly below, using the technique previously described. This technique only works with some
types of output stages. The OPA333 and OPA2333 are characterized to perform with this technique; the
recommended resistor value is approximately 20 k. Note that this configuration increases the current
consumption by several hundreds of microamps. Accuracy is excellent down to 0 V and as low as 2 mV.
Limiting and nonlinearity occurs below 2 mV, but excellent accuracy returns after the output is again driven
above 2 mV. Lowering the resistance of the pull-down resistor allows the op amp to swing even further below
the negative rail. Resistances as lowas 10 k can be used to achieve excellent accuracy down to 10 mV.
OPA333
ADS1100
Load
V
I C
2
R
1
4.99 kW
R
3
4.99 kW
R
4
48.7 kW
R
2
49.9 kW
+5 V
3 V
REF3130
R
7
1.18 kW
R
SHUNT
1 W
R
6
71.5 kW
R
N
56 W
R
N
56 W
(PGA Gain = 4)
FS = 3.0 V
Stray Ground-Loop Resistance
I
LOAD
R
1
V
EX
V
OUT
V
REF
R
1
OPA333
R R
R R
+5 V
+ +
+
- -
+
4.096 V
0.1 F m
+5 V
Zero
Adjust
K-Type
Thermocouple
40.7 V/ C m
R
2
549 W
R
9
150 kW
R
5
31.6 kW
R
1
6.04 kW
R
6
200 W
+5 V
0.1 F m
R
2
2.94 kW
V
O
R
3
60.4 W
R
4
6.04 kW
OPA333
D1
REF3140
O P A 3 3 3
O P A 2 3 3 3
A P P LIC A TIO N INFO RM A TIO N
Figure 20 shows a temperature measurement application
Figur e 2 0. Te mp e r a tur e M e a s ur e me n t
Figure 21 shows the basic configuration for a bridge amplifier.
Figur e 2 1 . S in gl e O p A mp Br idge A mp l if ie r
A low-side current shunt monitor is shown in Figure 22. R
N
are operational resistors used to isolate the ADS1100
from the noise of the digital I
2
C bus. The ADS1100 is a 16-bit converter; therefore, a precise reference is
essential for maximum accuracy. If absolute accuracy is not required and the 5-V power supply is sufficiently
stable, the REF3130 can be omitted.
NOTE: 1%resistors provide adequate common-mode rejection at small ground-loop errors.
Figur e 2 2 . Low- S ide C ur r e n t M on itor
V
1
-In
V
2
+In
R
1
R
2
2
3
5
6
1
R
2
OPA333
OPA333
INA152
V
O
V = (1 + 2R / R
O 2 1 2 1
) (V V ) -
OPA333
3 V
1 MW 60 kW
100 kW
1 MW
NTC
Thermistor
OPA333
Output
R
SHUNT
Load
V+
V+
R
G
R
L
R
(2)
1
10 kW
R
BIAS
+5V
zener
(1)
Two zener
biasing methods
are shown.
(3)
MOSFET rated to
stand-off supply voltage
such as BSS84 for
up to 50 V.
O P A 3 3 3
O P A 2 3 3 3
Additional application ideas are shown in Figure 23 through Figure 26.
(1) Zener rated for op amp supply capability (that is, 5.1 V for OPA333).
(2) Current-limiting resistor.
(3) Choose zener biasing resistor or dual NMOSFETs (FDG6301N, NTJ D4001N, or Si1034)
Figur e 2 3 . High- S ide C ur r e n t M on itor
Figur e 2 4. The r mis tor M e a s ur e me n t
Figur e 2 5. P r e cis ion In s tr ume n ta tion A mp l if ie r
R
1
100 kW
1/2
OPA2333
RA
Inverted
V
CM
+V
S
INA321
(1)
+VS
V
OUT
+V
S
+V
S
+V
S
OPA333
+V
S
1/2 V
S
dc
3
2 1
4
5
6
G = 1 kV/V
TOT
G = 5
INA
G = 200
OPA
f = 150 Hz
LPF
f = 0.5 Hz
HPF
(provides ac signal coupling)
V = +2.7 V to +5.5 V
S
BW = 0.5 Hz to 150 Hz
f = 0.5 Hz
O
Wilson
V
CENTRAL
(RA + LA + LL) / 3
7
ac
1/2 V
S
R
2
100 kW
1/2
OPA2333
LL
+V
S
R
3
100 kW
1/2
OPA2333
LA
R
4
100 kW
R
9
20 kW
R
6
100 kW
RL
+V
S
+V
S
1/2
OPA2333
1/2
OPA2333
1/2
OPA2333
C
4
1.06 nF
C
3
1 F m
R
14
1 MW
R
12
5 kW
R
13
318 kW
R
7
100 kW
R
8
100 kW
R
10
1 MW
C
2
0.64 F m
R
11
1 MW
C
1
47 pF
R
5
390 kW
O P A 3 3 3
O P A 2 3 3 3
(1) Other instrumentation amplifiers can be used, such as the INA326, which has lower noise, but higher quiescent
current.
Figur e 2 6. S in gl e - S up p l y, V e r y Low P owe r , EC G C ir cuit
O P A 3 3 3
O P A 2 3 3 3
LA YO UT GUID ELINES
GENERA L LA YO UT GUID ELINES
Attention to good layout practices is always recommended. Keep traces short and when possible, use a printed
circuit board (PCB) ground plane with surface-mount components placed as close to the device pins as possible.
Place a 0.1-F capacitor closely across the supply pins. Apply these guidelines throughout the analog circuit to
improve performance and provide benefits, such as reducing the electromagnetic interference (EMI)
susceptibility.
Operational amplifiers vary in susceptibility to radio frequency interference (RFI). RFI can generally be identified
as a variation in offset voltage or dc signal levels with changes in the interfering RF signal. The OPA333 is
specifically designed to minimize susceptibility to RFI and demonstrates remarkably low sensitivity compared to
previous generation devices. Strong RF fields may still cause varying offset levels.
D FN P A C KA GE
The OPA2333 is offered in an DFN-8 package (also known as SON). The DFN is a QFN package with lead
contacts on only two sides of the bottom of the package. This leadless package maximizes board space and
enhances thermal and electrical characteristics through an exposed pad.
DFN packages are physically small, have a smaller routing area, improved thermal performance, and improved
electrical parasitics. Additionally, the absence of external leads eliminates bent-lead issues.
The DFN package can be easily mounted using standard PCB assembly techniques. See Application Reports
SLUA271, QFN/SON PCB Attachment and SCBA017, Quad Flatpack No-Lead Logic Packages, both available
for download at www.ti.com.
NO TE
The exposed leadframe die pad on the bottomof the package should be connected to V
or left unconnected.
D FN LA YO UT GUID ELINES
Solder the exposed leadframe die pad on the DFN package to a thermal pad on the PCB. A mechanical drawing
showing an example layout is attached at the end of this data sheet. Refinements to this layout may be
necessary based on assembly process requirements. Mechanical drawings located at the end of this data sheet
list the physical dimensions for the package and pad. The five holes in the landing pattern are optional, and are
intended for use with thermal vias that connect the leadframe die pad to the heatsink area on the PCB.
Soldering the exposed pad significantly improves board-level reliability during temperature cycling, key push,
package shear, and similar board-level tests. Even with applications that have low-power dissipation, the
exposed pad must be soldered to the PCB to provide structural integrity and long-termreliability.
O P A 3 3 3
O P A 2 3 3 3
REV IS IO N HIS TO RY
NOTE: Page numbers for previous revisions may differ frompage numbers in the current version.
C ha n ge s f r om Re vis ion C (M a y 2 007) to Re vis ion D P a ge
Changed data sheet format to most current standard look and feel .................................................................................... 1
Added OPA2333 DFN-8 pinout to front page ....................................................................................................................... 1
Changed 2nd signal input terminals parameter in the Absolute MaximumRatings from"voltage" to "current" (typo) ........ 2
Added OPA333 thermal information table ............................................................................................................................ 4
Added OPA2333 thermal information table .......................................................................................................................... 4
Added Table 1 ...................................................................................................................................................................... 6
PACKAGE OPTION ADDENDUM
www.ti.com 12-Feb-2014
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (C) Device Marking
(4/5)
Samples
OPA2333AID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 O2333A
OPA2333AIDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br)
OPA2333AIDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br)
CU NIPDAUAG Level-1-260C-UNLIM -40 to 125 OBAQ
OPA2333AIDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br)
OPA2333AIDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS
& no Sb/Br)
OPA2333AIDGKTG4 ACTIVE VSSOP DGK 8 250 Green (RoHS
& no Sb/Br)
OPA2333AIDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br)
OPA2333AIDRBR ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR -40 to 125 BQZ
OPA2333AIDRBRG4 ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br)
OPA2333AIDRBT ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br)
OPA2333AIDRBTG4 ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br)
OPA2333AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br)
OPA333AID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br)
OPA333AIDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 OAXQ
OPA333AIDBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br)
OPA333AIDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br)
OPA333AIDBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br)
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (C) Device Marking
(4/5)
Samples
OPA333AIDCKR ACTIVE SC70 DCK 5 3000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 BQY
OPA333AIDCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS
& no Sb/Br)
OPA333AIDCKT ACTIVE SC70 DCK 5 250 Green (RoHS
& no Sb/Br)
OPA333AIDCKTG4 ACTIVE SC70 DCK 5 250 Green (RoHS
& no Sb/Br)
OPA333AIDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br)
OPA333AIDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br)
OPA333AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 3

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF OPA2333, OPA333 :
Automotive: OPA2333-Q1, OPA333-Q1

NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
OPA2333AIDGKT VSSOP DGK 8 250 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
OPA2333AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA2333AIDRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
OPA2333AIDRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
OPA333AIDBVR SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
OPA333AIDBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
OPA333AIDBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
OPA333AIDCKR SC70 DCK 5 3000 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3
OPA333AIDCKT SC70 DCK 5 250 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3
OPA333AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 31-Dec-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA2333AIDGKT VSSOP DGK 8 250 364.0 364.0 27.0
OPA2333AIDR SOIC D 8 2500 367.0 367.0 35.0
OPA2333AIDRBR SON DRB 8 3000 367.0 367.0 35.0
OPA2333AIDRBT SON DRB 8 250 210.0 185.0 35.0
OPA333AIDBVR SOT-23 DBV 5 3000 203.0 203.0 35.0
OPA333AIDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
OPA333AIDBVT SOT-23 DBV 5 250 180.0 180.0 18.0
OPA333AIDCKR SC70 DCK 5 3000 203.0 203.0 35.0
OPA333AIDCKT SC70 DCK 5 250 203.0 203.0 35.0
OPA333AIDR SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 31-Dec-2013
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per J ESD46, latest issue, and to discontinue any product or service per J ESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as components) are sold subject to TIs terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TIs terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license froma third party under the patents or other intellectual property of the
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Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
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Resale of TI components or services with statements different fromor beyond the parameters stated by TI for that component or service
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Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
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In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TIs goal is to
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TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
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Copyright 2014, Texas Instruments Incorporated

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1-Hz TO 10-Hz NOISE

Automotive: OPA2333-Q1, OPA333-Q1

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