Advance Instrumentation - I: Operational Amplifier Fundamentals

Advance Instrumentation - I
IC Department 1 Prof. J. B. Vyas

Chapter-1
Operational amplifier

An operational amplifier is a basically very high gain DC amplifier that uses feedback for
the control of gain, input impedance, output impedance and frequency characteristics. The
operational amplifier is an extremely efficient and versatile device and is primarily used to
perform various mathematical functions, such as computation and summation.
The characteristics of an ideal operational amplifier are constant gain over frequency,
infinite non inverting input impedance, zero output impedance, infinite common mode
rejection, no DC offset and zero amplifier noise. Commercially available operational
amplifiers are excellent but not ideal, so that one can expect deviation from characteristics
predicted from ideal assumption.
1. The performance of real operational amplifier
The actual characteristics of real Operational Amplifier are considerably more
complicated. The real operational amplifier may be modeled as shown in figure1. There
are two input terminals, and a single output terminal. If the output of Operational
Amplifier e
o
is nominally positive with respect to ground, the lower input terminal is also
positive and is therefore called the non inverting input. The upper input terminal input
waveform is inverted with respect to e
in
and is therefore called inverting input. The
resistance seen looking in to the amplifier between positive and negative terminal is Rd
(differential input impedance). The resistance seen looking back in to the amplifier from
the output terminal is Ro (open loop output impedance). A DC Input offset voltage e
os
, two
input bias current Ip and In, a frequency dependent open loop gain of the Operational
Amplifier A, a common mode input impedance Rcm, an input noise current Ina and an
input noise voltage e
na
is also included in the model.
2. Input offset voltage and input offset current.
All Operational Amplifier requires small and relatively constant (Ip and In) at each input to
make transistor in active region. The average value of these current is called the input bias
current I
B=
(I
P
+I
N
)/2. The difference of these current is called the input offset current
I
OFF
=( I
P
+I
N
).
The circuit of figure 2 shows a feedback back configuration including the main source of
offset error. Rs is included to reduce the output offset voltage to zero.
The low level DC input signal is converted to a square wave AC with analogue switches
S1 and S2, amplified as AC by a low noise amplifier O1 at a fixed gain G= (R1+R2)/R1
and demodulated to DC by the output switches S3 and S4. The DC offset voltage of the
amplifier e
os1
= (R1+R2)/R1 is then eliminated by the blocking capacitor C
O
(non polarized
4.7uF to 10uF). The offset voltage e
os2
of the buffer O2 may be either negligible or turned
out using as offset adjusting potentiometer. The maximum switching frequency FO is
mainly depends on the settling time of the operational amplifier O1.

-
(ep-en)A
ens
Ina
Ip
A
In
Ro
Ina
eo
+
Rcm
Rd
en
ep
Rc
eos
In
-
Ip
A
100K
R2
Equivalent ckt. for feedback
configuration
eo
+
990 E
R1
e-
Rs
e+
1K
eos

s p os p
R I e e =
2 1
R
e e
I
R
e
o n
n
n
+ =
( )
o n p
e A e e and =
( ) [ ]
2 1
2 1
1
//
1
R R I R I e
R R
AR
A
e
n s p os o
+
+
+
=
( ) [ ]
2 2
//
2 1
1
2 1
OFF
B n
OFF
B p
n s p os o
I
I andI
I
I insertingI
R R I R I e
R
R R
e
= + =
+
+
=
!
"
#
$
%
&
'
(
)
*
+
,
+
+ '
(
)
*
+
,
+
+
+
=
2 1
2 1
2 2 1
2 1
2
2 1
R R
R R
Rs
IOFF
Rs
R R
R R
IB eos
R
R R
eo
2
1
2
1 R I e
R
R
e
OFF os o
'
'
(
)
*
*
+
,
+ =
Referring to the circuit, Let

1

2

3

Where A is the open loop gain of the amplifier, e
os
is the input offset voltage, Ip is the
current flowing into positive terminal and In is the current flowing into negative terminal
of opamp. Substituting the values of e
p
and en equation (3) we get

4

Now if A is large, then equation (4) becomes

5

We obtain

6

If Rs = R
1
R
2
/R
1
+R
2
, Then equation (6) gives out an offset error of

7

Equation (7) can be used to limit the output offset drift due to variation in bias current and
input offset voltage with tempearture variation.
It is interesting to note that the offset produced at the output is not dependent upon the
inverting and non inverting configuration of the circuit. This means that for each
configuration, the offset error referred to the input side will be different, even though
overall gain may be same.

Example
A type 741 operational amplifier has the following paarmeters
Input offset volatge=7.5mV (max)
Input offset volatge temperature sensitivity=6V/C
Input offset current=300nA
Input offset current temperature sensitivity=0.5nA/C
Compute the DC error with the offset adjustment for the ampliifer shown in figure over the
temperature 0 to 50 degreeC

2
1
2
1 R I e
R
R
e
OFF os o
'
'
(
)
*
*
+
,
+ =
Non Inverting Amplifier
Rc
R1
eo
+
en
R2
ep
Rcm
A
-
Rd
( )A e e e
R
e
R
e e
l R
e
R
e e
I
e
R
n p o
cm
n
d
p n
n
d
p o
s
s
in
=
+
=
Solution

e
o
=101*50C *6V/C-100K*0.5nA*50C
e
o
=30.3mV-2.5nV
e
o
=27.8mV
The output offset varies from 0 to 27.8mV over the temperature of 0 to 50 degree.

3. The Input impedance and there effects

The infinite input impedance and zero output impedance of the ideal amplifier are
approached in the real circuit as a normally high input impedance and output impedance of
few hundred ohms in magnitude. Although the real opamp ahs high input impedance,
loading effect cannot be neglected. Common mode input impedance is usually high
typically greater than 10Mohms. In comparison of source3 impedance, it is essentially
infinite and has little effect on circuit operation. The differential input impedance however
may be as low as 10K Ohms or as high as 100MOhms depending upon amplifier type. The
open loop input impedance figure changes considerably when the amplifier is use with
feedback connection.

4. The Input impedance of a non inverting amplifier

Consider the equivalent circuit of figure, we wish to obtain an expression for the closed
loop input impedance.

8

9

10
1
2 2 2
1
2
1
R
R
es
Rcm
R
R
R
R
R
A IsRd
Rcm
esRd
es esA
d
+
'
'
(
)
*
*
+
,
+ + + + '
(
)
*
+
,
+ =
cm in
R A R R / ) 1 (
1
+ + =
en
en
R2
Rc
eo
Rd
Inverting Amplifier
-
A
Rcm
+
R1
( )
'
'
(
)
*
*
+
,
+
=
=
+
=
=
s
o
in
n o
cm d
n o n n s
n s
s
s
s
in
Ae
e
R
R
A e e
R R
e
R
e e
R
e e
R
e e
I
I
e
R
1
//
1
2 1
1

From 8, 9, 10 we have

Setting R
2
/R
d
=R
2
/R
cm
=0 in the above equation we have for Rin

Where =R
1
/R
1
+R
2
= feedback factor

5. The Input impedance of an inverting amplifier

Substituting these equations,

R1
eo
Equivalent cirucit for output impedence
+
-
A
R2
Rout
Rs
(ep-en)A
Ro
1 2
2
) (
R
e
R
e e
and
R
e e
R
e e A e
I
n n o
n o
o
n p o
o
=
+

=
( )
!
"
#
$
%
&
'
(
)
*
+
,
+
+ =
'
'
(
)
*
*
+
,
+ + + =
) // ( //
1
) // (
1
2
1
1
2
1
2
1
cm d in
cm d
R R
A
R
R R
R R A
R
R
R
AR
R
A eo
es

5. The Output impedance of an inverting and non inverting amplifier

Assume Ip and In are zero then we have

2 1
// ) 1 /( R R A Ro R
out
+ + =
2 1
1
2 1
1 1
R R
R
where
R R R
A
eo
Io
o
+
=
+
+
+
=
( )
!
"
#
$
%
&
'
(
)
*
+
,
+
+ = ) // ( //
1
2
1 cm d in
R R
A
R
R R
e+
ed/2
+
A
ecm
eo
Acm
-
-
ed/2
+
Effect of common mode gain
+
-
e-

Ro is open loop impedance of opamp
From these equations, we have

That is Rout is reduced.
The output impedance of the circuit is function of open loop output impedance of opamp
Ro, of amplification A and of resistor R1 and R2.

Example 2:
A type 741 amplifier with an open loop output impedance of Ro=70 and an open loop
DC gain A=2*10
5
is used in the circuit with R1=3K and R2=27K
Hence feedback factor =0.1
The resulting impedance at zero frequency is
Rout= 70/(1+2*10
5
)//30000 = 0.0035

Example 3 :
A type 741 amplifier with Rd=2M, Rcm=400M and an open loop DC gain A=2*10
5
is
used as non inverting amplifier with R1=1K and R2=100K
Thus from equation, input impedance is

Rin =363M

7. Common mode Rejection
The ideal operational amplifier provides an output proportional to differential voltage
applied to its input terminals and produces no output for common mode voltage (Voltage
common to both of its terminal). However, in practical case, because of slightly different
gains between the inverting and non inverting inputs common mode voltages are not
entirely cancelled in the output.

egain common
in openloopga
A
A
CMRR
CMRR
e
e A e
cm
cm
D o
mod
= =
'
(
)
*
+
,
+ =
Acm
A
ed/2
ecm/CMRR
e+
-
-
ecm
-
ed/2
+
e-
+
+
Equaivalent offset voltage induced by common mode gain
eo
2
1 log 20 ) 0 ( ) (
'
'
(
)
*
*
+
,
+ = =
cm
f
f
f CMRR f CMRR

For the circuit shown above, the output voltage is given by

e
o
=A(e
p
-e
n
)+A
cm
(e
p
+e
n
)/2 or
e
o
=e
D
A+e
cm
A
cm
22

Where e
D
is the differential voltage, e
cm
the common mode voltage, Acm the common
mode gain and A the differential gain (or open loop gain) of the operational amplifier.
from equation 22, we have

CMRR is common mode rejection ration of amplifier.
The error term (A*(e
cm
/CMRR)) in the equation 23 can be modeled as an additional offset
voltage equal to the common mode voltage divided by the CMRR.

CMRR is normally expressed in terms of dB and it is given by CMRR(dB)=20log(A/A
cm
).
For many operational amplifier, the CMRR as a function of frequency can be
approximated by

24

where f
cm
is the corner frequency of the CMRR and CMRR (f=0) the common mode
rejection ration at f=0.
In the case of operational amplifier connected in the non inverting configuration, the input
common mode voltage e
cm
varies directly with the input signal e
s
.

+
R2
Acm
A
-
Non-inverting amplifier with common mode error
ecm/CMRR
R1
e+
eo
es
e-
'
(
)
*
+
, +
'
'
(
)
*
*
+
,
+ =
CMRR
CMRR
R
R
e e
s o
1
1
1
2
2
200
1000
1 log 20 70 ) 1 (
'
(
)
*
+
,
+ = = dB KHz f CMRR

This is because the feedback provides a voltage at the inverting terminal, which follows
that at the non-inverting input (e
n
-e
p
)

Hence, e
p
=e
s
+e
s
/CMRR and e
n
=e
o
(R
1
/R
1
+R
2
)
If the open loop gain of the operational amplifier is large, then

25

Inverting amplifier have no error due to common mode gain because the non-inverting
input is grounded (e
p
=0) and e
cm
=0.

Example 4: A type 741 operational amplifier has the following specifications
Common mode rejection ration (f=0)= 70dB
Corner frequency of CMRR f
cm
= 200Hz. Determine the CMRR of the amplifier with
R1=1K, and R2=100K at the operating frequency f=1KHz.

Solution:
From equation (24)

Therefore CMRR=56dB
from equation 25 we have
e
o
=e
s
(101)+((1+63)/63)
e
o
=101.16e
s
Hence error due to common mode gain will be 1.6mV pp for an input voltage of 100mv
PP.

8. Supply voltage Rejection ration (SVRR)
the output voltage of ideal operational amplifier depends only on the input voltage and is
independent of power supply voltage. In real operational amplifier, the output voltage is a
function of power supply voltage. The SVRR may be defined by
ply
o
e
e
A
SVRR
sup
1
=
2
) ( ) (
ripple ripple
o
e e
A SVRR e
+
=
peak Vpeak e
ply
=

= 3 . 0
2
9 . 0 5 . 1
sup
p mVp e
V e
o
o
=
=
5 . 4
3 . 0 100 10 150
6
c
DC
f
f
j
A
A
+
=
1
C
-
eo
Ro
+
Equivalent cirucit for frequency response
A
(ep-en)A
es

SVRR= Change in input offset voltage/change in power supply voltage
Different manufacturer uses the different terms related to SVRR, such as the power supply
rejection ration(PSRR) and power supply sensitivity(PSS). These terms are expressed
either in a microvolt per volt or in dB. Let the ripple on the plus supply is going positive
while the ripple on the negative side is moving negative. If the ripple on the plus and
minus are unequal, ripple appears on the operational amplifier output therefore,

26

example5: A type 741 operational amplifier has a PSRR of 150V/V(max.). It is utilized
as a non-inverting amplifier with a closed loop gain of A
cl
=100. There is a 1.5V ripple on
the positive supply and a 0.9Vp-p ripple on the negative supply. Determine the ripple that
appears on the amplifier output?
Solution:

9. Frequency response

Open loop gain of an operational amplifier is an important factor in circuit design. It
determines the accuracy of the closed loop gain frequency response, input and output
impedance.
An open loop gain of a single pole operational amplifier may be represented by

27

fc
f
and
f
f
A
A
c
DC
1
2
tan
1
=
'
'
(
)
*
*
+
,
+
=

Where ADC is the open loop gain of the amplifier at zero frequency, fc the corner
frequency (or 3 dB cut off frequency) and f the operating frequency.
The equation may be expressed in rationalized form:

28

where is the phase angle.
example 6:
A type 741 amplifier has the following parameters:
open loop gain A
DC
=2*10
5
, corner frequency fc=5Hz. Compute the magnitude of gain A
and phase angle at f=10KHz.
Solution:
A = 20 log (A
DC
)-10log[1+(f/fc)
2
] = 40dB
= -89.97
The gain bandwidth product is 2*10
5
*5Hz or 1MHz
In the case of a non-inverting amplifier circuit, by utilizing equation 27, the resulting
amplitude e
o
/e
s
is A
cl
=A/(1+A) 29
Where feedback factor =R
1
/R
1
+R
2
, substituting of equation 27 into equation 29results in
expression of closed loop gain that can be written as

eo
e+
2.7K
741
es
3K
R1
R2
27K
-
+
Rs
e-
I
i A
A
Aclo
+
+
+
=
1
1
) 1 (
1
1 1
1
1
) 1 1 (
1
+
+ +
+
=
DC
C
DC
cl
A
f
f
j
A
A
DC
clo
C
cl
cl
A
A
f
f
j
A
A
) 1 1 (
1
0
+
+ +
=

Chapter-2
example 7:
open loop gain A
DC
=2*10
5
, corner frequency fc=5Hz. Determine the closed loop gain of
the non inverting amplifier shown in figure at f=10KHz.

Solution:
Aclo = 2*10
5
/(1+0.1*2*10
5
)= 9.9995
from equation 31 we have for closed loop gain
A
cl0
=9.8053
= -11.3
The bandwidth of amplifier f
B
=100KHz
In the case of a inverting amplifier circuit, by utilizing equation 27, the resulting amplitude
e
o
/e
s
is

32

Where feedback factor 1=R
1
/R
2
, substituting of equation 27 into equation 32results in
expression of closed loop gain that can be written as

or as

33

)
1 1
1
1 )( 1 1 (
0
+
+ +
=
DC
DC
cl
A
A
A
)
1 1
1
1 (
)
1 1
1
1 (
tan
1
+
+ =
+
+
=
DC
C B
DC
C
A
f f
bandwidth
A
f
f
741C
+
R2
R1
e-
eo
R
27K
es
2.5K
2.7K
-
e+
Inverting Amplifier
where A
cl0
is the closed loop gain of the inverting amplifier at zero frequency.

34

The phase angle

example 8:
open loop gain A
DC
=2*10
5
, corner frequency fc=5Hz. Determine the closed loop gain of
the non inverting amplifier shown in figure at f=20KHz.

Solution:
The feedback factor 1=2.7/27=.1, from equation 34 we have
Aclo = 2*10
5
/(1+0.1*2*10
5
)= 9.9995
from equation 33 we have for closed loop gain
A
cl
=9.766
= -12.4
The bandwidth of amplifier f
B
=91KHz

1 2 )
1 1
1
1 (
1

+
+ =
n
DC
C B
A
f f
e-
741C
+
2.5K
eo
R2
e-
e+
e+
R1
R1
e-
3K
+
-
+
eo
R
12K
R1
12K
2.5K
es
2.5K
741C
3K
-
741C
3K
12K
-
e+
Fig.13 Extending GBP by cascading

example 9:
open loop gain A
DC
=2*10
5
, corner frequency fc=5Hz. Determine the bandwidth of the
amplifier shown in figure 13

Solution:
The feedback factor 1=0.25, from equation 34 we have
The overall gain of the circuit is 64. The bandwidth is

Number of stages=3
The bandwidth is f
B
=102KHz

10. slew rate
The slew rate is defined as the maximum rate of change of output voltage per unit time.
S=slew rate=(de
o
/dt)max. The slew rate is generally expressed in volts/microseconds.

-
D
C
e-
e+
e-
es
e+
eo
Q2
+
IC2
Q8
2N1070
Fig.14 EQUAIVALENT REAL OPERATIONAL AMPLIFIER
Q7
2N1070
Q1
Q3

Figure 14 illustrates the slewing problem. The input signal is large enough to fully saturate
Q1 while turning Q2 completely off. Q1 then directs all available bias current into current
mirror and Q3 and D. with Q2 off Q3, can only sink its current. C and I through the second
stage IC2. And because I=C(de/dt), the output voltages maximum rate of change is de0/dt.
The 741 operational amplifiers, for instance, used a 30pF compensation capacitor that
charges from a 20uA bias current source and yields a 0.66uV/s slew rate.
For a sinusoidal signal, instantaneous voltage can be written as
e
s
=e
o
sinwt. The slew rate is defined as (de
o
/dt)
max
so we differentiate instantaneous voltage
to obtain
de
s
/dt=eo(2f)cos(2f)
it is maximum when cos(2f) is =1 so
(de
s
/dt)max=eo(2f)=S 35

example 10:
A type 741 internally compensated operational amplifier has a slew arte of 0.5uV/s.
Determine the maximum amplitude available at the output of the amplifier for a sine wave
with a frequency of 33KHz.
Solution:
The undistorted maximum output voltage
eo=S/2f=2.4V peak or 4.8V peak-peak
Driving the amplifier beyond its slew rate results in triangular output that decreases with
increase in frequency.
11. Noise
In operational amplifiers, noise is an unwanted signal. Most noise is broadband and is due
to the random thermal motion of electron charges. AS a results noise voltage and noise
current are super imposed on the inputs of the opamp. If the signal levels from the sensors
are very low, then the noise sources become significant. A circuit model for nose
discussion is shown here. in figure15.

+
ena
e-
Figure 15, Ampliifer with input current and volatge
noise errors
-
eo
e+
R1
Rs
A
R2
B
L
H
ce na no
f
f
f
f e e +
'
'
(
)
*
*
+
,
= ln
1
B
L
H
ci s na no
f
f
f
f R I e +
'
'
(
)
*
*
+
,
=
+
ln
2
B S
f KTR e 4 4 =
B
L
H
ci s na no
f
f
f
f R I e +
'
'
(
)
*
*
+
,
=
ln
3
10
10 28 . 1

The total input referred noise for the amplifier is calculated as follows.

Noise voltage component is

36

Noise current I
na+
component is

37

Noise current Ina-component is

38

The Resistor R
s
noise component is

39

where K is Boltzman constant is 1.38*10
23
j/degree absolute and
T is absolute temperature in Kelvin.

The Resistor R
2
noise component is

B no
f KTR
R R
R
e
2
2 1
1
5
4
+
=
B no
f KTR
R R
R
e
1
2 1
2
6
4
+
=
2
6
2
5
2
4
2
3
2
2
2
1
) ( ) ( ) ( ) ( ) ( ) (
no no no no no no no
e e e e e e e + + + + + =
!
"
#
$
%
&
=
ofsource noisepower
oisepower tota
NF
ln
log 10
!
!
"
#
$
$
%
&
+ + +
+ =
2
1
2
6
2
5
2
4
2
3
2
2
) (
) ( ) ( ) ( ) ( ) (
1 log 10
no
no no no no no
e
e e e e e
NF
nVRMS e
nV e
no
no
26 . 469
90
100
100
ln 200 20
1
1
=
+ '
(
)
*
+
,
=
nVRMS e
K pA e
no
no
4 . 1370
90
10
100
ln 2000 40 * 5 . 0
2
2
=
+ '
(
)
*
+
,
=

40

The Resistor R
1
noise component is

41

Total Noise
42

The amplifier noise figure is

43

if the noise signal is applied to the non inverting input and Rs is the
source resistance. Then

44

From this equation this can be seen that when Rs is small, noise voltage will dominant, a
and when large source resistance Rs is involved noise current will become important.

Example 11. A type 741 amplifier has the following parameters:
Input noise voltage ena=20nV/Hz. Voltage noise corner frequency fcc=200Hz.
Input noise current Ina=0.5pA/Hz. Current noise corner frequency fci=2000Hz.The
operational amplifier is used in the non inverting mode with a closed loop gain of 100.
Determine the value of the minimum noise figure (NF) in the frequency band from 10Hz to
100Hz. The ambient temperature is 300K.
Solution:
Choose R1=1K and R2=99K. Noise figure has its minimum value when
Rs=ena/Ina=40k. Hence, the optimum source resistance Rs=40K.
Bandwidth is fB=90Hz.

Noise current Ina+component is

nVrms e
no
16 . 244
4
=
nVrms e
no
8412 . 3
5
=
nVrms e
no
22 . 38
6
=
uVrms e
no
47 . 1 =
nVrms e
pA e
no
no
918 . 33
90
10
100
ln 2000 990 * 5 . 0
3
3
=
+ '
(
)
*
+
,
=
!
"
#
$
%
&
+ =
2
2
) ( 106 . 59614
) ( 1 . 2100827
1 log 10
nv
nv
NF

Noise current Ina-component is

The Resistor R
s
noise component is

The Resistor R
2
noise component is

The Resistor R
1
noise component is

Total Noise

The amplifier noise figure is

NF=15.59dB

Data sheets

General purpose Operational Amplifier 741C
Sr. No parameter amplitude Unit
1. Input offset voltage 7.5 mV
2. Input offset voltage drift 6 V/C
3. Input bias current 800 Na
4. Input offset current 300 nA
5. Input offset current drift 0.5 nA/C
6. Input resistance (differential) 2 M
7. Input resistance (Common mode) 400 M
8. CMRR 70(minimum) dB
9. SVRR 150 V/V
10. Large signal Voltage Gain 2*10
5

11. Slew Rate 0.5V V/sec
12. Open loop output resistance 70

13. Unity gain bandwidth 1 MHz
14. Input noise voltage 20 nV/Hz
15. Input noise current 0.5 pA/Hz
16. From the graph, the 3dB corner frequencies
17. Open loop gain 5 Hz
18. SVRR 200 Hz
19. CMRR 200 Hz

Very low noise Operational Amplifier OP27
Sr. No parameter amplitude Unit
20. Input offset voltage 0.3 mV
21. Input offset voltage drift 1.8 V/C
22. Input bias current +/-150 Na
23. Input offset current 135 nA
24. Input offset current drift 0.1 nA/C
25. Input resistance (differential) 4 M
26. Input resistance (Common mode) 2000 M
27. CMRR 94(minimum) dB
28. SVRR 86(min.) dB
29. Large signal Voltage Gain 8*10
5

30. Slew Rate 2.8 V/sec
31. Open loop output resistance 70

32. Unity gain bandwidth 8 MHz
33. Input noise voltage 3 nV/Hz
34. Input noise current 0.4 pA/Hz
35. From the graph, the 3dB corner frequencies
36. Open loop gain 10 Hz
37. SVRR 10 Hz
38. CMRR 2000 Hz

'
'
(
)
*
*
+
,
+
+
+ + +
+
+ +
+
+
+
= ) // ( 2
1 1
) // (
1
1
1
2 1
1
2 1
1
2 1
1
1
1
R R I
e
e e
e
R R I e
es
A
A
e
na
r
na ns
rl
OFF os o
es
e+
R2
e-
Inverting Amplifier
-15V
+15V
990E
1K
R1
+
Rs
741
100K
eo
-
'
'
(
)
*
*
+
,
+
+
+
+
= ) // (
1
1
1
2 1
1
1
1
R R I e
es
A
A
e
OFF os o

Inverting Amplifier

Figure illustrates the Inverting amplifier configuration

The application of Kirchoffs current law to the amplifier yields the relationship

Where
1
the feedback factor = (R
1
/R
2
), e
rl
, e
r2
and e
ns
are the noise voltage generated by
the resistance R1, R2 and Rs respectively.

Example 1: A type 741C operational amplifier has the following specifications
Input offset voltage drift = 1.8nV/C
Input offset current drift = 50pA/C
Supply Voltage rejection ration= 86dB
Large signal voltage gain= 4*10
5

Compute the DC errors with offset adjustment of the amplifier shown in figure above over
the temperature range from 0 to 50C. Calculate n bit accuracy.

Solution:
Reducing equation for DC error gives,

1
) 2 log(
72 . 5
10000
log
1
) 2 log(
log

'
(
)
*
+
,
=
Error
olatge FullscaleV
n
( ) [ ] ) 1 /( // //
2 1
A R R R R R
cm d in
+ + =
2 1 1 2 1
/ ) //( ) 1 /( R R R and R R A Ro R
out
+ = + + =
mV e
e e
Aclo SVRR e
3
2
4 . 14 6 . 15
* 100 * 10 * 50
2
* *
sup
6
sup
=
=

=
+

A) Offset drift and gain error
substituting the values in this equation we get
e
o
=100.97(-99.01mV+90nV-2.5mV)
or e
o
=-9997.283mV
B) Error due to supply voltage variation
SVRR=10
-86dB/20
=50V/V

Total error er=10000mV-(9997.28mV-3mV)=5.72mV
C) n-bit accuracy may be calculated as follows:

n=10 bits
Input impedance of the amplifier

Rin= 1K ohms
Output impedance of the amplifier

Rout =0.015ohms

'
'
(
)
*
*
+
,
+ + + + + +
+
+
= ) // ( 2 ) 1 ( ) // (
1
1
2 1 1 2 2 1
R R I e e e e R R I e
CMRRop
CMRRop
e
A
A
e
na r r na ns OFF os S o

990 E
R1
e-
1K
e+
eo
-
+
99K
Rs
OP27
es
R2

Chapter-3
Non-inverting Amplifier

Figure 2 illustrates the non- inverting amplifier.

The application of Kirchoffs current law to the amplifier yields the relationship

Where the feedback factor = (R
1
/R
1
+R
2
).

Example 2: A type OP27 operational amplifier has the following specifications
Large signal voltage gain= 8 X 10
5

Common mode rejection ration= 94dB
Input noise Voltage e
na
=3nv/Hz
Voltage noise corner frequency f
ce
= 27Hz
Input noise current i
na
=0.4pA/Hz
Current noise corner frequency f
ci
= 140Hz

Compute the AC errors of the amplifier shown in figure (2) in the frequency band 1Hz to
333Hz. Calculate the n bit accuracy for the full scale output voltage of 10V AC (peak to
peak).

Solution:

2
10
1 log 20 ) 0 ( ) ( '
(
)
*
+
,
+ = =
Hz
f
f SVRR f SVRR
B
20 / 66
10
dB
2
2
1 log 20 ) 0 ( ) ( '
(
)
*
+
,
+ = =
KHz
f
f CMRR f CMRR
B
20 / 9 . 96
10
dB
2
1
) 1 (
'
'
(
)
*
*
+
,
+
+
=
DC c
clo
op
op clo s
s
amp
A f
fA
CMRR
CMRR A e
e
e
2 10
10 5621 . 1 1
94 . 9998
10000
f
mV
mV e
amp
+
=
B
L
H
ce na clo no
f
f
f
f e A e +
'
'
(
)
*
*
+
,
= ln
1
B
L
H
ci na clo no
f
f
f
f I R R A e +
'
'
(
)
*
*
+
,
= ln ) 2 // 1 ( 2
2

SVRR(100Hz) = 86dB-20dB = 66dB or

= 0.5mV/V

e
sup=
RR * A
clo
* (Power supply ripple)

=0.5mV*100*10mV
= 0.5mV Peak to Peak

Common mode rejection ration

CMRR(100Hz) = 97dB-0.1dB = 96.9dB or

=70795

Error due to bandwidth

Where A
clo
= A
DC
/(1+A
DC
))=99.998

at f=333Hz, e
amp
=1.15mV

Noise calculation
Bandwidth f
B
=f
H
-f
L

= 333Hz-1 Hz =332Hz

e
no1
= 6.6VRMS

Noise current component is

B S clo no
f R A e
10
3
10 28 . 1
=
B clo no
f R A e
2
10
4
10 28 . 1
=
B clo no
f R A e
1
10
5
10 28 . 1 ) 1 (
=
2
5
2
4
2
3
2
2
2
1
) ( ) ( ) ( ) ( ) (
no no no no no no
e e e e e e + + + + =
1
) 2 log(
15 . 1
10000
log
1
) 2 log(
log

'
(
)
*
+
,
=
Error
olatge FullscaleV
n
clo DC c dB
A A f f /
3
=
cm in
R A R R / ) 1 (
1
+ + =
2 1
// ) 1 /( R R A Ro R
out
+ + =
e
no2
= 2.7VRMS

The Resistor R
s
noise component is

eno3=7.3VRMS

The Resistor R
2
noise component is

eno4=0.74VRMS

The Resistor R
1
noise component is

eno3=7.3VRMS

Total Noise

e
no
= 12.57Vrms or 75.42V peak to peak

In the above error analysis, the AC error terms are dominated by the error due
to bandwidth. Hence, the n-bit accuracy may be calculated as follows:

n=12 bits
Maximum operating frequency of the amplifier
f
max
=Slewrate/2e
o
f
max
=2.8V/sec/25V
f
max
= 89KHz

3-dB bandwidth of the amplifier

=80KHz
Input impedance of the amplifier

Rin= 2G ohms
Output impedance of the amplifier

Rout =8.7 milliohms

OP27
An inverting integartor
R
-
e+
R
+
es
e-
C
eo
- - -
'
(
)
*
+
,
+ + =
t
OFF
B os
OFF
t
os
t
s
o
R I
R I e dt
C
I
dt
RC
e
dt
RC
e
e
0 0 0
2
'
(
)
*
+
,
=
OFF
os o
I
R
e
C dt
de 1
( )
OFF
o
I
C dt
de 1
=

Integrator
If a capacitor is placed as the feedback resistor in the inverting amplifier, the results is an
Integrator. The integrator shown in figure, provides the out put which is proportional to the
time integral of the input signal.

This circuit is very important in the instrumentation as a charge balancing amplifier for
variable capacitance and piezo electric transducers. The transfer function of integrator is
given by

In the above equation e
os
is the offset voltage of operational amplifier. I
B
the bias current,
IOFF the offset current and RC the time constant of the integrator. If the input voltage es is
reduced to zero then the change in output voltage

Adjusting the e
os
to zero, then

An offset current of I
OFF
=300nA causes the output voltage to rise at a rate of 1V/sec. If
C=0.3uF. The performance of the integrator may be improved by selecting the FET input
amplifier (such as GA3140) and a high quality capacitor (Teflon or polycarbonate)

Example1 :
An integrator can be used to separate DC offset from AC signal without a coupling
capacitor. One such circuit is shown in figure.

es
39 K
10 K
e+
-
C
R
e-
Separation of DC Offset from AC signal
eo
e-
+
+
-
e+
eo
10 K
OP27
1uF
CA3140
-
= dt
RC
wt e
e
p
o
sin
wRC
wt e
e
p
o
cos
=

The integrator feeds a signal e
r
back to the input to reduce the DC level of the output to
zero. In this case feedback signal is added with the input signal on the resistor 10K to
remove DC offset. Low frequency cutoff is set by the integrator equal to 1/ 2RC and
OP27 serve as buffer.

Integrator in frequency domain

If the input voltage is sinusoidal input voltage e
s
=e
m
sin wt then output voltage becomes

'
'
(
)
*
*
+
,
+
'
'
(
)
*
*
+
,
+
'
'
(
)
*
*
+
,
=
'
'
'
'
'
(
)
*
*
*
*
*
+
,
'
'
(
)
*
*
+
,
+
'
'
(
)
*
*
+
,
+
'
'
(
)
*
*
+
,
+
'
'
(
)
*
*
+
,
+
'
'
(
)
*
*
+
,
+
=
fc
f
j
fo
f
j
fo
f
j A
Loopgain
fc
f
j
fo
f
j
fo
f
j A
fc
f
j
fo
f
j
A
e
e
DC
DC
DC
s
o
1 1
1 1
1 1 1
'
'
(
)
*
*
+
,
'
'
(
)
*
*
+
,
=

fo
f
fc
f
1 1
tan tan 90
R
e-
+
C
OP27
eo
Differentiating circuit
es
-
e+
R
'
(
)
*
+
,
+
+
+
+
+
=
RCs
RCs e
RCs
InRs
e
RCs
A
A
e
s
os o
1 1
1
1
The amplitude of output voltage is therefore inversely proportional to the angular
frequency. If the open loop gain of the amplifier is A is not infinite then

The phase shift

Where A
DC
is the open loop DC gain, fc is the open loop -3dB cutoff frequency, fo is the
integrator cutoff frequency and f is the operating frequency. If the fo =1000Hz,
A
DC
=2*10
3
, fc=5Hz then at f=100kHz, the loop gain = 10 and phase shift =-90 degree. The
integrator is stable for all frequency but the phase margin is -180-(-90)=-90 degree.

Differentiating circuits
Using the capacitor as input element to the operational amplifier yields a differentiating
circuit. Circuit shown here gives output proportional to derivative of input.

The application of KCL to the summing points yields the relationship

'
'
(
)
*
*
+
,
+
'
'
(
)
*
*
+
,
+
=
'
'
'
'
'
(
)
*
*
*
*
*
+
,
'
'
(
)
*
*
+
,
+
'
'
(
)
*
*
+
,
+
'
'
(
)
*
*
+
,
+
'
'
(
)
*
*
+
,
+
'
'
(
)
*
*
+
,
+
'
'
(
)
*
*
+
,
=
fc
f
j
fo
f
j
A
Loopgain
fc
f
j
fo
f
j
fo
f
j A
fc
f
j
fo
f
j
fo
f
j A
e
e
DC
DC
DC
s
o
1 1
1 1
1 1 1
'
'
(
)
*
*
+
,
'
'
(
)
*
*
+
,
=

fo
f
fc
f
1 1
tan tan
2
R I
R I
dt
de
RC e
dt
de
RC e
OFF
B
os
os
s
o
+ + =
eo
C
R
OP27
es
R
e+
-
e-
Practical Differentiating circuit
R1
+

if the open loop gain of the amplifier is infinite, then

If the input voltage is sinusoidal input voltage e
s
=e
m
sin wt then output voltage becomes
e
o
=wRCe
p
coswt. If A is not infinite then the transfer function becomes.

Phase shift

At high frequencies phase shift becomes -180 degree. the phase margin =-180-(-180)= 0
degree. Hence, the differentiating circuit is unstable.
One practical method of removing instability is shown in figure. The resistor R1 is added
to the input to limit high frequency gain of differentiating circuit. It makes the circuit less
susceptible to high frequency noise and ensures dynamic stability. The corner frequency
where gain limiting resistor comes in to the picture is given by f
1
=1/2R1C. For this
reason, f
1
should greater than 10 times of the highest input frequency.

'
'
(
)
*
*
+
,
+ +
'
'
(
)
*
*
+
,
+
'
'
(
)
*
*
+
,
+
=
'
'
'
'
'
(
)
*
*
*
*
*
+
,
'
'
(
)
*
*
+
,
+ +
'
'
(
)
*
*
+
,
+
'
'
(
)
*
*
+
,
+
'
'
(
)
*
*
+
,
+
'
'
(
)
*
*
+
,
+
=
1
1 1
1
1
1
1 1
1
1 1
f
f
j
o f
f
j
fo
f
j
f
f
j A
Loopgain
f
f
j
fo
f
j
fo
f
j
f
f
j A
jf
fo
R
Rc
fo
f
j
A
e
e
DC
DC
DC
s
o
'
'
(
)
*
*
+
,
+
'
'
(
)
*
*
+
,
'
'
(
)
*
*
+
,
=

1
tan tan
1
tan
1 1 1
f
f
fo
f
fc
f
f
f
Transfer function of the circuit is given by

Rs
R2
+
R2=1K
+
Load
R2
-
R1
R1=1K
current booster
-
Constant current
sourec for grounded
load booster
eo1
eo2
A
es
A

Voltage controlled current source for grounded loads
In instrumentation, the measurement of resistance is generally carried out
with a current source rather than a voltage source I order to eliminate the error
due to the lead resistance of the resistance probe. A constant current source
with no common mode voltage is shown in figure.

2
1
1 2
2
1
) 1 ( 1
2
2
R
R
eo eo
R
R
e es eo
R
eL
Io
Rs
eL eo
=
=
+ =
'
(
)
*
+
,
+ = 1
2 2
1
2 2 R
Rs
R
R
R
eL
R
es
Io
) 4 ( '
1 1
mA R R I e e
s r
+ =
2
/ ) ' ( R e e I
p o
=
'
'
(
)
*
*
+
,
+
'
'
(
)
*
*
+
,
= mA
R
e
R
R
I
s
s
o
4
2
1

From the above equations, eliminating eo1 and eo2, we get

The output current becomes independent of the voltage when the condition R2=R1-Rs is
fulfilled. Hence, I
o
=e
s
/R
s

The output resistance of the current source can be adjusted to infinity by slightly varying
R2. When larger output current is needed, a current booster (example LH002C) may be
used. As shown in figure.

Voltage to current transmitter
Current transmitter are ideal for a variety of applications (like Temp. transmitter) requiring
high noise immunity current mode signal transmission. The most straight forward circuit is
shown in figure.
In the voltage to current converter, the operational O1 forces its input voltage e
s
across the
resistor Rs. Neglecting the transistor base current error, the load current becomes

Is=es/Rs

The input voltage to current converter is

The operational amplifier O2 controls the output current by causing the resistor R2 voltage
to equal the difference between the supply voltage and the input voltage.
The current through the load will be

or

[ ]
'
'
(
)
*
*
+
,
+ + + +
'
'
(
)
*
*
+
,
+ =
6
5
3 3 6 5 2 1 1 2
6
5
2
1 ) // )( ( ) ( 1
R
R
e R I e R R I I e e
R
R
e
D OFF os OFF OFF os os o
5 6
6
3 4
4
2 1
1
, ,
,
1
) 1 )( 1 (
) 1 )( 1 ( 5 . 0
log 20
mod
lg
R R
R
R R
R
R R
R
CMRR
CMRR
where
CMRR
oras
egain common
ain a Differenti
CMRR
p n
OP
OP
n p
n p
IA
IA
+
=
+
=
+
=
+
=
'
'
(
)
*
*
+
,
+ +
+ +
=
=

Chapter-4
Instrumentation amplifier

Instrumentation amplifiers are commonly used for separating low level differential signals
from high common mode noise. They have the following important characteristics.
. Very high input impedance
. High CMRR
. wide range of gain set by a single external resistor
. wide bandwidth
. less settling time
These amplifiers are widely used in conditioning strain gauge bridges, Thermocouples,
current shunts and biological probes.
The most popular configuration for instrumentation amplifier using operational amplifier is
shown in figure 1.
The transfer function of the instrumentation amplifier is

1

Where (R6+2R5)/R6 is the differential gain and e
D
the differential signal. In the above
equation the DC error terms are dominated by the input offset voltages. In the
configuration shown in figure 1, common mode rejection depends on matching of R1, R2,
R3 and R4. the common mode rejection ration of the instrumentation amplifier is given by

and CMRR
op
the common mode rejection ration of the operational amplifier.

Example 1: A type 741C operational amplifier has the following specifications
Input offset voltage drift = 1.8nV/C
Input offset current drift = 50pA/C
5

Compute the DC errors with offset adjustment of the instrumentation amplifier shown in
figure above over the temperature range from 0 to 50C. The differential input signal
e
D
/2=5mV and the common mode signal e
cm
=10VDC. Calculate n bit accuracy for the full
mV V V
e e
gain SVRR 75 . 0
2
) 985 . 14 ( 015 . 15
1000 / 50
2
) (
=

=

+
mV e
ng Substituti
e e
cms
n
n p
cm cms
8 . 3
001998 . 0 , 10000141
) 1 )( 1 (
=
= =
+ +
=

999E
-
139.890K
+
+
O3
eo
139.890K
1001E
-
R4
R2
R3
1000E
-
R5
R6
+
O1
R5
e2=ecm+eD/2
280E
R1
Instrumentation Amplifier Using Three Op-amps
e1=ecm-eD/2
999E
O2
scale output voltage of 10VDC. The resistors values are R1=1001, R2=R3=999,
R4=1000, R5=139860 and R6=280.
.

DC error (with offset zero and power supply voltage tolerance of 1%).
(1) offset voltage drift over temperature
e
drift
=e
os3
-I
OFF3
R=2.41V
(2) supply voltage variation error

SVRR=10
-86/20
=50V/V

3) Error due to common mode

1
) 2 log(
55 . 4
10000
log
1
) 2 log(
log

'
(
)
*
+
,
=
Error
olatge FullscaleV
n
-
O3
10K
R3
280E
R2
R1
+
R4
O2
Figure 2
+
+
-
1000E
O4
Instrumentation Amplifier for DC
application
139.890K
e2=ecm+eD/2
-15V
-
-
R5
+
e1=ecm-eD/2
R5
1001E
eo
139.890K
999 E
+15V
999E
R6
O1
4) Gain error

10V-5mV*1.99999*498.88*1.9984278=30.34mV
The gain errors may be reduced to zero by connecting 277K parallel to R6. that is,
=0.001996
then e
o
=10V. Hence gain error=0.
n-bit accuracy may be calculated as follows:

n=11 bits

Hence we can interface this amplifier with an 11bit ADC.
Common mode rejection ration of the amplifier

CMRR
IA
=20log(496.00669*1320.5959)=116dB.
It is important to note that the CMRR of the instrumentation amplifier increases with
gain. Figure 2 shows the circuit configuration with the value of all the components.

( )
2
1
1
2
1
2 2
'
'
(
)
*
*
+
,
+
+ '
(
)
*
+
,
+
=
DC c
clo
clo D
D
amplitude
A f
fA
A e
e
e

2
10
1 log 20 ) 0 ( ) ( '
(
)
*
+
,
+ = =
Hz
f
f SVRR f SVRR
B
20 / 66
10
dB
peak to mvpeak e
weget
p n
mV e
ng Substituti
e e
cms
cms
n
n p
cm cms
=
= =
=
= =
+ +
=
71 . 1
500025 . 0 , 50005 . 0
8 . 3
8 . 001996 . 0 , 00002 . 1
) 1 )( 1 (

Example 2. A type OP27 amplifier has the following parameters:
Input noise voltage e
na
=3nV/Hz. Voltage noise corner frequency f
cc
=27Hz.
Input noise current Ina=0.4pA/Hz. Current noise corner frequency f
ci
=140Hz.The
5

Compute the AC errors in the frequency band from 1hz o 100hz for the instrumentation
amplifier shown in figure. Calculate n bit accuracy for the full scale output voltage of
10Vpeak peak AC. The resistors values are R=1000, R5=139860 and R6=280.

Solution:

Error due to bandwidth

Where =0.0019968 (at f=0), fc=10Hz, =1.00002, A
clo
= 500.49 and e
D
=10mV peak to
peak. We get e amplitude=0 at f=0 and e
amplitude
=0.2mV at f=100Hz.

Error due to power supply ripple.

SVRR(100Hz) = 86dB-20dB = 66dB or

= 0.5mV/V
e
sup=
RR * A
clo
* (Power supply ripple)

=0.5mV*100*10mV
= 0.5V Peak to Peak
Error due to common mode signal
Chossing the value so resistors The resistors values are R1=1000, R2=R3=999.9,
R4=1000.

1
) 2 log(
712 . 1
10000
log
1
) 2 log(
log

'
(
)
*
+
,
=
Error
olatge FullscaleV
n
1K
280E
e1=ecm-eD/2
R5
O2
Instrumentation Amplifier for AC
application
-
1K
R3
O3
-
1K R1
-
Figure 3
1000E
R2
R5
139.890K
-
+
eo
+
R4
R6
O1
+
O4
+
270K/390K
e2=ecm+eD/2
139.890K
C
3. Noise calculation

Bandwidth f
B
=f
H
-f
L

= 99Hz
eno=0.492mV peak-to-peak

The n-bit accuracy may be calculated as follows:

n=11.5 bits or 12 bits

es
1mA
R
Voltage to Frequency converter
+
Figure 1
Monostable
-
O1
SW
+
e-
-
comperator
e+
C
-
'
(
)
*
+
,
=
=
ON
t
ON
R R
t
C
I I
dt
C
I I
eo
0
-
= . =
1
0
1
0
t
s s
o
t
RC
e
eo dt
RC
e
e
R ON
s R ON
ON
ON R
I Rt
e
f
I
I t
T
t
t t
I
I
= . = .
+
=
1

Voltage to frequency converters

In the voltage to frequency converters analog input voltages can be converted to a
proportional frequency. the block schematic of the voltage to frequency converter based on
charge balancing circuit technique is shown in the figure1. The operation of the circuit is as
follows.

During the charging period, the integrator charges for a fixed period t
ON
which is set by the
mono-shot. The output of the integrator is given by

During discharge period, the integrator output voltage cross zero triggers a one shot.
Hence,

equating the above equations, we get

ON
ON
T
t
Voltage to Frequency conversion waveform
Figure 2
t
1
t
ON
T
t
( )
.
1
1
jw wheres
RCs T
t R I
eo
ON R
= '
(
)
*
+
,
+
=
( )
s ON R
f t R I eo =

example: if R=40K, I
R
=1mA and t
ON
=25sec then for e
s
=10V the frequency output
f=10KHz.

Frequency to Voltage converters
For F to V, the same circuit and components of V to F converter may be used as shown in
the figure 3.
The one shot is activated by the TTL input logic(fs) and it switches 1mA current sink into
the integrator input for a measured time period t
ON
. The integrator acts as a first order low
pass filter for the current waveforms. The filtered output is directly proportional to the
frequency.

Choosing the 3dB cutoff frequency of the filter 1/2RC then

+
e-
Figure 3
+15V
SW
C
fs
O1
eo
-
2.2K
e+
R
Monostable
12K
1nF
1mA
-
+
comperator
Frequency to Voltage converter

Chapter-5
ACTIVE FILTERS

Active filters are used in data acquisition systems for two reasons: 1)
To limit the bandwidth of the processed signal to less than half the sampling
frequency in order to eliminate frequency aliasing and 2) To reduce
electrically generated noise in the system.

Active filters are frequency selective amplifiers used either to pass or
reject selected bands of frequencies. The most common and basic types of
filters are low pass (LP), high pass (HP), band pass (BP) and band rejection
(BR).

These filters are very popular due to their advantages over passive
filters, which are as follows:

1. No inductors
2. High input and low output impedance providing easy of coupling.
3. Control of gain
4. Easy to tune
5. Small size and weight
6. Less shielding problems.

Active filters have the following disadvantages compared with the
passive filters.

1. Require a power supply.
2. Inject more noise
3. Lower Q-factor
4. Signal level limitations
5. Sensitivity to temperature
6. Efficiency decreases as frequency increases(limited frequency
range)

The most commonly used response is Butterworth. The Butterworth low pass
filters have an amplitude frequency response. This is flat in the pass band and
drops sharply just before the cutoff frequency. Their step response shows a
considerable overshoot. This increases for higher order filters.


BUTTERWORTH LOW PASS FILTERS

The transfer function of a low pass filter has the general form

A(S) = A
0_____________ (
1(1))..

1+C
1
S+C
2
S
2
+. +C
n
S
n

Where C
1
, C
2
,..C
n
are constants (positive and real). The order of the filter is
equal to the highest power of S (= jW/Wc). It is advantageous for the
realization of filters if the denominator polynomial is written in factored from.

A(S) = A
0
______________ (2)
(1+a
1
S+b
1
S
2
)(1+a
2
S+b
2
S
2
)

Where a
i
and b
i
are constants (positive and real).
The coefficient a
i
and b
i
in equation (2) are

determined as follows:

For even order n:

a
i
= 2 cos [ P(2i -1) / 2n] for i = 1 to n
2
b
i
= 1

For odd order n:

a1 = 1
b1 = 0
And

a
i
= 2 cos [ P(i -1) / n ], for i = 2 to n+1
2
b
i
= 1

The coefficients of the Butterworth polynomials up to the order 10 are shown
in the Table 1 and Table 2.

Table 1 factor of Butterworth polynomials_________________________
Butterworth polynomial

n
1 s + 1
2 s
2
+ 1.41421356s + 1
3 (s + 1) (s
2
+ s + 1)
4 (s
2
+ 0.76536686s + 1)) (s
2
+ 1.84775907s + 1)
5 (s + 1) (s
2
+ 0.61803399s + 1) (s
2
+ 1.61803399s + 1)
6 (s
2
+ 0.51763809s + 1) (s
2
+ 1.41421356 s + 1) (s
2
+1.93185165s + 1)
7 (s + 1) (s
2
+0.44504187s + 1) (s
2
+1.24697960s + 1)
(s
2
+1.80193774s + 1)
8 (s
2
+0.39018064s + 1) (s
2
+1.11114047s + 1) (s
2
+1.66293922s + 1)
(s
2
+1.96157056 s + 1)
9 (s + 1) (s
2
+0.34729636 s + 1) (s
2
+ s + 1) (s
2
+ 1.53208889s + 1)
(s
2
+ 1.78201305s + 1)
10 (s
2
+0.31286893s + 1) (s
2
+0.90798100 s + 1) (s
2
+1.41421356 s + 1)
(s
2
+1.78201305s + 1) (s
2
+1.97537668s + 1)

Table 2 coefficients of the Butterworth polynomial
q(s) = s
n
+ a
n-1
s
n-1
++ a
1
s + 1

n a1 a2 a3 a4 a5 a6 a7 a8 a9
2 1.41421356
3 2.00000000 2.00000000
4 2.61312593 3.41421356 2.61312593
5 3.23606798 5.23606798 5.23606798 3.23606798
6 3.86370331 7.46410162 9.14162017 7.46410162 3.86370331
7 4.49395921 10.09783468 14.59179389 14.59179389 10.09783468 4.49395921
8 5.12583090 13.13707118 21.84615097 25.68835593 21.84615097 13.13707118 5.12583090
9 5.75877048 16.58171874 31.16343748 41.98638573 41.98638573 31.16343748 16.58171874 5.75877048
6.39245322 20.43172909 42.80206107 64.88239627 74.23342926 64.88239627 42.80206107 20.43172909 6.39245322

ACTIVE SECOND ORDER LOW PASS FILTER

According to equation (2). The transfer function of second order low pass
filter has the general from,

A(S) = A
LPF
___ (3)
1+a
1
S+b
1
S
2

= A
LPF
___
1+ 2S+S
2

R5
R4
e1
eS
0
Figure 1:
Sallen-Key
Configuration
e0/G
+
-
U1
3
2
6
C4
e0
R1 R3
C2
0

Active low pass filters can be designed using operational amplifiers with
positive feedback. The gain of the amplifier must be fixed by the internal
negative feedback in the configuration shown in figure 1. The positive
feedback is caused by capacitor C
2
.

Apply Kirchhoffs current law (KCL) to the network and obtain

(e
s
e
1
) = (e
1
e
0
)C
2
s + (e
1
- e
0
/ G) (4)
R
1
R
3

(e
1
e
0
/G) = e
0
C
4
s (5)
R
3
G

Where s = jw and the closed loop gain G = (R
5
+ R
4
) / R
4.
From equation (4)
and (5), the transfer function becomes

e
0
= G______________________ (6)
e
s
1 + s ( R
3
C
4
+ R
1
C
2
- R
1
C
2
G + R
1
C
4
) + s
2
R
1
R
3
C
2
C
4

Substituting s = sWc

in equation (6), we get

e
0
= G______________________ (7)
e
s
1 + sWc ( R
3
C
4
+ R
1
C
2
- R
1
C
2
G + R
1
C
4
) + s
2
Wc
2
R
1
R
3
C
2
C
4

Comparing the coefficients of equation (7) with those of equation (3) gives

A
LPF
= G = (R
5
+ R
4
) / R
4
(8)
a
1
= Wc ( R
3
C
4
+ R
1
C
2
- R
1
C
2
G + R
1
C
4
) (9)
b
1
= Wc
2
R
1
R
3
C
2
C
4
(10)

Solving equation (8), (9), and (10), we arrive at the design equations
_____________________
R
3
= a
1
+ a
1
2
4b
1
(1 G + C
4
/ C
2
) (11)
2WcC
4

R1 = ________2b1_____________________ (12)
C
2
W
c
[a
1
+ a
1
2
4b
1
(1 G + C
4
/ C
2
) ]

A
LPF
= G = (R
5
+ R
4
) / R
4
(13)

EXAMPLE 1:

Design a Butterworth low pass filter using Sallen-key configuration. The filter
must meet the following specifications: the stop band attenuation A
min
= 54
dB. The pass band attenuation A
max
= 3 dB. The pass band frequency where
attenuation is A
max
. f
c
= 10 KHz. The stop band frequency f
s
= 20 KHz.
overall gain of the filter = unity.

Solution :
1. Determine the order of the filter

n = log {10
(Amin / 10) -1
/ 10
(Amax / 10) -1
}
2 log { f
s
/ f
c
}
Order of the filter n = 9
In order to satisfy the low pass filter stop band specification a 9
th
order filter is
required.


2. Get the Butterworth polynomials from table 1.

A(S) = 1_______________________
(1+S) (1+a
1
S+S
2
) (1+a
2
S+S
2
) (1+a
3
S+S
2
) (1+a
4
S+S
2
)
Where
a
1
= 0.34729636
a
2
= 1
a
3
= 1.53208839
a
4
= 1.87938524 and S = jW/Wc

3. Plot the poles and zeros of the filters

S
1
= -1
S
2
= -0.17365 + j0.9548
S
3
= -0.5 + j0.866
S
4
= -0.766 + j0.6428
S
5
= -0.9397 + j0.342


Figure: 2 Pole-Zero Diagrams

4. Compute the 3-dB cutoff frequency of the overall filter

f
c
= f
s
______________ = 10KHz
{10
(Amin / 10) -1
/ 10
(Amax / 10) -1
}
1/2n

5. Get the 3-dB cutoff frequencies of the individual filter stages
___________________________

=
{- (a
i
2
- 2

) +

(a
i
2
- 2

) + 4 } / 2
1
st
stage = f
c
=10.00 Hz
2
nd
stage =
1
f
c
= 15205 Hz
3
rd
stage =
2
f
c
= 12720 Hz
4
th
stage =
3
f
c
= 9172 Hz
5
th
stage =
4
f
c
= 7026 Hz

6. Get the pole pair quality factor Qi, of the individual filter stages.
__
Qi = b
i
for i = 1, 2, 3.
a
i

1
st
stage = Q
0
= 1
2
nd
stage = Q
1
= 2.879
3
rd
stage = Q
2
= 1.000
4
th
stage = Q
3
= 0.6527
5
th
stage = Q
4
= 0.5321

7. Plot the magnitude and phase response of the filter (figure 3)

Figure 3 Amplitude and phase response of the 9
th
order Butterworth low
. pass filter.
8. Get the 1
st
and 2
nd
order filter configurations

A
LPF
= 1
__________
R
3
= a
i
+ a
i
2
4 C
4
/C
2

2 f
c
C
4

R
1
= 1_____________ where i = 1,2,3,4.
f
c
C
2
{a
i
+ a
i
2
4 C
4
/C
2
}

9. Choose high quality capacitors (Example : Polycarbonate or Teflon)

1
st
stage C
6
= 1.5 nF
2
nd
stage C
2
= 47 nF & C
4
= 1nF
3
rd
stage C
2
= 4.7 nF & C
4
= 1nF
4
th
stage C
2
= 2.2 nF & C
4
= 1nF
5
th
stage C
2
= 1.5 nF & C
4
= 1nF

10. Get the values of resistors

1
st
stage R
5
= 10.61 K
2
nd
stage R
3
= 8.5265 K & R
1
= 1.2642 K
3
rd
stage R
3
= 22.058 K & R
1
= 4.8866 K
4
th
stage R
3
= 35.961 K & R
1
= 6.4035 K
5
th
stage R
3
= 44.717 K & R
1
= 23.728 K

For good stability choose metal film resistors.

11. Choose the opamp and check the slew rate

Opamp OP 27 has a slew rate of 2.8 v/ sec. and a unity gain
bandwidth of 8MHz. for 10V peak AC the operating frequency is
45KHz. hence, Opamp OP 27 has been selected for this filter.

12. Draw the circuit diagram of the 9
th
order Butterworth low pass filter
with the values of all the components.
C2
R3
C4
eS
0
Second order
R1
e0 +
-
U1
3
2
6

eS
First order
e0
C6
+
-
U1
3
2
6
0
R5


Active high pass filters (HPF)

High pass filter characteristics can be derived from corresponding low
pass filter transfer function through replacement of S by 1/S. a 2
nd
order
high pass filter transfer function is described by

A(S) = ___A
HPF
S
2
/ b
1_____
(14)
1 + a
1
S + 1 S
2

b
1
b
1
Now, the equation (14) can be implemented by using Sallen-Key
configuration.

Active second order HPF
If the resistors (R
1
, R3) and capacitors (C
2
, C4) are interchanged in the low
pass filter circuit (figure 1), then the circuit becomes HPF (figure 4)

R5
+
-
U1
3
2
6
C3
0
R6
e0
C1
eS
Figure 4:
Sallen-Key
Configuration
0
R4
R2

The transfer function of the circuit is given by

e
0
= GR
2
R
4
C
1
C
3
s
2
______________________ (15)
e
s
1 + s (R
2
C
1
+ R
4
C
3
+ C
3
R
2
- GR
4
C
3
) + R
2
R
4
C
1
C
3
s
2

Where G = ( R
5
+ R
6
) / R
5
and s = jW, substituting s = SWc in equation
(15) we get

e
0
= GR
2
R
4
C
1
C
3
s
2
Wc
2
______________________ (16)
e
s
1 +sWc (R
2
C
1
+ R
4
C
3
+ C
3
R
2
- GR
4
C
3
) +R
2
R
4
C
1
C
3
s
2
Wc
2

comparing the coefficients of equation (16) with those of equation (14)
gives

A
HPF
S
2
= GR
2
R
4
C
1
C
3
s
2
Wc
2
(17)
b
1
a
1
= Wc (R
2
C
1
+ R
4
C
3
+ C
3
R
2
- GR
4
C
3
) (18)
b
1

1 = R
2
R
4
C
1
C
3
Wc
2
(19)

b
1

Solving equation (17), (18) and (19), we get
________________________
R
2
= a
1
+ a
1
1 [4b
1
( C
1
+C
3
)(1-G)] / C
1
a
1
2
(20)
2b
1
(C
1
+ C
3
) Wc

R
4
= 2(C
1
+C
3
)__________________________ (21)
WcC
1
C
3
{a
1
+ a
1
1 [4b
1
( C
1
+C
3
) (1-G)] / C
1
a
1
2
}

EXAMPLE 2:

Design a 4
th
order Butterworth high pass filter using the Sallen-key
configuration. The filter must meet the following specifications: gain of
the filter A
HPF

= 1 and 3dB cut off frequency f
c
= 668 Hz.

1. Get the Butterworth polynomials from the Table 1.

A(S) = A
LPF
____________
(1+a
1
S+S
2
) (1+a
2
S+S
2
)
Where a
1
= 0.76536686, a
2
= 1.84775907

2. Substituting S = 1/S, obtain the Butterworth polynomials for HPF.

A(S) = A
HPF
S
4
_________
(1+a
1
S+S
2
) (1+a
2
S+S
2
)
3. Get the 2
nd
order HPF circuit.

R4
eS
R2
C3
e0
C1
+
-
U1
3
2
6
0

4. Choose capacitors C
1
= C
3
= 0.1 F

5. For unity gain A
HPF
= 1 and G = 1
R
4
= 2 and R
2
= a
1
____
a
1
CWc 2CWc

6. Get the values of resistors
1
st
Stage R
4
= 6226, R
2
= 912
2
nd
Stage R
4
= 2597, R
2
= 2201

7. Choose opamp : OP-27

8. Draw the circuit diagram of the 4
th
order Butterworth HPF with the
values of all the components.

2 2
4 3
2
4 3
1
3
1 s C R R Cs
R
R R
R
R
e
e
s
o
+ +
=
5V
-15V
-4.4V
TTL INPUT
5K
5V
-5V
5K
2N2222A
-
2N2222A
2N2907
1N4148
10K
1N4148
+
10K
A
1K
1N4148
3K

Chapter-6
Current switch

Assignment 7

Using the configuration shown in the figure1, design a unity gain second order Butterworth
low-pass filter with -3dB cut off frequency of 280 Hz.

A
R3
A
+
-
+
R4
R6
R1
C
-
-
eo
Tow - Thomas Circuit
+
R2
R5
es
C
A

C3
0.1uF
es
C3
0.1uF
R
4
2579 E
R
4
-
A
eo
R
2
712 E
+
2201 E
-
C1
0.1uF
+
A
C1
0.1uF
6226 E
R
2
Band pass Filter

2
1
) (
S
Q
S
A
S A
F
S
BPF
+ +
=

Plot the magnitude and phase response of the filter

Figure 5 Amplitude and Phase response of the 4
th
order Butterworth high pass
filter

Active Band Pass Filter

Band pass characteristics can be derived from low pass filter transfer function
through replacement of S by Q(S
2
+1)/S. Therefore, the transfer function of
the second order BPF is

22

Where

Q= f
C
/f
B
f
C
the center frequency of the filter and f
B
= (f
H
-f
L
) the
bandwidth of the filter. The frequency response of the magnitude and phase
are shown in figure 6 for Q=10 and A
BPF
=1

s
R R
C C R R
s
R R
C C R R R
s
R R
C R R
e
e
s
o
3 1
) 5 4 ( 3 1
3 1
5 4 3 2 1
1
3 1
5 3 2
2
+
+
+
+
+
+
=
CWcS
R R
C R R
S C Wc
R R
R R R
WcS
R R
C R R
e
e
s
o
3 1
3 1 2
3 1
3 2 1
1
3 1
5 3 2
2 2 2
+
+
+
+
+
=
3 2 1
3 1
2
1
R R R
R R
C
f
c
+
=
1 2
2
R
R
A
BPF
=
C R f Q
c 2
=
C f
Q
R
c
=
2
BPF c
CA f
Q
R
2
1
=
) 2 ( 2
2
3
BPF c
A Q C f
Q
R
Second Order Band Pass Filter

The multiple feedback band pass filter circuit is sown in figure 7

23

Substituting s=SWc and C4=C5=C in equation (23) we have

24

Comparing of coefficients of equation, (24) with those of equation (22), we
get the following equations.

25

26

27

From equation (27) the bandwidth of the filter f
B
=1/R
2
C which is
independent of R
1
and R
2.
Solving equations (25), (26) and (27) gives the
following relations.

C4
R
2
R1
-
C5
eo
A
Fried Circuit
+
R
3
es
-
R
3
68K
A
34K
R1
C5
0.1uF
+
R
2
170 E
eo
es
C4
0.1uF
Example 3: Design a Second order Butterworth BPF using the FRIED circuit.
The filter must meet the following specifications. Center Frequency of the
filter f
C
=312Hz, Q=10 and the gain of the filter A
BPF
=1

Solution: Choose capacitors C
4
=C
5
=C= 0.1F. The computed values of
resistors are

R
2
= 68K
R
1
=34K OR 68K//68K
R
3
=170

2
2
1
) 1 (
) (
S
Q
S
S A
S A
BRF
+ +
+
=
2 2 2
3
4
2 2 2
1
2
1
1
s C R RCs
R
R
s C R
R
R
e
e
in
o
+ +
+
'
'
(
)
*
*
+
,
=
2 2 2 2
3
4
2 2 2 2
1
2
1
) 1 (
c
c
in
o
W S C R RCSWc
R
R
W S C R
R
R
e
e
+ +
+
'
'
(
)
*
*
+
,
=
RC
f
c
2
1
=
1
2
R
R
A
BRF
=
4 2
/ R R Q =

Active Band Rejection Filter

Band stop characteristics can be derived from low pass filter transfer function
through replacement of S by S/Q(S
2
+1). Therefore, the transfer function of
the second order BRF is

28

Where

Q= f
C
/f
B
f
C
the center frequency of the filter and f
B
= (f
H
-f
L
) the
bandwidth of the filter. The frequency response of the magnitude and phase
are shown in figure 8 for Q=10 and A
BPF
=1

Second Order Band Reject Filter
Figure 9 shows the circuit connection for BRF. Its transfer function is found
to be

29

Substituting s=SWc in equation (29)

30

Comparing of coefficients of equation, (30) with those of equation (28), we
get the following equations.

31
32

33

Example 4: Design a Second order Butterworth BRF using configuration
shown in figure. The filter must meet the following specifications. Center
Frequency of the filter f
C
=50Hz, Bandwidth of the filter f
B
=6Hz and the gain
of the filter A
BRF
=1
U4
R
4
R4
U2
R2
+
HP
R1
U3
-
R
2
R
BP
-
-
LP
+
es
C
+
eo
R
+
R3
BR
-
Universal Active low pass filter
C
U1
Solution: Choose capacitors C= 0.2F. For A
BRF
=1, R
1
=R
2
=10K
Q factor= f
C
/f
B
=25/3. From equation 33 we have
R
4
= 3.3K
R
3
=27K
and R= 27K//27K

R1
34K
R
2
D1
LM336
+
sine wave
-
+
O2
741
R
3
C5
0.1uF
-
Square Wave
R1
C4
0.1uF
12K
Open
Collector
+15V
10K
68K
O1

LM311
170 E
sine wave
BPF
COMPARATOR

Precision AC Source
Generation of low frequency sine wave for applications like strain gauge instrumentation
system is much easier to use an analog comparing circuit and a band pass filter. The block
diagram of such a circuit is shown in figure 1.

Fig. Block diagram of sine wave generator

The basis of a sine wave oscillator is the series connection of an analog comparing circuit
and a band pass filter as in figure 2. The comparing circuit O
1
and the reference diode D
1

supply a constant square wave output voltage, which is subsequently filtered. The band
pass filter O
2
removes harmonics and gives out a very clean sine wave.

R1
C
+
O3
-
-
SW2
R
C1
+
O2
Figure 1: Auto Zero Amplifier
SW3
+
O1
Ro
eo
SW1
-
es
Chapter-7
Auto Zero Amplifier
Auto zero amplifier are most widely used in DC low level signal measurement. The block
schematic of these amplifiers is shown in the figure 1.

In this method the switches SW1, SW2 and SW3 are toggled at a nominal rate, which
forces the circuitry to alternate between auto zero and sampling cycle. With the switches
flipped down, the inputs of the instrumentation amplifier are shorted together and a
feedback loop closed around input stage to null its offset. SW3, R, C and O2 forms the
integrator, which stores offset value to be algebraically added to the input signal voltage
during sampling cycle. When the switches are flipped up, the circuit is forced in to the
sampling cycle. During this period the zeroed amplifier resumes amplifying differential
input signal, which SW3 then transmits to the output stage. SW3, R1 and C1 form the
sample and Hold circuit to store the amplified signal during the auto zero cycle.
In the sample mode, the output of the instrumentation amplifier
= Gain(input voltage + offset voltage) + Integrator output voltage
But in the AUTO ZERO MODE, the integrator output voltage=-Gain(Offset voltage)
Therefore, the output of the instrumentation amplifier = Gain*input voltage

S4
+
S2
Ro
OP27
-
S1
S3
es
C1
C
Figure 1: Chopper Amplifier
eo
OP27
-
R2
R3
R1
O2
Oscillator
+
O1
1.5K
1nF
Chopper amplifier

To avoid the drift problems usually associated with the DC amplifier, chopper amplifier
are often used for microvolt measurement. In a chopper amplifier the DC input voltage is
converted into an AC amplified by an AC amplifier and then convert back into a DC
voltage proportional to the original DC input signal.
The principal of operation of a chopper amplifier is illustrated in figure1 . The four
analogue switches (S2-S3) and (S1-S4) are controlled by the signal A and A* at a
frequency f
O
generated by the oscillator. these switches are used as chopper for pulsed
modulation and demodulation.

current
U1
eo
e-
Rf
-
+
Rf
Ina
Rs
Ip
Rd
erf
eo
ens
eos
Figure 2: practical I to V converter
In
-15V
Ina
-
ena
+
0 to 1.992mA
741C

Current to Voltage converter
The current to voltage converter generally used to convert the current output signal
produced by most DAC into a voltage output.

The source current Io must flow through feedback resistor Rf since no current can flow
into the operational amplifier input since the inverting input of the operational amplifier is
at virtually ground potential. The ideal output voltage is given by
e
o
=I
o
R
f
Error budget analysis of current to voltage converter.
A practical I-V converter using opamp 741 is ash own in figure2. The transfer function of
the circuit is given by

[ ]
rf ns na f na f OFF os f o
e e I R e R I e R I
A
A
eo + + + + +
+
= 2
1
mV V uV
e e
gain SVRR 015 . 0
2
) 9 . 14 ( 1 . 15
1 / 150
2
) (
=

=

+
2
1
'
'
(
)
*
*
+
,
+
=
DC c
clo
clo
f o f o
A f
fA
A
R I R I e
B
L
H
ce na clo no
f
f
f
f e A e +
'
'
(
)
*
*
+
,
= ln
1
B
L
H
ci na clo no
f
f
f
f I R R A e +
'
'
(
)
*
*
+
,
= ln ) 2 // 1 ( 2
2

Where A is the open loop gain, e
na
the input noise voltage of operational amplifier, I
na
the
input noise current of operational amplifier, e
ns
the input noise voltage of resistor Rs and e
rf

the input noise voltage of Resistor Rf.
DC error (with offset zero and power supply voltage tolerance of 1%).
(3) offset voltage drift over temperature (T=50C)=0.3mV
(4) offset current drift =-0.032mV
(5) supply voltage error

Total DC errors: 0.283mV

AC errors
1. Error due to power supply
150V/V*1*10mV=1.5mVp-p (100Hz)

2. Gain error

Where A
clo
= A
DC
/ (1+A
DC
)) A
DC
is the open loop gain of the amplifier. If A
DC
is 2*10
5

and f
C
=5Hz, then the gain error becomes 0 at f=0 and 1.25mV at f=3KHz.

3. Noise calculation

Bandwidth f
B
=f
H
-f
L

= 90Hz

e
na
=20nV/Hz, f
ce
=200Hz and f
B
=90Hz
e
no1
= 0.47VRMS

Noise current component is

I
na
=0.5pA/Hz, f
ci
=2KHz
e
no2
= 0.088VRMS

The Resistor R
s
noise component is
B S clo no
f R A e
10
3
10 28 . 1
=
f clo no
f R A e
2
10
4
10 28 . 1
=
2
4
2
3
2
2
2
1
) ( ) ( ) ( ) (
no no no no no
e e e e e + + + =
1
) 2 log(
29 . 0
2550
log
1
) 2 log(
log

'
(
)
*
+
,
=
Error
olatge FullscaleV
n
clo DC c dB
A A f f /
3
=

eno3=0.044VRMS

The Resistor R
f
noise component is

eno4=0.044VRMS

Total Noise

e
no
= 0.48Vrms or 2.88V peak to peak

Maximum operating frequency of the amplifier
f
max
=Slewrate/2e
o
f
max
= (0.5V/sec)/22.55V
f
max
= 34KHz

3-dB bandwidth of the amplifier

=1MHz
Hence, the n-bit accuracy may be calculated as follows:

n=10 bits

Chapter-8
Sample and hold circuit
A sample and hold circuit is a voltage memory device that stores a given voltage on a high
quality capacitor accurately over periods ranging from microvolts to several minutes.
These devices are widely used in analog signal processing and data conversion systems.

Figure 1 shows, a sample and hold circuit consisting of an analog switch S
1
, two (unity
gains) buffers U
1
and U
2
and hold capacitor C
H
When the switch closes (in he hold mode)
the capacitor charges to the input voltage. The voltage across the capacitor e
c
is given by

1
AC
ON H
t
R C
c s e e e
, )
=
* '
+ (
(1)

where R
ON
is the on resistance of the switch S1 and t
AC
the acquisition times. Re arranging
the equation (1) gives

ln
s
AC ON H
s c
e
t R C
e e
, )
=
* '
+ (

To charge the capacitor to 99% of the input voltage ,the required time or the acquisition
time t
AC
=6.9 R
ON
C
H
, when the switch opens in the hold mode the capacitor retains the
charged voltage eC and thus holds the desired voltage for a specified period . the output
voltage eo is given by
1 ( )
H
C H
t
R R C
o c e e e
=
P
(2)

where R1 is the input resistance of the operational amplifier and Rc the capacitor leakage
resistance (mega ohm microfarad).
From equation (2) we have
1 ( ) ln
c
H c H
o
e
t R R C
e
, )
=
* '
+ (
P

the self-discharge time constant ( the length of time required for an open-circuited
capacitor to discharge to 36.8% of its charged voltage) becomes

t
H
=(R
1
||R
C
)C
H
(3)

Example 1: determine the acquisition time to 0.1% full scale or a 10V step input with CH
=10nF and TON=300.
Solution:
t
AC
=6.9R
ON
C
H
=20.7 sec.

Example 2: assuming the following specifications determine the self-discharge time
constant of the capacitor C
H.
Input resistance of the operational amplifier U2 (CA3140),R
1
=1.5
Hold capacitance C
H
=0.01 F(poly carbonate)
Leakage resistance of the capacitor =10
10
- F.
Solution :
Using equation (3) we get t
H
=6000secs. With 741 operational amplifiers ,tH becomes
4seconds. Therefore , the U2 must be a FET input operation amplifier.

Important S/H characteristics

Acquisition time : the time required for the circuit output yo become equals to the input .
the output then follows the input until the circuit is again put in the hold mode.

Drop rate : the rate of of change in output voltage with time while in the hold mode.
Droop rate typically varies from 1mV to 5mV per second.

Pedestal error : charge injection is the phenomenon of moving small amount of charge
from the main signal path switch to or from the hold capacitor during switching . the error
resulting charge transfer may be referred to as pedestal error or hold step.

Aperture time : the time delay between switching off the control voltage and the actual
cut off of the series switch . during this time the output signal may change slightly. In high-
speed applications variation in aperture time can become important .such variations is
called aperture uncertainty or aperture jitter.

It has been pointed out that operational amplifier U2 must have FET input. Employing
feedback as shown in the figure 2 can eliminate its offset voltage.

In the sample mode ,diodes D1 and D2 are off. The output of the operational amplifier U1
becomes
0 0 ( ) s os e e e A e = +
in the above equation ,A is the open loop gain of the operational amplifier U1 .if A is
infinite then e0=es.
In the hold mode , the output voltage remains constant .resistor R and diodes D1,D2
prevents operational amplifier U1 becoming saturating in this mode of operation .

figure 2: S/H circuit with feedback

Maximum allowable input frequency
A S/H amplifier stores (in the hold mode) an instantaneous voltage (sample value ) at a
desired instant time. The constant on this time is aperture uncertainty ( figure 3). The
aperture error is
s
ap ap
de
e t
dt
=
(4)
where des/dt is the input signal slew rate and tap the aperture time. any sinusoidal signal
follows the from:
es=ep sinwt

des/dt
eap
des/dt
eap
tap
The maximum rate of change of input sinusoidal signal is
max 2
s
p
de
f e
dt
=
(5)
but
1
2
n
p
ap
e
e
+
=
(6)
where n is the number of bits of desired resolution . from equation 4,5 and 6 we have
1
1
max
2 2
n
ap
f
t
+
=

for tap =1nsec and n=12 the maximum frequency that can be handled by a S/H circuit (to
within LSB) is 19.4KHz.
Software programmable gain amplifier
Gain =1,or 2,5,10,20,50,100,200.

Figure 4: software programmable gain amplifier
One of the most common uses of an analog multiplexer is to alter the gain of an amplifier.
The figure 4 shows a SPGA with gains of 1, 2,5,10,20,50,100, and 200. the gain error due
to on resistance of the switch is completely eliminated by placing the multiplexer in the
feedback path of the operational amplifier. The analog multiplexer Mux 08 provides a
make before brake operation necessary to prevent the amplifier from open loop during gain
switching.

Error= mI
D
R
ON
+2R
ON
nI
D

-
U1
+
0 to 7
0 to 7
0 to 7
n=8
8-ch
mux
2
8-ch
mux
1
8-ch
mux
8
8-ch
mux
e
0

m=8

Analog multiplexers
Analog multiplexers are used for time-sharing of analog to digital converters between a
number of different analog information channels. An analog multiplexer consists of a
group of analog switches arranged with inputs connected to the individual analog channels
and output connected in common. the switches in the multiplexer can be addressed by a
digital input code.

Single ended analog multiplexers

Figure 1 shows an n-channel single ended multiplexer with a buffer amplifier .figure 2
shows the equivalent circuit of an n-channel multiplexer, which is characterized by series
resistance RON ,shunt capacitance CD and a leakage current ID . the amplifier input bias
current (IB) is also shown in the figure
.

Where a switch S1 is closed in the multiplexer with n inputs , input to the amplifier
charges up to

e
1
R
ON
(nI
D
+I
B
)with a time constant =nC
D
R
ON

in a large low level multiplexing configuration , he error can be serious . for example , if
the leakage current ID is 100nA ,and RON = 100., and n=64 , the error voltage is
approximately 0.655mV. the time constant also becomes quite large for a large number of
inputs . suppose the capacitance of each switch is 14pF and the time constant is 0.6sec. a
4sec delay will be required to each within 0.1 % of the final value.
Analog
signals
Digital
codes
E0
n-channel
analog
mux
-

+


multiplexing employing block switching

when several channels need to be measured simply tying to gether the outputs of the
different multiplecers may not be advisable . this can cause heavy capacitance loading on
the selected channel . by using multi tire architecture as shown in figure 3 ,the
capacitance can be lowered significantly .

the input error is redused to

mI
D
R
ON
+2R
ON
(nI
D +
I
B
)

if m=n=8 then the error for the example above is redused to 0.27 mV.

The total capacitance on the output of the selected input channel is reduced to

C=C
D
(m+2n

). And the associated delay is reduced by a factor of three.

Integrating or Dual-slope analog to-digital converters

Integrating ADCs operate by the indirect method of converting a voltage to time period ,
which is then measured by a counter ./ thos type of ADCs is widely used in most digital
voltmeters(DVM) and digital panel meters (DPM) .
the converter is illusterated in the simplified figure 1 a and its timing diagram for one
conversion cycle is also shown in figure 1b. figure 1c shows the operation of ADC for the
bipolar signals.
-
U1
+
+ U2 -
R

Control
logic

counter
Figure 1 block diagram of an integrating ADC
n- bit Data
EOC
start
clock
S1 S2 S3
e
s

e
R

e
s ,
e
R
are always
opposite polarity.

S1
S2
S3
C

the conversion cycle consists of two separate integration intervals. At ,rest the switches S1
and S2 are open and S3 is closed . the integrator U1 output is zero. At start of conversion ,
the switch S3 is open and the unknown input voltage .

es=-[eDC +e
AC
(sin wt+ )] is connected to the integrator input through the switch S1 .
where e
AC
(sin wt+ ) is a DC input with an AC interference signal superimposed upon it
and is the phase angle of the interference signal at the start of the integration. The input
voltage is integrated for a fixed period of time t1 . at the end of time period t1 ,the output
of the integrator is given by

[ ]
1
01
0
1
sin( )
t
DC AC e e e wt
RC
= + +
- (1)
RC is the time constant of the integrator . the equation (1) may be simplified as

( )
1
01 1 cos( ) cos
DC AC e t e
e wt
RC wRC
= + & #
% "
(2)

at the time period t1 , the counter overflow , causing S1 to be opened and the reference
voltage er to be connected to the integrator input through the switch S2, the integrator
output decreases until it crosses zero, and the zero crossover detector U2 changes state ,
indicating the end of conversion (EOC). The integrator U1 output becomes

2
02 01
0
1
t
r e e e dt
RC
=
-
(3)

the voltage e
r
is the reference voltage. At the end of the time period t2,e02=0. hence the
equation (3) becomes

( ) ( )
2
1
Dc AC r e e e t
COS wt COS
RC wRC RC
+ = & #
% "
(4)

OR

( ) ( )
1
2 1
Dc AC r
r r
e t e e
t COS wt COS
e we RC
= + = & #
% "
(5)

where
1
sin( 1)
tan
1 cos( 1)
wt
wt
, )
=
* '
+
+ (

we can write the equation (5) as

2 1
DC
t
r
e
r error
e
= + (6)

if error is zero ,t1=n1/fc and t2=n2/fc .then equation (6) gives
2 1
DC
r
e
n n
e
= (7)
where fc = the clock frequency to the converter. If e
r
and n1 are constant then the net count
n
2
present in the counter at the end of time period t
2
is directly proportional to the input
voltage e
DC.
Normal mode line frequency rejection
The series or normal mode rejection (NMR) of the converter is given as the ratio of the
maximum error produced by the sine wave to the peak magnitude of the sine wave .from
equation (6) NMR is
10K
100K
Level
Translator
S4 S5
-

+
-

+
To the ADC
S4
S5
es
Figure 1c:for
bipolar
operation of
ADC
t1
fixed
t2
variable
voltage
time
es
Figure 1b timing diagram

1
cos( ) cos( )
AC
error wt
e wt
+
=
the NMR is generally expressed in dBs as

1
20log
cos( ) cos( )
wt
wt
& #
=
$ !
+
% "

where = 1
1
1
sin( )
tan
1 cos( )
wt
wt
& #
$ !
% "

a plot of the NMR of the integrating ADC is shown in figure2.

Chapter-9
Advantages of Integrating ADC
! Simplicity
! Relatively low cost
! High accuracy and linearity
! Excellent noise rejection
! No sample and hold required
! Non critical component
! No missing codes
! Neither the clock frequency nor the integration time influence the result
! Offers excellent differential and integral linearity

Disadvantages of ADC
! Low speed (3 to 100 reading / second)
! Requires a stable ripple free reference voltage
! If the main frequency is not constant , these ADC s require a phase locked
loop(PLL) to track the main frequency.

Integrating ADC interface

Figure 3 shows an integrating ADC interface. An integrating ADC offers a high line
frequency rejection, good resolution and linearity. This is available as an inexpensive
13-bit ADC (ICL7109) chip. In this ADC, an input voltage integration phase, a
reference integration phase and an auto-zero phase are carried out in 8192 clock
periods, serving to eliminate offset voltages and determine the magnitude and polarity
of sampled voltage.
The ADC integrates the input signal for only 2048 clock periods. To achieve high
normal-mode line frequency rejection, the integration period is made equal to the
period of the mains supply by incorporating phase locked loop (PLL) and a divide-by-
2048 counter. Hence, the clock frequency f
c
for the ADC is 2048 fs , where fs is the
frequency of the mains supply.

The stability of the reference voltage is a major factor in the overall absolute accuracy
of the ADC. An external reference voltage is employed. This has a temperature
coefficient of 2 ppm/C. A change in temperature of 35C in the environment
introduces a 0.25 bit error having REFIN and INLO at analog common minimizes the
rollover errors of ADC. The components are selected for 4.096 V full scales.

Error analysis of ICL ADC 7109

Supply voltage: 5V DC
Differential input voltage: 4V DC
Resolution: 12 bit or 1 part in 4096 (or 244ppm)
Selection of components

R
INT =
Full scale voltage
=
4V
=
200K!
20A 20A

C
INT =
2048 clock period 20A
=
20482010
-6
=
0.1F
Integrator output voltage swing 204850Hz4V

Auto-zero capacitor C
AZ
= 0.1F

Selection of reference voltage

LM399 has a reference voltage of 6.8V with a temperature coefficient of 2 ppm/C.
With the operating temperature of 0 to 50C, the reference voltage includes an error of
0.35 LSB.

The total error

1. Error due to reference : 0.35 LSB
2. Scale factor error : 0.00 LSB
3. Roll over factor : 0.1 LSB

4096e
cm
C
s =
40961010pF = 0.1
e
r
C
r
4.7F

4. Auto zero loop residuals : 0.1LSB
Total error : 0.5LSB

Therefore, the total error = LSB


Flash Analog-to-Digital Converters

The second popular technique for analog to digital conversion is flash method
(parallel or simultaneous). In this method, the entire conversion process occurs
simultaneous rather than sequentially. However, its circuit complexity and cost
increase a in geometric progression with the addition of each bit. These ADCs are
generally used in very high-speed applications viz., digital TV, transient recorder,
distortion analyzers, radar signature analyzers, video densitometry, and image
processing and high speed digital transmission.

The converter consists of 2
n
-1 high-speed comparators, a resistor network, a stable
ripple-free reference voltage and an ultra fast encoder circuit.

3- Bit Flash ADC: A 3-bit flash ADC is illustrated in figure 7. The circuit
employs seven comparators to directly implement the quantizer transfer function
of an ADC. Positive input of comparators are connected to an analog input through
a high speed buffer amplifier and inverting inputs are connected to a series of
stepped reference voltages. The upper comparator C7 turns ON at slightly higher
input signal (13e
r
/14) than the next comparator C6 a step lower on the voltage
divider (11e
r
/14).
For a given analog voltage all comparators biased below the reference voltages
turns ON (logic one state) and all those biased above it remain OFF (logic zero
state) sine all comparators change states simultaneously, the quantization process
is a one step operation.
An ultra fast thermometer decoder and encoding circuit translate the logic output
of the comparators into the most commonly used code natural binary.
Table1 shows the coding for quantizer and encoder outputs.
In the encoder, simple NAND gate perform the logic according to the following
equation:

Boolean expression:

MSB Bit C = L4L5L7L6
Bit B = L2L3L7L6
LSB Bit A = L1L3L5L7

Where L1, L2 , and L7 are the thermometer decoder outputs and bits A, B and C
are the binary outputs data.
The most critical component in the flash ADC is the analog comparator. The input
offset voltages of the comparators affect the accuracy of the converter.
The speed of the converter is limited by the delays of comparators and of the logic
network.

Advantages
Very high speed (10
6
to 10
8
conversions/ sec at 12 bit resolution)

Disadvantages
High resolution difficult to realize
High power
High hardware complexity
Expensive
Table 1: states of variables in the flash ADC

Comparator states

Thermometer decoder output

Binary number

C7 C6 C5 C4 C3 C2 C1

L7 L6 L5 L4 L3 L2 L1

C B A
0 0 0 0 0 0 0
0 0 0 0 0 0 1
0 0 0 0 0 1 1
0 0 0 0 1 1 1
0 0 0 1 1 1 1
0 0 1 1 1 1 1
0 1 1 1 1 1 1
1 1 1 1 1 1 1
1 1 1 1 1 1 1
1 1 1 1 1 1 0
1 1 1 1 1 0 1
1 1 1 1 0 1 1
1 1 1 0 1 1 1
1 1 0 1 1 1 1
1 0 1 1 1 1 1
0 1 1 1 1 1 1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1


Two stage simultaneous ADC
A limitation of the simultaneous conversion method is that the number of
comparator required increase exponentially with N, the number of bits. A 4-bit
converter for example requires only 15 comparators, but an 8-bit converter
needs 255 comparator. For this reason it is common practice to implement on
8-bit DAC with 4-bit stages as shown in figure8.
The results of the first 4-bit conversion is converted back to analog by means
of an ultra fast 4-bit DAC and then subtracted from the analog input voltages.
Second 4-bit ADC then converts the difference and the two sets of data are
accumulated in the 8-bit register. This results in a speed compromise but
higher resolution.

L7
L6
C
L5
L4

L3 B

L2

A
L1

ENCODER LOGIC
n/2
ADC
n/2
DAC
n/2
ADC

2
n/2
e
s

MSD
LSD

Pipeline ADCs
Pipeline ADCs (also called sub-ranging) consists of numerous consecutive
stages, each containing a sample and hold, a low resolution ADC and DAC,
and a summing circuit that include an inter-stage amplifier to provide gain. The
outputs of each stage are combined in the output latch. Target applications for
pipeline ADCs include communication systems, CCD-based imaging systems
and data acquisition systems.

D7
e
r
D6

e
r

2
2
Bits

in ADC

-
D5
+ D4

-
D3
+ D2

- D1
D0

+

e
s =
e
r
D
A
+ (1/4)e
r
D
B
+ (1/16)e
r
D
C
+ (1/64)e
r
D
D

2
2
2
2
2
2
2
2

D
A
,D
B
,D
C
and D
D
are varies from 0 to 3

ADC(A)
2-Bit

ADC(B)
2-Bit

ADC( C)
2-Bit

ADC(D)
2-Bit

DAC(1)
2-Bit

DAC(2)
2-Bit

DAC(3)
2-Bit

X4
X4
X4
Error budget analysis of DAC08

The DAC08E has the following specification:
Non linearity: 0.19 % FS
Full scale temperature coefficient TCI
FS
: 50 ppm/C(max)
Zero-scale current I
ZS
:2 uA (max)
Full scale current I
FS :
[510/256 0.4%]mA
Power supply sensitivity : PSS IFS and PSS I
FS
: 0.01%max.

Calibration
Suitable gain trimming arrangement is shown in figure1.

Digital Input Word

4.7 K Current Sink
e
R

e
0

10V

39 K 1.28K

1.28K
10K
Gain Trim

Figure1: DAC circuit using DAC08

Error after calibration

Gain error over temperature (25 to 70 C)
TCI
FS
(temperature difference) % = 50E-06 45100 = 0.255%
Effect of e
R
temperature coefficient
20 ppm/C 45100 = 0.09%
Error due to power supply changes = 0.002%
Linearity error over temperature = 0.01%
Total worst case error = 0.225% 0.09% 0.02%0.01% or 0.345%
The total error = 0.345% 2550mV or8.7975mv or 1 LSB

Monotonicity
As the input code to a DAC is increased, the output should increase in a
monotonic manner. If this does not happen, then the DAC is said to be non-
monotonic

+

DAC08E
- Current sink
Absolute accuracy
Absolute accuracy is the worst case difference between actual converter output
and ideal converter output

Relative accuracy
Relative accuracy is the worst case difference between actual converter output
and ideal converter output after gain and offset errors have been removed.

Settling time
When the input code of an ideal DAC changes from one binary value to
another, its output immediately jumps from the old output voltages top the new
output voltages. In a real converter, capacitance and inductance introduce time
delays into the circuitry and therefore a certain amount of time elapses before
the output reaches the new value. This is referred to as the settling time.

Glitches
The DAC input code is changed by one LSB from 1000 to 0111. This requires
turning OFF MSB and turning ON all the lower bits. If the circuitry forming
the DAC turns bits OFF faster than it does turns them ON, the DAC voltage
temporarily heads for an output corresponding to 0000. Hence, the DAC code
sequence transiently appears as 1000-0000-0111 and a glitch appears in the
output. Smoothing the output of a DAC by means of a low pass filter can
minimize the effects of glitches.

Microprocessor (and computer) interfacing to digital to-
analog converters
In order to maintain a constant output from the digital-to-analog converters, the
input data must be held constant. This requires the use of a peripheral interface
adapter between the microprocessor (and PC) and the DAC. A number of
converters now in the market includes data latches at the input and provide
address decoding circuitry to help the microprocessor (and PC) address the
DAC.

Converters with resolution higher than 8-bits require the passing of more than
one byte of data to the DAC before the output level can be changed. some form
of double buffering is required at the DAC input .a number of recently
developed converters include such buffering plus address decoding to route the
high and low bytes of data to correct latch circuitry,. A circuit diagram of this
type of DAC is shown in figure.

Chapter-10

Successive approximation ADC

The most popular technique for ADC is the successive approximation
conversion method. This ADC provides high resolution rapid conversion.
These are commonly used in
- high speed data acquisition system
- digital process control system
- automatic test system
- PCM system
- Waveform sampling and digitizing

The schematic block diagram of successive approximation ADC is shown in
the figure 4.

The converter operation as follow:
-the clock circuit controls the timing of the SAL ( successive approximation
logic )
- the start conversion signal clears the converter to zero. The SAL set the
DAC output to efs/2 and compares the analog input voltage es.
- if the comparator output is 1 ( high) , then the DAC output increments by
efs/4. if the comparator output is 0 ( low ) , the DAC output decrements by
efs/4.
- the SAL again checks the comparator output and causes the DAC output to
be increment or decrement by efs/8.
-this process continues until the LSB efs/2
n
has been tested and the final
comparison made.
- the conversion process stops at the end of n comparison for an n bit
converter.
-the binary number equivalent of the analog input voltage can then be read
from the output of the SAL of the converter.


The advantage and disadvantages of the converter may be summarized as
follows :
Advantages :
-High speed ( 10 conversions/sec ) and high resolution
Disadvantages :
-several critical components
- can have missing codes
- requires sample and hold
- difficult to auto-zero
-high cost
-requires pre filter to minimize input noise

The circuit diagram of an 8 bit successive approximation ADC is shown in
figure 5.
The ADC operation as follows:

1 the start signal ( CP0)
- Feed the clock pulse to the shift register by setting the flip-flop B0 to
state 1 (high ) .
- Set output of the SR R0 to state 1 and all other outputs R1 to R10 to
state 0 (low).
- Disables the output buffer B9.
- Reset flip-flop B1 to B8 to zero.
- the input signal to the DAC is in the state 0 ( low).

2 The second clock pulse ( CP1 )
- Changes the state of R1 to state 1
- Set the flip-flop B1 to state 1
- The input signal to the DAC is now 10000000B
- The output of the DAC is 1.28v
- The output of the comparator is in the state 0 (low).

3 The second clock pulse ( CP2 )
- Transfer the comparator state 0 to D7.
- The output of the comparator is in the state 1.

4 The third clock pulse ( CP3 )

5 The fourth clock pulse ( CP4 )

6 The fifth clock pulse ( CP5 )

7 The sixth clock pulse ( CP6 )

8 The seventh clock pulse ( CP7 )

9 The eighth clock pulse ( CP8 )
10 The ninth clock pulse ( CP9 )

11 The tenth clock pulse ( CP10 )
- Reset the flip-flop B0
- Enable the buffer B9.

The timing diagram of the ADC is shown in the figure 6.
The accuracy is determined essentially by the comparator and the DAC. The
primary factor limiting the speed of this ADC are

-settling time of the DAC
- response time of the comparator
- delays introduced by the various logic circuits.

Speed calculation

For a sinusoidal input signal represented by e
fs
sin(wt)/2 , the maximum rate
of change of voltage ( de
s
/dt)
max
is we
fs
cos(wt)/2 , Where e
fs
is peak to peak
amplitude of the input signal equal to full scale voltage of the converter. The
peak voltage of the co sinusoidal wave is maximum at t = 0. hence,

de
in
= efs "f (8)
dt

The maximum rate of change of the DAC output is one LSB per clock period.
de
DAC
= efs (9)
dt 2"tc2
n

f
max
= fc
2"n2
n

Where n is the number of bits and tc is the clock period.
Equiting (8) and (9) we get the maximum frequency that can be applied to the
ADC input.

Example : for an 8 bit converter with a 100KHz clock frequency. The
maximum frequency for a full scale input signal is 7.77Hz. for e
fs
= 10v , this
corresponds to a maximum rate of change of 0.5v/msec.


6 4
R1
R4
5
start
7
clock
8
R7
R9
0
R5
9
R10
R3
3 2
R0
10
R6
R8
output of shift register
Q0
R2
1

D6
D1
D4
D3
D7
D0
D5
D2

Timing diagram of ADC

Error analysis of ADCs
The input-output relationship for an ideal 3bit ADC is shown in figure8. As
the input increases from 0 to full-scale, the output codes stair steps from 000
to 111. The width of an ideal step represents the size of the LSB of the
converter and corresponds to an input voltage of e
fs
/2
n
for an n-bit converter.

The output codes are constant for an input voltage range equal to one LSB.
Thus, as the input voltage increases , the output codes first overestimate the
input voltage and then under estimates the input voltage. This error, the
quantization error is plotted against input voltage in figure 9. for a given
output codes , the input voltage can be anywhere within a one LSB
quantization interval. The quantization error for an actual converter ( as an
example ) is shown in figure 10.


Differential linearity error:
It is the difference between the actual code step width and one LSB.

DLE = e
n+1
-e
n
- 1LSB
(e
fs
)
2
n

where e
n
represent the transition voltage of an nth quantization level.

Integral linearity error:
It is measure of the maximum deviation of the actual transition point in ADCs
transfer characteristic from the straight line drawn between the end point (
first and last code transitions). Figure 12 plots the step size
111
DLE
1LSB
-1LSB
000
1LSB
011
ILE
001 010 100 110
step size
+1/2LSB
2LSB
101
-1LSB
figure 12: step size, DLE and ILE for the actual ADC
-1/2LSB

differential linearity error and integral linearity error for the converter of
figure 10. the step size for each output code is plotted. The differential
linearity error is the difference between the actual step size and ideal step size
of one LSB and is plotted versus output codes.
The integral linearity error for an output code of 101 equals the sum of the
differential linearity error for codes upto and including 101 : -0.5+0.5-
0.5+0+0+1 = 0.5 LSB
Offset error:
It is the amount by which the straight line through the centers of the end point
quantization levels fails to pass through zero. This error is usually specified in
volts or as a fraction of an LSB or as a percentage of full-scale.

Gain error:
It refers to the amount by which the slope of the straight line through the
transfer characteristic deviates from one. Gain error is usually specified as a
percentage of full-scale.

Power supply rejection ratio of an ADC:

The change in the converter output codes for a DC variation in the supply
voltages. The usual units of measure for PSRR are decibels (dB). As an
example an 8 bit ADC might be specified with PARR of 34dBs. PSRR
dBerror
=
2
4
/10
34/20
= 5codes.

Quantization noise
In the process of quantizating a dynamic signal the error voltage waveform is generated as
in figure 13, which represents a noise source, which corrupts the digital representation of
the input signal.

The RMS (root mean squared) amplitude of this error can be easily derived. if the error
signal is generated by a ramp input signal, a uniform distribution of code results in the
saw-tooth with a periodicity, which is designated as T. the error signal is then described by
e
C
= qt . t varies from T to + T
T 2 2
Where q is the quantization level equal to e
fs
/2
n
. The RMS value of this function can be
calculated with the following standard equations:
If a sine wave with peak-to-peak amplitude equal to the ADC full-scale voltage is used as
an input signal. Its RMS voltage would be
+ T
2
( e
C
)

2
= 1 - (qt / T )
2
dt
T - T
2
___
Or e
C
RMS

= q / 12

an input signal. Its RMS voltage be
___
e
C
RMS

= q2
n
/ 2 2

The RMS to RMS signal to noise ratio (SNR) for the ideal ADC is then given by
SNR dB 6.02n + 1.76
Where n is the number of bits in the A/D conversion code. This is the well-known
equation, which relates ideal SNR to the A/D resolution. it should be intuitive that an
increase in resolution reduces the error amplitude by a factor of two per bit. Result in an
increase in SNR of 6dB per bit.


Aperture error
Aperture error is defined as amplitude and time error of the sampled data
points. This is due to the uncertainly of the dynamics data changes during
sampling. In data converters, aperture error can be reduced are made
insignificant either by the use of a sample and hold or with a very fast ADC.
For sinusoidal input signal represented by e
fs
/2sin(wt), the maximum rate of
change of voltage

de
in
= e
fs
"f
dt

for sinusoidal data, maximum aperture error occurs at the zero crossing where
the signal slew rate occurs and is expressed mathematically as:
the f is the maximum data frequency. e
fs
the peak to peak amplitude of the
input signal to full scale voltage of the converter and t
ap
the aperture time of
the system.

Aperture error = de
in
t
ap

dt

or aperture error = "fe fs t
ap

the t
ap
may be the conversion time of the ADC with no sample and hold or the
aperture time of a S/H if one is used in front of an ADC.
If the aperture error is set to 1/2LSB . 1/2LSB = (e
fs
/2)2
n+1
, where n is the
number of bits of desired resolution). Then the maximum full scale sine wave
frequency that produces is

fmax = 1
2" t
ap
2
n+1

for t
conv
= 2sec and n = 12, the maximum frequency that can be handled by
an ADC is

fmax = 1
2" t
conv
2
n+1

ADCs with a conversion time of 2sec are expensive when compared to low
speed ADCs with a low aperture sample and hold . for t
conv
= 25sec , tap =
50nsec , tac = 10sec and n=12 , the maximum frequency that can be handled
by a converter is

fmax = 1 = 14KHz
2(t
conv
+ t
ap
+ t
ac
)

Alias error

Digital data acquisition system contain an ADC that converts an analog
signal to a digital signal at a specified sampling rate. This sampling rate is
extremely important in dynamic measurements where high frequency analog
signals are being processed. From the nyquist sampling theorem, a minimum
of two samples per cycle of the bandwidth is required in an ideal sampled
data with no loss of information. If the frequency of the analog signal is
greater than half the sampling frequency, the sampling process is inadequate
and the output from the ADC gives a false low frequency waveform, called an
alias , that differ from the true analog signal.
Commercial digital instruments avoid the aliasing by using antialiasing
analog filters to reduce the high frequency component in the analog in the
analog signals.

Quantization noise
In the process of quantizating a dynamic signal the error voltage waveform is generated as
in figure 13, which represents a noise source, which corrupts the digital representation of
the input signal.

The RMS (root mean squared) amplitude of this error can be easily derived. if the error
signal is generated by a ramp input signal, a uniform distribution of code results in the
saw-tooth with a periodicity, which is designated as T. the error signal is then described by
e
C
= qt . t varies from T to + T
T 2 2
Where q is the quantization level equal to e
fs
/2
n
. The RMS value of this function can be
calculated with the following standard equations:
an input signal. Its RMS voltage would be
+ T
2
( e
C
)

2
= 1 - (qt / T )
2
dt
T - T
2
___
Or e
C
RMS

= q / 12

an input signal. Its RMS voltage be
___
e
C
RMS

= q2
n
/ 2 2

The RMS to RMS signal to noise ratio (SNR) for the ideal ADC is then given by
SNR dB 6.02n + 1.76
Where n is the number of bits in the A/D conversion code. This is the well-known
equation, which relates ideal SNR to the A/D resolution. it should be intuitive that an
increase in resolution reduces the error amplitude by a factor of two per bit. Result in an
increase in SNR of 6dB per bit.

Chapter-11
Data acquisition systems
Electronic systems, which are used to process analog signals and convert them into digital
form, are referred to as data acquisition systems (DAS). Multi-channel data acquisition
systems perform the task of processing several analog input signals. The systems output is
a time shared between the various input channels in a manner, which is controlled by the
system.
The operation of switching several input signals one at a time to a single output channel is
called multiplexing. In data acquisition systems multiplexer operation is performed
automatically under the control of digital logic signals. Figure 1 shows the
interconnections between some of the functional components might be included in a
typical data acquisition system (DAS).
In the figure 1, the sample and hold and ADC are time shared between the analog channels.
The ADC converts an analog sample value that held by the S/H in the hold mode into
digital form. The programmable gain amplifier (PGA) can also be instructed to select the
gain of the amplifier. When a conversion is completed the S/H is switched to the sample
mode for a time, which is long enough for it to acquire the next channel value. It is then
returned to the hold mode and the sequence is repeated.
The multiplexer may be instructed to select analog channels in sequence or in a random
access mode. Selection of a particular in put channel is performed by a binary-coded
digital word, which is applied to the multiplexer by the digital control circuitry.

System throughput rate

The throughput rate of the DAS is determined by the settling times required in the analog
multiplexer and PGA, S/H acquisition time and ADC settling and conversion time. The
channel maximum throughput rate is

1
2[t
smax
+t
spga
+t
ap
+t
ac
+t
conv
]

Where t
smax
is the settling time of the multiplexer, t
spga
the settling time of the PGA, tap the
aperture time of the S/H, t
ac
the acquisition time of the S/H and t
conv
the conversion time of
the ADC.

Example:

substituting, t
smax
=1.5usec, t
spga
=2.8usec, t
ap
=30nsec and t
conv
=6usec in the above equation,
we get the maximum throughput rate of 37.5 KHz.

System throughput accuracy

The most common method used to describe data acquisition and conversion system
accuracy is to compute the root sum squared (RSS) errors of the system components. The
RSS error is statistical value, which is equivalent to the standard deviation and represents
the square root of the sum of the squares of the peak errors of each system component,
including ADC quantization

e
RSS
= [ (e
mux
)
2
+(e
pga
)
2
+(e
s/h
)
2
+(e
ADC
)
2
]
1/2


Where e
mux
is the analog multiplexer error, e
pga
the programmable gain amplifier error, e
s/h
the sample and hold error and e
ADC
the ADC error.

Example:

substituting

Mux error = 0.01%
PGA error = 0.01%
S/H error = 0.01%
ADC error = 0.012%(analog)
ADC error = 0.012%(quantization) in the above equation, we get RSS error = 0.024%.

-15
FIGURE 1: HIGH LIEVEL AND HIGH SPEED DATA ACQUISITION SYSTEM
EOC
CH7
Es
+15
-15
START
16 CHANNEL
5 +15
EOC
CH0
PGA
0
-15
S/H
AGND
0 0
G0 G1
ABC EN1 EN2
-15
DATA
SA ADC N=12 BIT
+15 -15
0
+15
ANALOG
MULTIPLEXER
CH1
DGND
+15
Antilogarithmic digital to analog converters
(Exponential with negative exponent)

The output voltage of the antilog DAC is proportional to the product of the reference
voltage and the exponentiation of the binary input number. These converters are generally
used in software controlled audio attenuators, digitally controlled AGC systems and
logarithmic ADCs.
The transfer function of the circuit of figure 7 is given by

E
0
= E
r
D ------------ (1)
2
n

Where n is the number of bits and D the digital input word (varies from 0 to 2
n
-1)

--
OP- AMP
--
FIGURE 7: DAC CIRCUIT
R
DIGITAL WORD
0
Er
E0
+
R
+
R
0
DAC
n-bit

The ratio of the voltages is frequently expressed by a logarithmic called decibel (or dB).
By definition decibels are 20 times of the log of the voltage ratio. This may be

20log (e
0
/e
r
) = -rN or e
0
/e
r
= 10
-(rN/20)
---------- (2)

Written as follows:

Where n is the integer equivalent digital input and r the resolution in dB. Equating
equation 1 and 2, we get

D= 2
n
10
-(rN/20)
----------- (3)

Possible implementation of antilog DAC is shown in the figure 8. the circuit consists of an
8 bit DAC and a read only memory (ROM). The ROM translates the 5 bit binary input
into an 8 bit word which is used to drive the DAC. Table 2 gives the nominal output
voltages for all possible input codes. The transfer function of the circuit of figure 8 is given
by

e
0
/e
r
= e
-(rNln10/20)

For r = 1 dB, the above equation becomes

e
0
/e
r
= e
-0.1151293N
or Attenuation = -NdB

where N is the binary input for values 0 to 31.

BUFFER
Er=
10v
D 0 TO 255
FIGURE8: 5 BIT ANTILOG DAC
OP27
--
PROM
74S188
+
0
R=5k
5 BIT
N
0 TO 31
E0
0
+
--
DAC
08
bit
R=5k
R=5k

TABLE 2: ATTENUATION vs. INPUT CODE
Input to ROM
(N)
Contents of ROM
(D)
Decimal Binary Decimal Binary
(HEX)
Out put voltage
(V)
Attenuation
(dB)
0 00000 255 EF 10.00 0
1 00001 228 E4 8.91 -1
2 00010 203 CB 7.94 -2
3 00011 181 B5 7.08 -3
4 00100 162 A1 6.31 -4
5 00101 144 90 5.62 -5
6 00110 128 80 5.01 -6
7 00111 114 72 4.47 -7
8 01000 102 66 3.98 -8
9 01001 91 5B 3.55 -9
10 01010 81 51 3.16 -10
11 01011 72 48 2.82 -11
12 01100 64 40 2.51 -12
13 01101 57 35 2.24 -13
14 01110 51 33 2.00 -14
15 01111 46 2E 1.78 -15
16 10000 41 29 1.59 -16
17 10001 36 24 1.41 -17
18 10010 32 20 1.26 -18
19 10011 29 1D 1.12 -19
20 10100 26 1A 1.00 -20
21 10101 23 17 0.89 -21
22 10110 20 14 0.79 -22
23 10111 18 12 0.71 -23
24 11000 16 10 0.63 -24
25 11001 14 0E 0.56 -25
26 11010 13 0D 0.50 -26
27 11011 11 0B 0.45 -27
28 11100 10 0A 0.40 -28
29 11101 9 09 0.36 -29
30 11110 8 08 0.32 -30
31 11111 7 07 0.28 -31
Voltage-segment digital-to-analog converters

Recently, a few IC manufactures have been introduced a new type of DAC which
is inherently monotonic.

Figure shows a simplified realization of a 4 bit voltage segment DAC. Basically,
this DAC is comprised of two resistor networks, twelve analogue switches, three
buffers and two segment decoders.

In operation, the most significant bits and the segment decoder D
2
select the
voltages(e
r
, 3e
r
/4, e
r
/2 and e
r
/4) from two adjacent taps of resistor network L
2
and
apply them to the inputs of two buffers, U
2
and U
3
. The e
r
is the reference voltage
to the converter. These buffers then force these voltages across the terminals of
resistor network L
1
. The least significant data bits and the segment decoder D
1

select the voltage at one of the taps of resistor network L
1
and apply to the output
e
o
via buffer U
1
. The output voltage e
o
is equal to e
2
at point P
0
and (3e
2
+e
1
)/4 at
P
1
, (e
2
+e
1
)/2 at P
2
and (3e
1
+e
2
)/4 at P
3
, where e
1
and e
2
are the outputs of buffer
U
2
and U
3
respectively.

Table shows the relationship between the digital input code and the analogue
output voltage for the 4 bit DAC. From table and figure, it is clear that the low-order
bits are repeated four times. Hence, the DAC output increases monotonically as
the digital input increases. This type of DAC will have a differential linearity error of
less than or equal to one LSB. The accuracy of the DAC mainly depends on the
leakage current of switches and the offset voltages of buffers.

DAC operating on the above principle is available as monolithic IC: 16 bits: AD569
from analog devices. The settling time is about 6 us.


Output from a 4 bit voltage segment DAC
Binary code
D C B A
Position of switches
Sw3 Sw2 Sw1
Analog output
voltage
0 0 0 0 P
0
P
0
P
0
0
0 0 0 1 P
0
P
0
P
1
e
r
/16
0 0 1 0 P
0
P
0
P
2
2e
r
/16
0 0 1 1 P
0
P
0
P
3
3e
r
/16
0 1 0 0 P
1
P
1
P
0
4e
r
/16
0 1 0 1 P
1
P
1
P
1
5e
r
/16
0 1 1 0 P
1
P
1
P
2
6e
r
/16
0 1 1 1 P
1
P
1
P
3
7e
r
/16
1 0 0 0 P
2
P
2
P
0
8e
r
/16
1 0 0 1 P
2
P
2
P
1
9e
r
/16
1 0 1 0 P
2
P
2
P
2
10e
r
/16
1 0 1 1 P
2
P
2
P
3
11e
r
/16
1 1 0 0 P
3
P
3
P
0
12e
r
/16
1 1 0 1 P
3
P
3
P
1
13e
r
/16
1 1 1 0 P
3
P
3
P
2
14e
r
/16
1 1 1 1 P
3
P
3
P
3
15e
r
/16

Circuit Diagram:

U1A
AD648A
3
2
8
4
1
+
-
V+
V-
OUT
R1
1k
R7
1k
U2A
AD648A
3
2
8
4
1
+
-
V+
V-
OUT
R6
1k
S1
SW DIP-4
1
2
3
4
8
7
6
5
R3
1k
S3
SW DIP-4
1
2
3
4
8
7
6
5
S2
SW DIP-4
1
2
3
4
8
7
6
5
R2
1k
HI
U3A
AD648A
3
2
8
4
1
+
-
V+
V-
OUT
R5
1k
0
R8
1k
R4
1k
Assignment
The circuit shown in figure 1 consists of two identical 8 bit digital to analog converters,
which are cascaded. Show that the circuit yields a 16 bit DAC.
LSD
R=5k
+
--
current sink
Er=
10v
0
R=5k
Rref
DAC08E
current sink
--
digital
input word
Rref
+
R=200
DAC
08
bit
0
R=5k
digital
input
word
--
0
Rref
R=5k
0
FIGURE 1: 16 BIT DAC USING TWO 8 BIT DAC.
0
R=5k
E0
Er=
10v
Rref
0
0
current sink
R=51k
current sink
+
MSD
DAC errors

Offset error
The offset voltage or zero error is the output voltage of the DAC when the digital input
word is equal to zero. The error produces a vertical shift of the transfer characteristic may
be positive or negative shift (figure 9).
In practice, the offset voltage will normally be adjusted to zero.

Figure 9: output a 3 bit DAC with offset vs. output of the ideal 3 bit DAC

Gain error
The gain error or scale factor of a DAC is the number, which establishes the relationship
between the converters analog values and digital code fractions. Gain error is the amount
by which the converters actual scale factor differs from its designed or nominal value. It is
usually expressed as a % deviation from the nominal value. The gain error may be defined
as the difference in full scale values between the ideal and actual transfer functions (figure
10) when the offset error is zero (expressed as a % of the desired nominal full scale).


Figure 10: output a 3 bit DAC with gain error vs. output of the ideal 3 bit DAC

Linearity error
The linearity error is the difference between the actual output voltage and the
corresponding voltage measured on the ideal transfer characteristics. The error is usually
specified as a part of an LSB (or as a % of full scale voltage). A good converter exhibits a
linearity error of less than 0.5 LSB (or 0.5x100/8=6.25%). The converter of figure 11
contains circuit mismatches that cause its output to be no longer perfectly linear.
The step size, the differential linearity error and integral linearity error are plotted in figure
12.

Differential linearity error
The differential linearity error is the magnitude of the maximum difference between each
output step of the converter and the ideal step size of 1 LSB.

Integral linearity error
The integral linearity error is the maximum deviation of the converters transfer function
from an ideal straight line.

Figure 11: output voltage versus digital input word for a 3 bit DAC containing circuit
mismatches

figure 12: linearity error


Chapter-12
Digital to Analog Converters

Digital to analog converters(DAC) provide an interface between the digital signals of
computer system and the continuous signals of the analog world. The DAC takes digital
signals (or digital codes) as inputs and generates constant output voltages or currents,
which may be used to control processes or display status information.

DAC with CMOS switches

A popular technique for digital-to-analog conversion is the R-2R ladder method. This
method is specifically used for multiplying type digital-to-analog convertors. These are
commenly used in AGC(Automatic gain Adjustment)Systems, Complex function
generators, and audio encoders.

A possible implementation of a 3-bit CMOS DAC is shown in figure1 using a R-2R ladder
network, three SPDT CMOS switches and a summing amplifier, The ladder network
consists of series resistors of value 2R. The bottom of each shunt resistor
(2R) has a SPDT switch, which connects the resistor to either the ground or the input of an
inverting amplifier.

The digital input signals D0 to D2 direct the currents to either the summing-point of adder
U1 or the ground. Since points ON and OFF are at ground potentials the ladder currents are
independent of switch position. Hence with the application of KCL to the network, the
voltages e1 and e2 are er/2, er/4 respectively. If all bits are OFF(000B), then the output
voltages e0 is 0 (shown in figure1). Similarly, if all bits are ON(111B) the the output
voltages(shown in figure 1).

e
0
= -e
r
/R* R
f
/2
3
*7

In general for an n bit CMOS DAC the output voltage

e
0
= -e
r
/2
n
*R
f
/R
dac
*[D]

Where n is the number of bits, Rdac is the resistance of the ladder network(R) and D is the
digital input code, which varies from 0 to 2n-1.

Advantages of DAC with CMOS switches

The advantage of DAC with CMOS switches is that only two values of the resistors are
required, with the resultant ease of trimming and excellent temperature tracking. For high
speed applications relatively low resistor valued can be used.

What is multiplying DAC?

If the reference voltage can be varied during converter operation, the DAC is said to be
multiplying DAC. The varying reference signal is multiplied by the digital code. A DAC
with CMOS switches realized with the inverted R-2R ladder of figure 1 can have a wide
bandwidth and the reference can be either polarity. Finally, if bipolar coding is used and a
bipolar reference is also permitted, four quadrant multiplication is possible. Digital-to-
analog converters operating on the above principle are available as monolithic ICs, 12 bits
AD7531 from Analog Devices. The settling time is about 0.5sec.

Programmable Phase Shifter

To achieve a variable phase shift a multiplying DAC U4 is connected in the feedback loop
of an integrator U2. Operational amplifier U1 serves as a summing amplifier U3 permits
phase variation between 0 to180 without disturbing the amplitude of the output signal eo.

e
01
= e
s
+ e
02

e
02
= -De
01
/jwR
dac
C2
n

And e
0
= -(e
01
+ e
02
)

Apply KCL to the circuit shown in Figure 2 and obtain

Solving the above three equations we get

#E0/es# = 1

$ = -2 tan
-1
2"f
c
R
dac
2
n
/D

Where Rdac is the resistance of the ladder network, f is the frequency of input signal, D the
fractional binary values have the input digital code and n the number of bits. If the
frequency of the input signal es is constant, then for the components shown the circuit
provides phase shift of

5.4 at code FFF Hex and
179.4 at code 001 Hex.

Programmable resistor using multiplying digital- to-analog convertors

Figure 3 shows a configuration that implements a digitally programmable resistor using a
multiplying digital-to-analog converter and operational amplifiers. The circuit is equivalent
to a voltage-controlled resistor. The simulated resistor has a value that reflects the ratio of a
fixed resistor Rx and a control voltages es, application includes generating precise
resistance values for remotely controlling monostable multivibrators and configuring
DAC1220 12 bit multiplying digital-to-analog converter.

Apply KCL to the network and obtain

e
1
= -e
s
D/2
n

Where D is the digital input code to the multiplying DAC and is varies from 0 to 2n-1 and
n is the number of bit in DAC.

e= (e
s
+ e
1
)/2 and e
2
=(e
s
+e
1
)

The current through the resistor R
x

I
s
=(e
s
/R
x
)(D/2
n
) and

R
s
= e
s
/I
s
or R
x
(2
n
/D)

Monostable Multivubrator
B
a2 a1 O
OP-27
3
2
6
+
-
OUT
1k
Timing pins
1k
R
39k
74LS121
15n
5k
LM311
7
2
3
1
8
4
OUT
+
-
G
V
+
V
-
C
0.01uf
0 to 10v
5k
es
Integrator

Voltage to Frequency converter using DAC08 as a current switch

D
A
DAC08E
74LS07
Buffer
+15v
+15v
+5v
+5v
-15v
+5v
+5v
1mA
Timing T=RCln(2)=20us
Output Frequency fo 0 to 10khz
-15v
D0 to D7
10k
10k
-5v
eR
R7
1k
-5v
10k
10k
U1
OP-27
3
2
6
+
-
OUT
10k
Rref
5k
10k
es
Rx
10k
Rref
5k
5k
U1
OP-27
3
2
6
+
-
OUT
OP-27
3 2
6
+
-
O
U
T
U1
OP-27
32
6
+
-
O
U
T
U1
OP-27
3
2
6
+
-
OUT
OP-27
32
6
+
-
O
U
T
eR
5k
Rref
5k
Rref
5k

Software Programmable Register
er/2
=2.5V
AD741
3
2
6
+
-
OUT
-15v
3 bit pipeline ADC
+15v
-15v
+15v
3
2
6
+
-
OUT
+15v
-15v
D0
comparator:LM311
+5v=er
er/2=2.5V
33k
3
2
6
+
-
OUT
AD741
3
2
6
+
-
OUT
+15v
D2
3
2
6
+
-
OUT
er/2=2.5V
+15v
es=0 to 5V
-15v
470
D1
33K
comparator:LM311
470
33k
470
+5v=er
33K
-15v
+5v=er

DAC08E
DAC08E
Digital Word D
Rs = (256*Rx/D)

Inverting Summing Amplifier
R
R
er/2
R
R
AD741
3
2
6
+
-
OUT
er/4
er

U3
3
2
6
+
-
OUT
R
R
C1
0.01uf
R
R
10k
R
R
10k
R
10k
Programmable Phase Shifter
10k
3
2
6
+
-
OUT
es
10k
e0 U1
10k
U2
10k
3
2
6
+
-
OUT

DAC1220
Digital Word

3
2
6
+
-
OUT
3
2
6
+
-
OUT
3
2
6
+
-
OUT
Rx
U1
U2
U4
R3
1k
10k
U5
10k
10k
3
2
6
+
-
OUT
Software Programmable Register
10k
es

U3
DAC1220
Digital Word D
+5v
470
-5v
10k
-5v
10k
U2
LM311
7
2
3 1
8
4
OUT
+
- G
V
+
V
-
LM311
7
2
3 1
8
4
OUT
+
- G
V
+
V
-
-5v
LM311
7
2
3 1
8
4
OUT
+
- G
V
+
V
-
10k
D2
AD741
3
2
6
+
-
OUT
AD741
3
2
6
+
-
OUT
D1
10k
D0
es
er/2
er/2
+5v
er/2
er/2 = 2.5v
+5v
3-bit pipeline ADC using 1-bit ADCs and 1-bit DACs
470
470

Rs
312.5
e+=15v
625
LM324
3
2
4
1
1
1
+
-
V
+
V
-
OUT
R1
100 12k
10k
2N1482
1
2
3
e+=15v
2N1482 1
2
3
Q3
2N1470 1
2
3
LM324
3
2
4
1
1
1
+
-
V
+
V
-
OUT
e+=15v
LM324
3
2
4
1
1
1
+
-
V
+
V
-
OUT
es = 0 to 5v
e+=15v
e+=15v
R2
100
4-20mA
4-20mA Current Transmitter
LM336-2.5V/ SO
4
8
5

Advance Instrumentation - I: Operational Amplifier Fundamentals

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Advance Instrumentation - I

IC Department 1 Prof. J. B. Vyas

Transfer function of the circuit is given by

Second Order Band Pass Filter

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