Digital Circuit Capacitance and Switching Analysis for
Ground Bounce in ICs with a High-Ohmic Substrate
Mustafa Badaroglu'.', Lakshmanan Balasubramanian'.', Kris Tiri3, Vincent Gravot',
Piet Wambacq', Geert Van der Plas', Stephane Donnay', Georges Gielen4, and Hugo De Man'34
'IMEC, DESICS, Kapeldreef 75, B-3001 Leuven, Belgium, 'Also Ph.D. student at K.U. Leuven, Belgium
3EE Dept. - University of California at Los Angeles, CA, USA, 4ESAT, K.U. Leuven, Belgium
Abstract:
Ground bounce is a major contributor to substrate
noise generation due to the resonance caused by the
inductance and the VDD-VSS admittance that
consists of the on-chip digital circuit capacitance of
the MOS transistors, the decoupling, and the
parasitics arising from the interconnect. This paper
addresses (1) the dependence of the VDD-VSS
admittance on the different states of the circuit and
the interconnect and (2) the computation of total
supply current with ground bounce. The VDD-VSS
admittances of several test circuits are computed with
13% maximum error relative to the measurements on
a test ASIC fabricated in a 0.18pm CMOS process on
a high-ohmic substrate with 18Qcm resistivity. It is
also shown that this admittance depends on the
connectivity of the gates to the supply rail rather than
their connectivity among each other.
1. Introduction
With the increase of switching speed of digital circuits
and tighter requirements on the signal-to-noise ratio in
analog circuits, substrate noise is a major obstacle for
single-chip integration of mixed-signal systems.
There have been only a few works addressing the
generation mechanisms of substrate noise. In most cases
only the propagation mechanisms have been measured.
A good overview of the substrate noise experiments is
given in [I]. Substrate noise experiments have been
carried out on test chips with dedicated digital substrate
noise generators [ I ] or using only small digital circuits
[3] by giving fewer details on how the noise is generated.
In [4], parallel sets of tri-state buffers with different
driving capabilities are operated with an intemal/extemal
clock in order to study the substrate noise. The outputs of
these tri-state buffers have binary-weighted loads, which
are in pF range, connected to the substrate. Due to these
large load capacitances in the experiments, the substrate
noise is dominated by capacitive coupling, mostly the
case in U 0 buffers. In reality only a small portion of the
digital circuitry can drive such large loads
simultaneously, mostly at a lower speed. The coupling
from the substrate contacts of the ground rail is therefore
more dominant in noise generation for large-scale
integrated circuits [5]. The modeling of the transfer
function from the power supply to the substrate or
equivalently to the circuit ground as well as the modeling
of the power supply become more crucial.
Therefore a careful selection of the test circuits is
necessary to study the scalability aspects of the measured
substrate noise to ULSI systems. For this purpose we
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have designed dedicated simple test circuits in a 0.18pm
6M CMOS process in order (1) to demonstrate the state
dependent transfer functions, (2) to verify that these
transfer functions are topology independent, and (3) to
show that these transfer functions as well as the supply
current can be linearly superpositioned in order to form
the models of large digital systems. Topology
independent transfer functions indicate that modeling
only connectivity to the supply network is important
rather than the connectivity to other gates. The paper is
organized as follows: In section 2 we introduce a lumped
model for ground bounce and briefly describe its
dependencies. In section 3 we describe the test circuits
used in our experiments. In section 4 the measurements
are presented. In section 5 conclusions are drawn.
2. Chip-level ground bounce macromodel
VSS
-b
Figure 1: (a) Chip-level ground bounce generation model.
(b) Equivalent parallel FUC-network.
Figure 1 shows the ground bounce generation model for
a network of the gates on a bulk substrate. In this model
the supply line inductance and its series resistance are
represented by Lb and Rb respectively. Additional on-
chip decoupling capacitance and its series damping
resistance are represented by Cd and Rd respectively. For
each gate: The circuit admittance is represented by a
capacitance (Cc) in series with a resistance (Rc). The
series resistance from the VSS contact to the substrate is
represented by Rs. The capacitance due to the reverse
biased n-well junction diode and the resistive path are
represented by Cw and Rw respectively. A resistive
network models the coupling through the bulk. By taking
the substrate into account the well capacitance (Cw) and
the substrate contact resistance (Rs) are computed as a
part of the VDD-VSS admittance.
Assuming that all gates under consideration belong to
single power domain, it is possible to combine the VDD-
VSS admittances (Y11) of each gate in the same power
network to a single admittance. As will be illustrated
later, the effective admittance will be the same for two
different circuits, which contain the same number and
0-7803-8 108-4/03/$17.0002003 IEEE.
 type of gates in a single power region. The contribution become 9.18fF, 7.28fF, 7.28fF, and 5.89fF respectively.
of the substrate in the overall Y11 is negligible for high- Note that interconnect capacitance is also logic-state-
ohmic substrates. For a 2-input NAND gate (NAND2) in dependent. The interconnect will be a more dominant
a 0.18pm CMOS technology on a high-ohmic substrate contributor to Cc for large digital circuits with dense
with 180cm resistivity this comparison is shown in interconnects and complex power grid and also for the
Figure 2. The substrate netlist is extracted by using future technologies with smaller devices. For the sake of
Substratestorm [ 6 ] . preserving the linearity one can use an average value
IY111
NAND2 1 (e.g. averaged between lOOkHz and 1GHz) for the VDD-
overall IYlll due to VSS admittance over the logic-states as well as the
the circuit and !he
substrate maximum and average error bound.
[degrees] ~ Y l l
90

88
IYlllonlydueto
IO" the subsbate
(Cw, Rw. Rs and
I" the substratemesh)

'?OW 1M 10M lOOM 1G 10G

Frequency

Figure 2: Contribution of the substrate in the overall VDD-

VSS admittance (Y11) of a NAND2 gate.
FrequenQ
By using this model the voltage swing at the VSS node
Figure 3: Average value of the NAND2 VDD-VSS circuit
(ground bounce) is computed as a function of the suppty admittance over the logic-states.
current (Isupply) for an equivalent parallel RLC-network %oaie~~~~,ni~iil
(Figure 1b) with the element values given by:

"-;3.E
---+1 - 1
L
.-
1
'O AB.0110 -
RP Rd(l+Qj) 2Rb(l+Q:) ' Rc(l+Q:) I. 1 0 mm io
cc Cd 10
CP=-+-
(l+l/Q:) (l+l/Qa) .::
d0
m=i1
-L
,
6 - A - -
-
-
- _ - -

e 1 1
%Ow IM 10M IWM 10 10G 50 0 2 0 4 06 08 3 12 1 1 16 1 8 2
FRC!Ye"V Svwly wltxle M

Q: =I/[w 'Rd 'Cd ' 1. Q! [w'Lb' /Rb '1, QZ = 1/[a

'Rc 'Cc '] Figure 4: (a) Relative difference (in %) in the magnitude of
The resonance frequency (w,) and the damping factor (6,) the NAND2 VDD-VSS admittance for each logic-state
-
of the oscillations are given as follows: compared to the value averaged over the logic-states. (b)

W O =-
my&='.F
1
2 R P CP
In order to solve w, and 5 an iterative approach can be
employed by first finding an initial value of w, for Qd=a:,
Qb=O, and Qc=O. This a, is then used in order to update
the new values of Qd, Qb, and Qc. These values are again
used to update o, and t;. This iterative solution goes on
until the convergence in w, and 6 values.
2.1. Logic-state dependence of the circuit capacitance
Equations (1)-(2) contain some non-constant terms due
to Cc and Rc. The significance of these terms can be
reduced by adding fixed decoupling capacitance but at
the expense of the chip area. Figure 3 shows the average
value of Y11, simulated in SPICE, over the logic-states
for the NAND2 gate including its substrate model.
Figure 4a shows the percentage difference of /Y111
relative to its mean value over the states. For medium
sized circuits (from lKgate to lMgates), the ground
bounce resonance (equation (1 -2)) occurs between
lOMHz to 2GHz. In this frequency region there is a
maximum variation of 30% over the mean value of IY 1 1I
which results in a 19% variation on the resonance
frequency with no extra on-chip decoupling. The values
of Cc for a NAND2 gate are 11.37fF)9.47fF, 9.47fF, and
5 . 9 9 s for the logic-states 00, 01, 10, and 11
respectively. By omitting the influence of the
interconnect capacitances inside the gate these values
NAND2 circuit capacitance versus supply voltage.
Figure 4b shows the simulated circuit capacitance as a
function of the supply voltage. Circuit capacitance in a
non-switching gate does not change significantly over
the variations of the supply voltage around its nominal
value due to ground bounce since the transistors in this
gate are either in cut-off or in the linear region. The
discussion in this section is applicable to all static CMOS
gates without loss of generality.
2.2. Supply current analysis with ground bounce
The linear relationship between the supply current and
the number of simultaneous switching gates does not
occur for the large ground bounce. The negative
feedback from the ground bounce on the supply current
of the buffers is addressed in [7]. This work only
considers the long-channel devices and the inputs from
an external source with a clean ground. In fact it is more
common to have the inputs from an on-chip driver In the
same power line with the switching circuit. The,
saturation current of a switching inverter for a rising
input is defined by:
Isupply = K(Vinp - VSS - Vth)" (3)
where K is a process and a geometry dependent
coefficient and CL is the short channel velocity saturation
coefficient, which is between 1 and 2 [8]. Vinp is the
input voltage, which may contain onloff-chip noise, and
VSS is the on-chip ground voltage, which has a ground

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 bounce component. In the case of an on-chip driver the capacitance C that corresponds to the input capacitance
negative feedback effect is much more than an external of the inverter W(N/P)=1.21/2.60pm. Circuit T1 has an
signal with a clean ground since the logic level high at equivalent area of 135-gates.
the input is the circuit positive supply VDD having a Circuit T3 is composed of serially cascaded inverters
supply bounce, which becomes out of phase with VSS (Figure 7). T3 is controllable with 4 inputs in order to
during the transition. Figure 5 shows the supply current operate the parallel combinations of 1,2,4, and 8 serially
and the ground bounce peak-to-peak values for a number cascaded inverters. Each set of serially cascaded
of simultaneous switching inverters (shown as T1 circuit inverters is driven by the buffer, which is loaded with the
in Figure 7) implemented in a 0.18pm CMOS process, same load capacitance as in T1 in order to preserve the
having Vtho(N/P)=0.32/-0.47V and with input rise time same inp
of 50ps, for the following three cases when the circuit:
(1) has no package parasitics,
(2) has a package (Lb=lnH, Rb=O.lQ) and has the input
from an external driver (BUF)with a clean supply,
(3) has a package (Lb=lnH, Rb=O.ln) and has the input
from an internal driver (BUF) on the same supply line
with the circuit.

z: [mvpp] vss
Case@)
Figure 6: Microphotograph of the test circuits.
(b) 400

i ; : 0 3100
200 Case (3)

0 Case 1
0 2 4 6 8 10 I2 14 16
Number of simultanecus switching inverters

Figure 5: (a) Supply current (b) Ground bounce voltage

peak-to-peak values versus the number of simultaneous
switching inverters.
The supply current peak-to-peak value starts to deviate
from the linear superposition with respect to the number
of switching inverters for a ground bounce larger than
7% of the voltage headroom (VDD-Vth=1.48V). This
value can be generalized to other gates provided that the
input rise/fall time is the same/faster adthan for the .UI TFFppTp T3 Clrcult
above case. The linearity is still preserved (due to a=1
for short-channel devices) for cases (2) and (3) however Figure 7: Schematic of the circuits T1 and T3.
with a smaller slope compared to case (1). The supply
current peak value decreases by 35% in case (3) with
respect to case (1) with the generated ground bounce of
48OmVpp in case (3).
3. Description of the test circuits
The dependence of supply current and ground bounce v
. I I J

has been verified experimentally with test circuits that

have been fabricated in a 0.18pm 6M CMOS process on
a high-ohmic substrate with 18ncm resistivity (Figure
6). These circuits are:
1. Parallel connection of 16 inverters (Circuit Tl),
2. Serially cascaded inverters in parallel (Circuit T3),
3. A 256-gates sequential circuit (Circuit T4),
Circuit T1 is composed of inverters connected in parallel
(Figure 7). The circuit is controllable with four inputs in
order to operate the parallel combinations of 1, 2,4 and 8
inverters. Each set is driven by a buffer (BUF). To have
equal input slope at each set, each buffer output is
balanced with several parallel connections of a load
Figure 8: Schematic of circuit T4.
Circuit T4 is composed of an 8-bit maximum-length
sequence PRBS generator in cascade with a 4-bit
comparator (Figure 8). The circuit generates a trigger
signal (TRIGOK) in order to synchronize the
measurements. The RESETGEN module generates a
synchronous reset for the circuit during the first 3 clock
cycles after external reset.
4. Experimental Results
We compute the average value of the VDD-VSS
admittance (Table 1) of the test circuits by simulating
them in SPICE and also by using the macro models

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SPICEDIODEL Cc [fF] T1
No interconnect
Local
Local+Signal
Local+Signal+Global I
MEASURED I
142411395
196711966
244512508
2527/2581
2324
Table 1: Mean values of the VDD-VSS capacitance for the
test circuits (from SPICE simulations, superpositioningof
the macromodels, and measurements)
Table 1 shows that the local interconnect is significant in
the overall VDD-VSS admittance: 21% in T1, 22% in
T2, and 21% in T4. Omitting all the interconnects wil’l
cause an error of 33%, 29%, and 36% for T1, T3, and T4.
respectively in the resonance frequency estimation. For
future technologies this error will be even more
pronounced. Note that the VDD-VSS admittances of TI
and T3 are the same even when local interconnect is
taken into account. This shows that the connectivity of
the gates to the supply rail is important rather than the
connectivity of gates to each other. The overall
difference is limited to 10% from the measurements.
,om[mv] VDDACPP
900
800
200
100
Y 2 4 6 6 IO
IS=denmal((lN4. IN3. IN2 [NI})
Input swltching state for a rising edge at the inputs
Figure 9: Measured supply bounce peak-to-peak value for
circuits T1 and T3 versus the input switching states.
Figure 9 shows the measured AC peak-to-peak value of
the supply voltage (VDD) on the die for T1,3 versus the
input switching states (IS). T3 generates 33% and 40%
less noise at IS=4 and IS=8 respectively in comparison to
the case in T1. This shows that the serial logic is less
noisy than the parallel logic. The negative feedback
effect is demonstrated by the deviation from a straight
line derived due to the first two points (at IS=O and 1).
For the maximum number of simultaneous switching
inverters in T1 this deviation is measured as 7 1‘YO.
Figure 10 shows the measured VDD-VSS admittance of
T4 as a function of the logic-states, which is controlled
by the on-chip PRBS.A 3-4% variation is measured 011
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the magnitude of the VDD-VSS admittance over
400MHz to lGHz frequency band with respect to the
admittance at the power-up logic-state of circuit T4. In
order to treat this logic-state-dependence, Table 1 uses
the average value for the VDD-VSS circuit admittance as
well as for the interconnect over the logic-states.
mi M ~ = w & an ~n iYi11 aner n w w c k s w r i -UP [ogJ 1MOWW an mi sbcn dod +es w r t - w p
12
1
08
06
D4
02
0
42
4 4
‘‘840aM 500M 6WM 7wM BDOM 9OW 1G
FW”*C.=f F-WV
Figure 10: Measured variations in the VDD-VSS
T3 T4
admittance of circuit T4.
1420/1395
196211966
234712508
2387/2581
261 1
192511831
269012645
357513407
3589/3501
3085
I 5. Conclusions
The experiments on simple circuits give ideas to do
further simplifications for ground bounce modeling. We
have shown that the contribution of the substrate in the
VDD-VSS impedance of the gates is negligible for high-
ohmic substrates. The logic-state dependency of the
inputs and interconnects on the ground bounce should be
taken into account. Both measurements and simulations
have shown that the assumption of linear superposition
of supply currents to obtain the total supply current is
valid only for ground bounce values below 15% of
VDD-Vth. We experimentally verified that it is possible
to derive the overall chip-level model for ground bounce
by directly summing the VDD-VSS admittances of the
individual gates. This sum is independent of the overall
circuit topology. Using this topology-independent
computation for a more complex sequential circuit has
estimated the circuit capacitance within 13% error.
Measurements also verified that the serial logic generates
less ground bounce than due to the parallel logic.
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