Académique Documents
Professionnel Documents
Culture Documents
2, FEBRUARY 2006
Authorized licensed use limited to: University of Central Florida. Downloaded on November 8, 2008 at 21:36 from IEEE Xplore. Restrictions apply.
BADAROGLU et al.: EVOLUTION OF SUBSTRATE NOISE GENERATION MECHANISMS 297
TABLE I
DESCRIPTION OF VARIABLES
Fig. 2. Schematic flow of the substrate currents in and around a digital gate,
and an analog circuit on the same die.
(1)
where is the critical electrical field at which the mobility of
where and are the parts of the cur- the carriers (electrons/holes) saturates. is the effective
rent due to impact ionization, S/D coupling, and supply length of an nMOS (pMOS) transistor.
coupling, respectively. For the sake of quantitative comparison As an illustration, we consider an nMOS device with
of the currents, we use the peak values of the time-varying cur- m, V, V, V/ m,
rents although these peaks do not necessarily happen at the same V , and V. Using (2) we find that the
time. In this paper we represent the peak value of the time-do- current is several orders of magnitude smaller than the
main currents by the notation , while we represent the dc current (Fig. 4) at = . At this point,
Authorized licensed use limited to: University of Central Florida. Downloaded on November 8, 2008 at 21:36 from IEEE Xplore. Restrictions apply.
298 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 53, NO. 2, FEBRUARY 2006
(8)
Authorized licensed use limited to: University of Central Florida. Downloaded on November 8, 2008 at 21:36 from IEEE Xplore. Restrictions apply.
BADAROGLU et al.: EVOLUTION OF SUBSTRATE NOISE GENERATION MECHANISMS 299
TABLE II
COMPUTATION OF DIFFERENT COMPONENTS OF [i (t)] =[i (t)]
RATIO (K ) FOR THREE TECHNOLOGIES: A 0.18-m PROCESS (BULK-TYPE),
A 0.35-m AND A 0.50-m PROCESS (BOTH EPI-TYPE)
Fig. 5. Layout and extracted substrate resistances for the nMOS device of the
2D case inverter in a 0.18-m 1.8-V CMOS process on a bulk-type substrate.
when
3D case (11)
where we typically have . and
are the thickness values of the substrate and of the well,
respectively. is the resistivity of the substrate (typically
10 cm). For the calculation of on bulk-type sub-
strates, the 2-D case is applicable when analog circuits are as-
Fig. 6. Illustration of switching in a circuit with ideal switches.
sumed to be placed far from digital circuits with a distance larger
than the thickness of the substrate ( – m).
Table II lists the values computed for the load capacitances C. Supply Coupling
and the ratio for the CMOS inverter In digital circuits, high peaks of the supply current of the
in several technologies: 0.18-, 0.35-, and 0.50 m CMOS. switching gates create supply noise in the supply network
The backside contact is grounded. Each inverter drives another (Fig. 6). In a p-type substrate this supply noise couples ca-
identical inverter. For the 0.18- m inverter, the layout and pacitively into the substrate from via the n-well junction
the extracted substrate parameters are shown in Fig. 5. The capacitance, and resistively from via the substrate contacts.
ratio for the 0.18 m inverter is the The supply noise consists of two parts: common-mode (CM)
higher than for the 0.35 m and 0.50 m inverters due to two and differential-mode (DM) noise [16]. CM noise is caused
reasons: (1) higher resistivity of the bulk-type substrate, and by the imbalance between supply current and ground return
(2) larger values due to a smaller S/D area due to 45 degree current when a circuit is driven by input signal(s) referenced to
poly lines and STI (which reduces the drain-bulk capacitances). power region(s) different from the one of this circuit. DM noise
Similar analysis for other standard cells has shown that the is caused by the oscillations of the damped LC tank formed
resistive division from (6) and (7) has about the same value between the circuit capacitance and the supply parasitics. For
as a result of using a fixed-height standard cell library where a digital circuit of practical size, the portion of gates driven by
the substrate contact area is proportional to the width of the input(s) referenced to different power regions is substantially
standard cell. low. Also the combinations of rising/falling transitions at the
From the results of Table II, we conclude that the input(s) have a canceling effect on the CM noise, which is not
value is at least an order of magnitude larger than the the case for the DM noise. From now on, we assume that the
value. On the other hand, these conclusions supply noise only consists of DM noise.
are not enough to decide that S/D coupling is not a dominant The amount of DM supply noise oscillations is found by ana-
injection mechanism. Therefore, we first need to know the lyzing the network shown in Fig. 6. In this network the equiva-
injection mechanism due to the supply coupling. This will be lent switching capacitance is represented by , which is the
described in the next section. Then, in Section III, we present average (dis)charged capacitance of the switching gates. Here
a quantitative framework that uses these results for finding the term is the switching activity factor that is defined as the
which noise injection mechanism actually dominates under the ratio of the equivalent switching circuit capacitance to the total
size constraints of the circuit together with external (package) circuit capacitance . The term is typically between
parasitics. and . We define the equivalent nonswitching capacitance of
Authorized licensed use limited to: University of Central Florida. Downloaded on November 8, 2008 at 21:36 from IEEE Xplore. Restrictions apply.
300 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 53, NO. 2, FEBRUARY 2006
the circuit , which is the average capacitance of From Section II.A, it was concluded that the impact ionization
the nonswitching gates. In addition, the decoupling capacitance mechanism can be neglected.
is a part of the equivalent nonswitching capacitance be- The dominance of supply coupling versus S/D coupling will
tween and . We define as the total duration of the now be judged by comparing (7) and (14). For the sake of
current charging the switching capacitance. This current is indi- brevity, here we consider bulk-type substrates with a floating
cated as in Fig. 6. We assume that this current is a trian- backside node. We will now describe the scaling of the currents
gular waveform with equal rise/fall times. The current coming with the number of gates . For the part we
from the external power supply and from the nonswitching ca- need to scale the resistance of a unit gate with
pacitances are indicated as and , respectively, in the total number of gates due to many parallel resistive
Fig. 6. There are two extreme cases that indicate which param- paths from the digital substrate contacts (that are connected to
eters to control in order to reduce the supply noise: (1) the case a single voltage source that models the total ground
when the nonswitching capacitance provides most of the cur- bounce in the system). For the part, we need to
rent required by the switching circuits, and (2) the case when scale the value with the total number of switching
the external power supply provides most of the current required gates . On the other hand, we do not scale the resis-
by the switching circuits. tances since for each gate the junction-related noise is injected
The first case occurs when where is from an individual source, which is the switching node of the
the resonance frequency where circuit. We also ignore the contribution of the impedance from
. We have in the comparison since the spec- the substrate contact(s) to the off-chip ground on the overall
tral bandwidth of the switching current is determined by impedance from the bulk node to the off-chip ground. After
either the rise or fall time, which is half of the total duration this scaling procedure, the supply coupling current is dominant
. We define the voltage transients and if the following condition is satisfied:
as the bounces on the ground and the positive supply rail, re-
spectively, measured on the die, referred to the external power
supply, which is assumed to be clean. For , and
, the ground bounce value at
(12) (15)
(14)
Authorized licensed use limited to: University of Central Florida. Downloaded on November 8, 2008 at 21:36 from IEEE Xplore. Restrictions apply.
BADAROGLU et al.: EVOLUTION OF SUBSTRATE NOISE GENERATION MECHANISMS 301
where
(18)
Authorized licensed use limited to: University of Central Florida. Downloaded on November 8, 2008 at 21:36 from IEEE Xplore. Restrictions apply.
302 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 53, NO. 2, FEBRUARY 2006
Authorized licensed use limited to: University of Central Florida. Downloaded on November 8, 2008 at 21:36 from IEEE Xplore. Restrictions apply.
BADAROGLU et al.: EVOLUTION OF SUBSTRATE NOISE GENERATION MECHANISMS 303
Authorized licensed use limited to: University of Central Florida. Downloaded on November 8, 2008 at 21:36 from IEEE Xplore. Restrictions apply.
304 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 53, NO. 2, FEBRUARY 2006
of these two extreme cases, the conclusions from these simula- and an increase in die area. With technology scaling KG be-
tions can be generalized for other circuits. We hereby demon- comes more effective. With proper KG, the S/D coupling will
strate a worst-case situation for S/D coupling where all gates become the dominant noise injection mechanism. In this case,
are switching in the same direction. During the simulations we substrate noise can be reduced by increasing the number of sub-
consider a practical system where each gate and its input(s) are strate contacts, by using a high-ohmic substrate, and by em-
referenced to a single power region. Therefore, the supply noise ploying GRs. For GRs the grounding should be properly done,
only consists of DM noise. Similar conclusions can also be de- otherwise the GR could act as a highway for the noise to propa-
rived when we consider the CM noise [16]. gate into the sensitive circuits. Technology scaling increases the
For all cases in the simulation the significance of impact ion- required number of bumps used for grounding the GR, but oth-
ization decreases substantially. Therefore, it can be ignored. It erwise does not change the efficiency of a GR. For all cases the
scales down the slowest in low-standby-power logic due to the significance of impact ionization can be ignored.
fact that the supply voltage scales down the slowest in this logic.
For 10 K gates with no KG, the supply coupling com- REFERENCES
puted using the equivalent network given by Fig. 6 does not
[1] S. Donnay and G. Gielen, Eds., Substrate Noise Coupling in Mixed-
scale with technology scaling. On the other hand, for 5 gates Signal ASICs. Norwell, MA: Kluwer, 2003.
with no KG, the supply coupling scales at the same rate as [2] D. K. Su, M. J. Loinaz, S. Masui, and B. A. Wooley, “Experimental re-
(di/dt)/ given by (13). The rate of sults and modeling techniques for substrate noise in mixed-signal inte-
scaling is the fastest in high-performance logic due to the fact grated circuits,” IEEE J. Solid-State Circuits, vol. 28, no. 4, pp. 420–430,
Apr. 1993.
that the switching time scales down the fastest in this logic. In [3] J. Briaire and K. S. Krisch, “Principles of substrate crosstalk generation
both cases the supply coupling dominates the S/D coupling. in CMOS circuits,” IEEE Trans. Computer-Aided Design Integr. Cir-
When we use KG, the situation reverses, i.e., the supply cuits, vol. 19, no. 6, pp. 645–653, Jun. 2000.
coupling scales down much faster than the S/D coupling. This [4] R. Senthinathan and J. L. Prince, “Simultaneous switching ground noise
calculation for packaged CMOS devices,” IEEE J. Solid-State Circuits,
means that the S/D coupling continues to be the dominant in- vol. 26, no. 11, pp. 1724–1728, Nov. 1991.
jection mechanism (if for the current technology we achieve to [5] M. Badaroglu, M. van Heijningen, V. Gravot, J. Compiet, S. Donnay,
reduce the supply-coupling by means of KG). Fast downscaling G. Gielen, and H. De Man, “Methodology and experimental verifica-
of the supply coupling is due to downscaling of the metal-bulk tion for substrate noise reduction in CMOS mixed-signal IC’s with syn-
chronous digital circuits,” IEEE J. Solid-State Circuits, vol. 37, no. 11,
parasitic capacitance of each gate despite the fact that the
pp. 1383–1395, Nov. 2002.
resonance frequency increases with technology scaling. But [6] M. Nagata, J. Nagai, K. Hijikata, T. Morie, and A. Iwata, “Physical de-
the impact of the decreasing capacitance is much faster than sign guides for substrate noise reduction in CMOS digital circuits,” IEEE
the impact of the increasing resonance frequency. This capac- J. Solid-State Circuits, vol. 36, no. 3, pp. 539–549, Mar. 2001.
[7] P. Larsson, “Power supply noise in future ICs: A crystal ball reading,” in
itance decreases since with technology scaling the metal-bulk
Proc. IEEE Custom Integrated Circuits Conf., May 1999, pp. 467–474.
dielectric material improves and the geometric dimensions of [8] X. Aragones, J. L. Gonzales, and A. Rubio, “Substrate coupling trends
the power rail of each gate scale down. in future CMOS technologies,” in Proc. 7th Int. Workshop on Power and
Timing Modeling, Optimization and Simulation, Sep. 1997, pp. 235–244.
[9] ITRS (Int. Technology Roadmap for Semiconductors) 2004 Edition
V. CONCLUSION (2004). [Online]. Available: http://public.itrs.net
In this paper we have analyzed the different generation mech- [10] M. Badaroglu, P. Wambacq, G. Van der Plas, S. Donnay, G. Gielen, and
H. De Man, “Impact of technology scaling on substrate noise genera-
anisms of substrate noise under the size constraints of the circuit tion mechanisms,” in Proc. IEEE Custom Integrated Circuits Conf., Oct.
together with external (package) parasitics and depending on the 2004, pp. 501–504.
substrate grounding. We have also analyzed their evolution with [11] S. Kristiansson, S. P. Kagganti, T. Ewert, F. Ingvarson, J. Olsson, and K.
ITRS 2004 roadmap. By knowing the significance of all injec- O. Jeppson, “Substrate resistance modeling for noise coupling analysis,”
in Proc. IEEE Int. Conf. on Microelectronic Test Structures, Mar. 2003,
tions, a designer can choose the most efficient low-noise design pp. 124–129.
technique for enabling the integration of mixed-signal systems [12] Substrate Noise Analyst™ tool (2005). [Online]. Available: http://www.
in future CMOS technologies. cadence.com
The supply coupling will become an even more dominant [13] K. Sakui, S. S. Wong, and B. A. Wooley, “The effects of impact ioniza-
tion on the operation of neighboring devices and circuits,” IEEE Trans.
mechanism in future technology nodes when the substrate is di- Electron Devices, vol. 41, no. 9, pp. 1603–1607, Sep. 1994.
rectly biased with the digital ground. The relative ratio of the [14] BSIM3 Manual [Online]. Available: http://www-device.eecs.berkeley.
supply coupling current to the supply voltage will increase 4.5 x edu/~bsim
when a circuit is fabricated in a 22 nm technology node com- [15] S. M. Sze, Semiconductor Devices: Physics and Technology Second Edi-
tion. New York: Wiley, Sep. 2001.
pared to a 90 nm realization with the same package. This in- [16] M. Badaroglu, P. Wambacq, G. Van der Plas, L. Balasubramanian, K.
crease happens for circuits having their supply resonance fre- Tiri, I. Verbauwhede, S. Donnay, G. Gielen, and H. De Man, “Digital
quency larger than the inverse of their switching time. Other- circuit capacitance and switching analysis for ground bounce in ICs with
wise, the peak value of the supply coupling becomes depen- a high-ohmic substrate,” IEEE J. Solid-State Circuits, vol. 38, no. 7, pp.
1119–1130, Jul. 2004.
dent on the switching activity factor and not on the technology [17] M. Badaroglu, P. Wambacq, G. Van der Plas, S. Donnay, G. Gielen, and
scaling. The latter case is likely to dominate in future technology H. De Man, “Digital ground bounce reduction by supply current shaping
nodes. In this case, supply coupling can only be reduced by and clock frequency modulation,” IEEE Trans. Computer-Aided Design
adding more decoupling, by shaping the supply current, and/or Integr. Circuits, vol. 24, no. 1, pp. 65–76, Jan. 2005.
[18] G. Van der Plas, C. Soens, M. Badaroglu, P. Wambacq, and S. Donnay,
by reducing switching activity. “Modeling and experimental verification of substrate coupling and iso-
The use of KG can eliminate the dominance of supply cou- lation techniques in mixed-signal IC’s on a lightly-doped substrate,” in
pling but at the expense of an increase in the ground bounce Proc. of VLSI Circuits Symp., Jun. 2005.
Authorized licensed use limited to: University of Central Florida. Downloaded on November 8, 2008 at 21:36 from IEEE Xplore. Restrictions apply.
BADAROGLU et al.: EVOLUTION OF SUBSTRATE NOISE GENERATION MECHANISMS 305
[19] P. T. M. van Zeijl, J. W. Eikenbroek, P. P. Vervoort, S. Setty, J. Tangen- Stéphane Donnay (M’00) received the M.S. and
berg, G. Shipton, E. Kooistra, I. Keekstra, and D. Belot, “A Bluetooth Ph.D. degree in electrical engineering from the
radio in 0.18 m CMOS,” in IEEE Int. Solid-State Circuit Conf. Dig. Katholieke Universiteit Leuven (K.U. Leuven),
Tech. Papers, vol. 448, Feb. 2002, pp. 86–87. Leuven, Belgium in 1990 and 1998, respectively.
[20] R. H. Dennard, F. H. Gaensslen, V. L. Rideout, E. Bassous, and A. R. He was a Research Assistant in the ESAT-MICAS
LeBlanc, “Design of ion-implanted MOSFETs with very small physical Laboratory of K.U. Leuven from 1990 until 1996,
dimensions,” IEEE J. Solid-State Circuits, vol. SC-9, no. 5, pp. 256–268, where he worked in the field of analog and RF
Oct. 1974. modeling and design automation. In 1997. he joined
[21] J. R. Pfiester, J. D. Shott, and J. D. Meindl, “Performance limits of IMEC, where he is now a Program Director. His
CMOS ULSI,” IEEE J. Solid-State Circuits, vol. SC-20, no. 1, pp. current research interests include circuit and system
design in very deep submicron technologies, ultra-
253–263, Feb. 1985.
low-power radios for sensor networks, system-in-a-package integration of RF
front-ends and the modeling and simulation of substrate noise coupling in mixed-
signal integrated circuits. He has authored or coauthored more than 100 papers in
books, journals and conference proceedings. He is co-editor of Substrate Noise
Mustafa Badaroglu (S’00–M’05) received the Coupling in Mixed-Signal ASICs (Norwood, MA: Kluwer, 2003).
B.Sc.degree from Bilkent University, Ankara, Turkey, Dr. Donnay is a member of the Technical Program Committee of the Euro-
in 1995, the M.Sc. degree from Middle East Technical pean Solid-State Circuits Conference (ESSCIRC) since 2001. He was co-recip-
University, Ankara, Turkey, in 1998, and the Ph.D. ient of the best paper award at the Design, Automation and Test (DATE) con-
degree from Katholieke Universiteit Leuven, Leuven, ference in 2002 and 2004.
Belgium, in 2004, all in electrical engineering.
Since 1999, he has been with IMEC, Leuven, Georges G. E. Gielen (S’87–M’02–SM’99–F’02)
Belgium, where he is now a Senior Researcher. received the M.Sc. and Ph.D. degrees in electrical
From 1996 to 1998, he was a Researcher with the engineering from the Katholieke Universiteit Leuven
Scientific and Technical Research Council of Turkey (K.U. Leuven), Leuven, Belgium, in 1986 and 1990,
(TUBITAK), Ankara, Turkey, where he worked respectively.
on design and implementation of embedded microcontrollers, digital signal In 1990, he was appointed as a Postdoctoral Re-
processors, and several mixed-signal integrated circuits. At IMEC, he has search Assistant and Visiting Lecturer in the Depart-
worked on deep-submicron design automation, low-power design, and design ment of Electrical Engineering and Computer Sci-
and implementation of WLAN and UWB transceivers. His research interests ence, University of California, Berkeley. From 1991
include deep-submicron effects analysis/suppression, low-noise/power design, to 1993, he was a Postdoctoral Research Assistant of
and supply/clock networks. the Belgian National Fund of Scientific Research at
Dr. Badaroglu was the recipient of the 2004 European Design and Automation the ESAT Laboratory, K.U. Leuven. In 1993, he was appointed as a tenure Re-
Association (EDAA) doctoral dissertation award and of the Best Paper Award search Associate of the Belgian National Fund of Scientific Research and at the
at the Design, Automation and Test Conference (DATE) in 2004. same time as an Assistant Professor at the K.U. Leuven. In 2000 he promoted to
Full- Time professor at K.U. Leuven. His research interests are in the design
of analog and mixed-signal integrated circuits, and especially in analog and
mixed-signal computer-aided design tools and design automation (modeling,
simulation and symbolic analysis, analog synthesis, analog layout generation,
Piet Wambacq (S’89–M’91) was born in Asse,
analog and mixed-signal testing). He is coordinator or partner of several (indus-
Belgium, in 1963. He received the M.Sc. degree in
trial) research projects in this area. He has authored or coauthored four books
electrical and mechanical engineering and the Ph.D.
and more than 250 papers in edited books, international journals, and conference
degree from the Katholieke Universiteit Leuven
proceedings. He is Editor-in-Chief of the Integration Journal, and a member of
(K.U. Leuven), Leuven, Belgium, in 1986 and 1996,
the Editorial Board of the International Journal on Analog Integrated Circuits
respectively.
and Signal Processing.
From 1986 to 1996, he was a Research Assistant at
Dr. Gielen has been a regular member of the Program Committees of inter-
the ESAT-MICAS Laboratory, K.U. Leuven. Since
national conferences (DAC, ICCAD, ISCAS, DATE, CICC...). He received the
1996, he is with IMEC, Leuven, Belgium, working
1995 Best Paper Award from the International Journal on Circuit Theory and
as a Principal Scientist on design methodologies for
Applications, and was the 1997 Laureate of the Belgian Royal Academy on
mixed-signal and RF integrated circuits. He is also a
Sciences, Literature, and Arts in the discipline of Engineering. He received the
Lecturer at Vrije Universiteit Brussel, Brussels, Belgium. His research inter-
2000 Alcatel Award from the Belgian National Fund of Scientific Research for
ests are design and computer-aided design of mixed-signal and RF integrated
his innovative research in telecommunications. He is a the President of the IEEE
circuits. He has authored or coauthored two books and more than 100 papers
Circuits and Systems (CAS) society for the 2005–2006 term.
in edited books, international journals, and conference proceedings. He is the
co-inventor of two patents.
Dr. Wambacq is an Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS Hugo J. De Man (M’81–SM’81–F’86) is Professor
AND SYSTEMS—I: REGULAR PAPERS. He is the co-recipient of the Best Paper
of Electrical Engineering at the Katholieke Univer-
Award at the Design, Automation and Test Conference (DATE) in 2002 and siteit Leuven, (K.U. Leuven), Leuven, Belgium since
2004. He regularly is a member of the Program Committees of international 1976. In 1975, he was a Visiting Associate Professor
conferences (e.g., DATE). at the University of California, Berkeley, teaching
device physics and integrated circuit design. His
early research was devoted to the development of
mixed-signal, switched capacitor and digital signal
processing (DSP) simulation tools as well as new
Geert Van der Plas (S’01–M’03) was born in topologies for high-speed CMOS circuits. He is Co-
Merchtem, Belgium, in 1969. He received the M.Sc. founder of IMEC, where he was Vice-President from
and Ph.D. degrees from the Katholieke Universiteit 1984–1995, in charge of design methods for DSP and telecom oriented chip
Leuven (K.U. Leuven), Leuven, Belgium, in 1992 architectures. Since then, he is a Senior Research Fellow of IMEC, working on
and 2001, respectively. design methods for low-power post-PC systems in nanoscale technologies. The
From 1992 to 2001, he was a Research Assistant work of his research team at IMEC has lead to many novel tools and methods
with the ESAT-MICAS Laboratory of K.U. Leuven, in the area of high level synthesis, hardware-software co-design and C++ based
where he worked in the field of analog modeling and design now available through a number of spin-off companies.
design automation. In 2002, he was appointed as a Dr. De Man received the Technical Achievement Award of the IEEE Signal
Postdoctoral Research Assistant in the same research Processing Society, The Phil Kaufman Award of the EDA Consortium, and the
group. Since 2003, he has been with the Design Tech- Golden Jubilee Medal of the IEEE Circuits and Systems Society in 1999. In
nology Division of IMEC, Leuven, Belgium, where he is working on noise cou- 2004, he received the lifetime achievement awards, respectively, of the Euro-
pling in mixed-signal integrated circuits. His current research interests include pean Design and Automation Association (EDAA) as well as the European Elec-
deep-submicron signal integrity analysis and design of mixed-signal circuits. tronics Industry. He is a member of the Royal Academy of Sciences in Belgium.
Authorized licensed use limited to: University of Central Florida. Downloaded on November 8, 2008 at 21:36 from IEEE Xplore. Restrictions apply.