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spice simulation has to spent much time especially on the And A = cox W KT e2 l8 (1)
post layout simulation, and there are many input vectors for L eff q
the simulation of the multi-port cell. Therefore circuit
designers are anxious to have the model to estimate the Where Vg, Vs are gate voltage and source voltage,
VDS ,VTHis the thermal voltage, is the linearized body-
Supported by the National Natural Foundation of China for Distinguished
Young Scholars under Grant No.60325205, the National Natural Science
Foundation of China under Grant No. 60673146, 60603049, the National High
Technology Development 863 Program of China under No. 2006AA0 10201, and
the National Grand Fundamental Research 973 Program of China, National
Basic Research Program of China under No 2005CB32 1600; Supported by
Beijing Natural Science Foundation No.4072024
325
1-4244-0797-4/07/$20.OO ©¢ 2007 IEEE
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effect coefficient 9 is the Drain Induced Barrier III. SRAM leakage power analysis model
Lowering, Cox is gate capacitance/area, L and W are the
length and width of the transistors. where it o is the carrier Input Address
mobility and Leff is the effective gate length of the device. B
ffe
'sub =I X'°t X
xsI
(2)
Data
'off is the leakage current per micron of a single transistor Output
measured from actual silicon at a given temperature, Wtot is SsActivaion
Pulse Generator
_lSers
the total transistor width(sum of N and P devices), Xs is the
empirical stack effect, and Xt is the temperature factor.
'off and Xt are constants at some temperature, so how to Figurel. Typical architecture ofarray structure
compute the Wtot and Xs are the important factors. For the
Wtot, equation (3) shows: column memory cell array
SRAM core cell has several kinds of architectures, but
W0t/XXs= (W *f )/ Xs, (3) the most common architecture is the 6T cell since the 6T cell
is easy to be realized and has small area. SRAM core cells
f, being the frequency of its occurrence in the design. Xsi account for the major area in the cache design. So the
is the individual factor of one cell, from equation (2) and (3) leakage power of 6T cell is the significant factor affecting
we can get the 'sub the whole power.
Not only the subthreshold leakage is state dependent, The leakage current in arrays varies within a clock cycle
recent researches show that the gate leakage is also state depending on the phase of operation being performed, since
depended. While Isub depends on the number of OFF different transistors would be in off state. There are three
transistors in stack, Igate depends strongly on the position of operations to the SRAM, read, write and idle. The core cell
ON/OFF transistors in stack so different circuit input states just has two states in the three operations in fig2, fig3.
can lead to different Isub and Igate Read or Write
IDLERedoWrte
For simulation purposes, an oxide leakage model was 0
incorporated in an existing 100nm BSIM3v3 (level49) model _ WL
generated Berkeley Predictive Technology Model [8], Since
BSIM3 does not model oxide leakage, voltage dependent
current sources from the gate to source (Igs), and from the
gate to drain were implemented in the macro model, The DL - I' __ DL FL
dependence of these currents on gate to source voltage (V-) T
and gate to drain voltage (Vgd) is given by the following two -ubteo lekag
expressions: ^ g e kage
l7O X L 1l
127.04
Leff X e(5.60625xVg
e
0 06xTo,-2
lo 5) WL
gs 2 iL iK
Where T0x and Leff are given in nanometers and igs and igd Figure2. Leaking memory cell transistors in Idle and active operation phase
are given in iA per ptm of transistor width (assuming
minimum channel length). There are a lot of differences between the I,ub and Igate
approved by the above equations, from the most 6T cell
Since the gate to source and gate to drain overlap regions design we can see the number and the area of n-ch transistors
are much smaller than the channel region, the gate tunneling are larger than p-ch, the Igate is ignored especially to the thin-
current in the OFF state is much smaller than gate tunneling oxide gate. We analyze the 6T cell Isub and Igate at different
in the ON state. If SiO2 is used for the gate oxide, PMOS process; the data is in table t. The conclusion is that the gate
transistors will have about one order of magnitude smaller tunneling current effectively displaces the subthreshold
gate leakage than NMOS transistors. current, changing the ratio of the leakage current.
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Table I. Pattern sequences for leading one position libraries used in the design and secondly Simulate all the
Core 180nm 90nm 65nm (pA) cells exhaustively for average leakage currents and stacking
cell (pA) (pA) factors.
Igate Isub Igate Isub Igate Isub
Read 1.2e 8.2e 1.2e 1.8e 2.le 1.9e To the inverter, the subthreshold leakage power
or
Write II
+04 +04 +05 +05 +06 +06 A= I effective leakage width L = XWp
(Lp / u)
Idle 3.7e Lle 0.7e 2.5e 1.Oe 2.3e Thereforethe effectiveLequation is:
+03 +05 +05 +05 +06 +06
A rTB -
T A=O effective leakage width L n=
JnJL /u)
I Nmux
leakageT-- ~A+(Ctotal-Nmux -N
Nbit -Iactive b(, .) Ididle -B (5) Linv = Y/ Wp (Lp l u) + Y2 Wn (Ln lIu)
Table II Leakage Power Model Inputs To the nand2, leakage power model:
Parameter Description (the inputs ports are A and B)
Nmux SRAM bitline multiplexers
Nbit DataBits L -2W (L /u) A=1 B=
Ctotal The total capacity of SRAM 4
T The statistical time length
We can see the l'eakage power is dependent on the 'state of L 1
the SRAM work. If we want to get the accurate leakage -W
4 n (L nU) A - ,B-O
power, we have to consider the working frequency and data
refresh frequency and so on. In most high speed and high L = - W (L I u) A=O,B= 1
density SRAM the pulse of word line in "on" state becomes 4
shorter and shorter, the Tr is generally much less than the T1,
and the statistical data shows the most core cells are in the L = -W S L /u A=O,B=O
idle state for a long time even though SRAM is working in 4
written or read state (fig3). Therefore the equation (5) can be From the above equations, the nand2 effective L is:
advised as the following one (6):
The nand3 effective L is
'leakage Ctotai B(6)
L2nand - Y2 Wp (Lp I u) + 2 Wn (L/nIu)
Memory Cell Array The above equations show that Isub is much dependent on
_ X_I_ _I Lea}ak. Rtat Of Different the Xs is the ratio of different gates 'sub, and therefore we can
IFdl I nand2 Xs:
i get the
Xs ~2 (Lnnd 2 /Linv)
:-
Rows
~~~~~~~~~~~~~~If
we define the inv Xs is "1", the from the equation, to
aciethe nand3:.
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SRAM address decoder and clock generators are
combined of digital circuits so their Igate is different to a
certainty ratio. To compute the Igater O spice simulation
Stepl: compute the average gate leakage of unit cells E0algorithm
such as the inverter, nand, nor and so on. 0.6
Step2: Count the number of all cells and their width.
b' 0.4
Step3: Calculate the total gate leakage based on a -d
certainty ratio of various cells. 0. 2-
The above statistical method reflects the average gate
leakage current , if computing the maximum or minimum 018.
Igate, the method will be have some errors more than 50%. 180nm 130nm 90nm
process variation
65nm
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