Design of 256-Kb Low-Power Embedded SRAM

Seung-Ho Song, Jung-Hyun Kim, Jung-Chan Lee, and Yeonbae Chung

Abstract - This work presents a low voltage

SRAM design technique to increase the operating Cell power decoder ___.
margin. For each read/write cycle, the wordline and
cell power node of selected SRAM cells are boosted VPPCPL CPL
into two different voltage levels. This technique
ICELL
enhances the read static noise margin (SNM) to a
sufficient amount without an increase of cell size. It lDo-I
also improves the SRAM circuit speed owing to an
increase of the cell read-out current. A 0.18-pm W
CMOS 256-Kbit SRAM macro has been fabricated Local.row.decoder*-----
with the proposed technique. The chip operates with BL /BL
50 MHz at 0.8 V supply voltage. It consumes a power
of 65 piW/MHz. Measurement shows that the
proposed SRAM configuration achieves a reduction Cell
by 87 % in bit-error rate while operating with 43 %
higher clock frequency compared with that of
conventional SRAM. Write driver

I. INTRODUCTION DL
/LL
As mobile electronic systems become popular, Sense amplifiercs
power consumption is a major concern in VLSI chip Fig. 1. Configuration of 6-T SRAM cell array. (CS:
design. Although various techniques to reduce the column signal, DL: dataline, /DL: /dataline)
power dissipation have been developed [1], lowering
the supply voltage is the most effective way. The
SRAM is an important intellectual property block and Read Write ,1
occupies a large area in SoC. However, the VPPCPL VPPCPL
performance of SRAM is greatly affected by the CP VDD
operating voltage. The static noise margin (SNM), a o ------------------------------------------
measure of the SRAM cell stability, deteriorates with VPPWL VPPWL
reduction of the supply voltage [2]. It causes to WL VDD ------
increase the fail-bit rate of SRAM cell array. In O
addition, the SRAM cell current for data detection is VDD
also reduced, which degrades the operation speed of BL, /BL O
SRAM.
There have been several attempts to overcome the Fig. 2. Proposed bias conditions for read/write cycle.
degraded operating margin and degraded cell current
due to lowering the supply voltage [3]-[7]. In this work, CPL-
we propose and demonstrate a dual-boosted cell based CCell Cell Ce Cell in write
SRAM which can enhance both cell stability and cell WL; _ Cell
current to a sufficient amount. ele C m C C Cellindummyread
Row el eli ndm yra
II. DETAILS OF SRAM DESIGN CPLk _ _ _
Cell Cell Cell Ce Cell in standby
Fig. 1 shows a configuration of 6-T SRAM cell array k Selected
and Fig. 2 illustrates the proposed bias conditions on the Column
memory cell. Although the SRAM cell stability is BLj IBLj BLj 1B11 BLk IBLk
certainly important during standby mode, the SNM during Fig. 3. Status of memory cells in array during write
read operation represents a more significant limitation to operation.
SRAM operation [2]. In addition, both read SNM and cell
read-out current value are in an inverse correlation [4]. anie oipoebt eloeaigmri n h
__________________________________circuit speed is the following.
The authors are with the School of Electrical Engineering During the read operation, boosting the wordline
and Computer Science, the Kyungpook National University, (WL) voltage of selected cells above supply voltage
Daegu, Republic of Korea (E-mail: shsong@ee.knu.ac.kr). increases the driving capability of NMOS access

1-4244-0637-4/07/$20.OO ©C2007 IEEE 313

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 Precharger
t I Equalizer
l__________ Precharger
rec
-rGerEqualizer Precharger Equalizer
t-Precharger
rec Equalizerar er
Capacitor Driver Prebias Circuit
32-Kbit 32-Kbit 32-Kbit 32-Kbit VPB
Cell Array Cell Array Cell Array Cell ArrayPB (,B
~~~_j ito

(C1)
...

Mc
...
~~~~~~~~~~~~~~~~~~~~~~~~HcPRE,
CPL <$'|'P,<aPE

Prebias Circuit
T VDD
u 0 ~ ~~~
o ~VPPWL 0
im ~~~~~~~~-EPVPPCPL w B2D Capacitor
0 ground l<42lumns,
0 > ~~~~~~~~~~PRE3ED-OP2

Column GatelDecoder Column GatelDecoder Column GatelDecoder Column GatelDecoder Fig. ofbooster.
5. Configuration CPL

SAIWDR SAIWDR HV SAIWWDR SAIWDR HVSW ISAIWDR SAIWDR HVS; SAIWDR SAIWODR
WL BoosterC 1.6
1.4
--PRE2
Fig. 4. Configuration of a memory block. (MC: 1.2- VPB
memory cell, HVSW: high-voltage switch, SA: sense 1,1.0
amplifier, WDR: write driver).. 0.8-....
0
-

transistor. Thus it increases the cell read-out current 0.4 - -

(ICELL), resulting in reduced bitline (BL) delay time [3].0.

But the read SNM decreases. To compensate the reduced 0.0 ............. I

SNM, a higher voltage than the WL level is applied to the Time (ns) 20
cell power line (CPL), which improves the cell read Fig. 6. Simulation waveforms of CPL booster at VDD
stability with enlarged SNM. In this work, the WL 0.8 V
boosting level (VPPWL) and CPL boosting level (VPPCPL)
are chosen to be 1.5VDD and 2VDD, respectively.
Meanwhile, to achieve a good write operation in low sub-block, which limits the overall power consumption
voltage SRAM, an access transistor with strong driving due to voltage boosting only to a selected sub-block
capability and relatively weaker pull-up transistor are level. Fig. 5 shows the CPL booster providing 2VDD. It
desired [7]. However, during the write operation as shown consists of two stages of boosting circuitry which are
in Fig. 3, only one of interleaved columns is selected for serially connected by a high-voltage switch. As shown
write while cells from the remaining columns on a in Fig. 6, the voltage level of CPL is settled down to the
selected row will experience a dummy read operation. To target value in 5 ns after kicking boosting capacitors by
achieve the best read and write margin on the cells from a signal PB1.
selected row, the same bias conditions are attempted to Fig. 7 shows circuit simulations at 0.8 V. The
the memory cells as that of read operation. Boosting the cycle time is 20 ns for both read and write cycle. The
CPL voltage to 2VDD increases the read SNM of cells on internally boosted levels of CPL and WL are 1.6 V and
the dummy read operation, but disturbs the write 1.2 V, respectively. During read, the data out is
operation of cell on the selected column because the obtained after one clock cycle. The access time is 23 ns.
conductance of PMOS pull-up transistor becomes larger Even though the voltage level of CPL is higher than
[5]. To resolve it, a boosting voltage of 1.5VDD is applied that of WL during write, the cell internal nodes (DN,
to the WL, which improves driving capability of the /DN) flip the state in 2 ns after wordline access.
access transistor. With increased driving capability of
access NMOS, the cell internal node with data 'high' state III. EXPERIMENTAL RESULTS
can be driven closer to the ground through the bitline
during write, which makes cell flip state easily. The proposed techniques were implemented in a
Fig. 4 shows a memory array configuration based 256-Kbit SRAM, and fabricated with 0.18 ptm CMOS
on the proposed dual-boosted cell technique. The WL process technology. The chip photograph is shown in
booster providing 1 .5VDD iS composed of a simple Fig. 8. The organization is 32K-word x 8-bit. The
circuitry with a boosting capacitor. The cell array macro size is 1520 pim x 1490 pim =2.26 mm2. Fig. 9
design has been optimized for both boosting shows the relation between VDD and cycle time. The
performance and area efficiency. One array block has SRAM achieves a 50-MHz operating frequency at
four sub-blocks, each containing 512-row x 64-column. 0.8-V power supply. The power dissipation is 65
Each WL couples 64 cells. Each CPL is shared among piW/MHz. Fig . 10 displays the measured waveforms of
two up and down cells and runs parallel to the WL, SRAM data out for 40 ns clock cycle.
coupling 256 cells within two adjacent sub-blocks. Fig. 11 shows the measured butterfly curves for
High-voltage switch (HVSW) decoded by block both conventional and proposed scheme. At the supply
address supplies the boosting voltage to the selected voltageofO.8 V,the read SNM isfoundto beA60 mV

314
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 1.6
1.4 CLK
1.2
I..1...
0'ir
0
0.8 . |

0.6 E
_01.2 DN IDN / < \ Fig. 10. Measuredwavefor sforreadDOUT
0.0 ________,_________________
0 10 20
Time (ns)
(a)
~~ ~~ ~~~20nslIdiv

1.4
1.2 Fig. 1.0. Measured waveforms for read at VDD 0.8 V and
1.0 40 ns clock cycle.
0
0.6

I Fig.
lii 1. Measr:d / n: t * - r<s : V - 0.8 V. (a)
0.2 i l
0.0 -40r(
0 10 20
Time (ns) b
(b)
Fig. 7. Simulation waveforms
atpVDD 0.8 V and 20 ns
cycle: (a) read cycle and (b) write cycle. (CLK: clock t
signal, DN: data-node, /DN: /data-node)
VDN MV
Fig. 11. Measured butterfly curves at VDD =0.8 V: (a)
without cell boosting, (b) VPPWL 1.2 V, VPPCPL 1.6 V.

* * ~~~~~~~~~~~~~~50

40-

30-
E
ccc 20

Fig. 8. Chip microphotograph. 10 of the 35 et

0F
il

without1cell5boosting,.(b).VPPWL.1.2.V,.VPPCPL
(a)3
...............i.hecovetina.n bosig el. y ootig h
.................voltage.evel.of.W.and.CPLto.1.2.Vand.1.6.
.......................mV..Italso.icrease.the ell.re d-out.urren
......................SRAM..operating...frequencyI.is..43.....owing..to.the
incras of reas rd cell re ducurrent.atwa tonimDD by the
circuithsiut elation. ig bVPW
Fig. 9. Shmooplot. ~ ~~ Fig Meu12. ebifaslured cell eb read-ucrenatd VDDtVPP 0.8giV:
inthe prnenimnary bnefibofstheg proposed botecniquhei
Fig. 9. Shmoo
plot, to reduce bitf~~ailureinduAT ACeDT by read and writ mlargin.A

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 [5] M. Yamaoka, K. Osada, and K. Ishibashi, "0.4-V
Without cell logic-library-friendly SRAM array using
boosting rectangular-diffusion cell and delta-boosted-array
---
- - --- - - voltage scheme," IEEE J. Solid-State Circuits, vol. 39, pp.
934-940, 2004.
VPPWL = 1.2 V _____ _____[6] K. Zhang et al., "A 3-GHz 70-Mb SRAM in 65-nm
VPPCPL= 1.6V 87 % CMOS technology with integrated column-based
dynamic power supply," IEEE J. Solid-State Circuits, vol.
41, pp. 146-151, 2006.
0 0.2 0.4 0.6 0.8 1 [7] M. Yamaoka et al., "90-nm process-variation adaptive
Number of bit-fail (normalized) embedded SRAM modules with power-line-floating
write technique," IEEE J. Solid-State Circuits, vol. 41, pp.
Fig. 13. Measurements of bit-fail count at VDD = 0.8 V. 705-711, 2006.

It has been also measured from fabricated chips as

shown in Fig. 13. At 0.8-V operation, about 87 00
reduction in number of fail bits has been achieved by
boosting the cell dually.

IV. CONCLUSION
In order to improve the cell stability and the
SRAM circuit speed encountered with low voltage
SRAM, we have proposed a dual-boosting cell
technique which can enhance both cell SNM and cell
read-out current. For each read/write cycle, the
wordline and cell power node of selected SRAM cells
are internally boosted into 1.5VDD and 2VDD
respectively. A 256-Kbit SRAM test chip with the
proposed scheme has been fabricated in a 0.18-ptm
CMOS process, and demonstrated: 1) 0.8 V operation
with 50 MHz while consuming a power of 65
ptW/MHz; 2) 400 mV read SNM and 44 ptA cell current
at 0.8 V power supply; and 3) a reduction by 87 00 in
bit-error rate and 43 00 higher chip operating frequency
compared with that of conventional SRAM. Since the
memory chip yield is often determined by the failure
rate of memory cells, the proposed technique will be
able to provide a significant improvement in the
manufacturing die yield.

ACKNOWLEDGMENT
This work was supported in part by the 2'nd BK21
Project and the Korea Research Foundation Grant
funded by the Korean Government (MOEHRD)
(KRF-2006-33 1-D0032 1).

REFERENCES
[1] K. Itoh, K. Sasaki, and Y. Nakagome, "Trends on
low-power RAM circuit technologies," Proceedings of
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[2] B. Seevinck, F. J. List, and J. Lohstroh, "Static-noise
margin analysis of MOS SRAM cells," IEEE J.
Solid-State Circuits, vol. SC-22, pp. 748-754, 1987.
[3] H. Morimura and N. Shibata, "A step-down
boosted-wordline scheme for 1-V battery-operated fast
SRAM's," IEEE J. Solid-State Circuits, vol. 33, pp.
1220-1227, 1998.
[4] K. Takeda et al., "A read-static-noise-margin-free SRAM
cell for low-VDD and high-speed applications," IEEE J.
Solid-State Circuits, vol. 41, pp. 113-121, 2006.

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