AN-1191

APPLICATION NOTE
One Technology Way P.O. Box 9106 Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 www.analog.com

ADV7182 CMRR Measurements Across Frequency Using ADSP-BF527
by Witold Kaczurba

Rev. 0 | Page 1 of 8
INTRODUCTION
This application note describes techniques for measuring
the noise spectrum for video ADCs using the Blackfin ADSP-
BF527. An external noise can have negative impact on video
quality. Finding a source of noise might be difficult, especially
in the complex systems using digital processing and/or radio
frequency. The measurement is especially important in case of
differential video using long cable runs (such as in automotive
applications using reversing cameras with cables going from the
head unit to the back of the car).
The method described in this application note allows analysis
of noise across a frequency spectrum as well as measuring the
noise floor level of video ADC. For this purpose, the ADV7182
is set into raw ADC mode that constantly converts all incoming
analog signals into 10-bit digital codes output via pixel lines
{ P[7:0], HS, VS } with an accompanying clock. In this
particular mode, the synchronization signal is not processed.
The ADC is connected to a 10 kHz differential signal generator
providing a reference 1 V peak-to-peak signal.
The ADSP-BF527 (or similar) acts as a data grabber trans-
ferring samples straight to the SDRAM. Once collected, data
can be transferred to a PC for further processing and to
perform FFT.
SINE WAVE
GENERATOR
(DIFFERENTIAL)
ADV7182
AIN+
AIN
DATA
CLK
ADSP-BF527
EXTERNAL
SDRAM
MEMORY
PC WITH
MATLAB,
PYTHON, OR
OCTAVE
USB
1
1
4
8
5
-
0
0
1

Figure 1. Simplified Setup













AN-1191 Application Note

Rev. 0 | Page 2 of 8
TABLE OF CONTENTS
Introduction ...................................................................................... 1
CMRR Measurement ....................................................................... 3
ADV7182 Script and Schematics ....................................................3
Blackfin as a Data Grabber ...............................................................5

REVISION HISTORY
6/13Revision 0: Initial Version


































Application Note AN-1191

Rev. 0 | Page 3 of 8
CMRR MEASUREMENT
The measurements of CMRR must be performed across
frequency. Factors that can have an impact on measurements
are differential pairs that are not kept together, termination
mismatch, and layout practices. The input resistor matching
has a crucial effect on CMR measurement. Matching should
be of 0.1% accuracy.
Test 1: Adjusting and Collecting Data for Single-Ended
Signal
During the first measurement test, a sine wave of known
frequency should be applied to one of the terminals (AIN+)
whereas the other should be connected to ground. The ampli-
tude of the sine wave should be adjusted to utilize the full range
of the ADC, without saturating the ADC. The digital data
should be collected using a digital grabber.
Test 2: Measuring
During the second measurement, a sine wave of the same
frequency and amplitude as in the first test should be applied
to both terminals. Common-mode rejection of the ADC amp
will reject the sine wave.
Result
In order to quantify results, data collected from the digital
output from the first and the second test should be plotted in
a semi-logarithmic scale showing absolute FFT values across
frequency. The comparison between plots from Test 1 and
Test 2 should provide information on how common mode is
rejected. Since this data is presented in a logarithmic scale
subtracting the result of Test 1 from the result from Test 2 for
the particular frequency should result in the CMRR in dB. The
code presented in Listing 3 has been adjusted to show the peak-
to-peak sine wave at 0 dB. The example shown in Figure 2 and
Figure 3 shows 59 dB CMRR attenuation for 1% resistors. Lab
results with 0.1% matched resistors showed 70 dB attenuation.
The data used for these figures has been generated for
illustration purposes.
0
20
40
60
80
100
120
140
160
0 500k 1.0M 1.5M 2.0M 2.5M
S
P
E
C
T
R
U
M

(
d
B
)
FREQUENCY (Hz)
1
1
4
8
5
-
0
0
2

Figure 2. Sine Wave (45772 Hz) of Full 10-Bit Range Adjusted to 0 dB
180
160
140
120
100
80
60
300k 400k 500k 600k 700k
S
P
E
C
T
R
U
M

(
d
B
)
FREQUENCY (Hz)
1
1
4
8
5
-
0
0
3

Figure 3. Frequency Spectrum Shows a 59 dB Spike
at 45772 Hz (Synthesized Data)
ADV7182 SCRIPT AND SCHEMATICS
The following script sets the ADV7182 in ADC sampling mode,
using CVBS_P on AIN1 and CVBS_N on AIN2. Figure 3 shows
the schematic that includes input recommended termination for
the ADV7182 as well as connection to ADSP-BF527 capturing
the data (Port F and Port J).

AN-1191 Application Note

Rev. 0 | Page 4 of 8
Listing 1. Special ADV7182 I
2
C Writes
42 0F 00 ; Exi t Power Down Mode
42 00 0E ; I NSEL = CVBS_P i n on Ai n 1, CVBS_N i n on Ai n2
42 02 04 ; Anal og St andar d Sel ect i on
42 07 00 ; Aut o- det ect of f
42 03 0C ; Enabl e Pi xel & Sync out put dr i ver s
42 1D 40 ; Enabl e LLC out put dr i ver
42 13 00 ; Enabl e I NTRQ out put dr i ver
42 64 10 ; Power up Xt al pat h
42 14 00 ; Speci al ADC t est mode
42 52 C0 ; Speci al ADC t est mode
42 5F 08 ; Speci al ADC t est mode
42 6C 80 ; Speci al ADC t est mode
42 60 A0 ; Speci al ADC t est mode
42 28 80 ; Speci al ADC t est mode
42 1D 40 ; Speci al ADC t est mode
Locate cl ose to DUT and same si de as DUT
Locate cl ose to DUT
and same si de as DUT
Al l decoupl i ng capaci tors to be l ocated cl ose to ADV7182
Reset
Power Supply Decoupling
To Blackfin
1
D
G
N
D
2
D
V
D
D
I
O
3
D
V
D
D
4
D
G
N
D
5
P7
6
P6
7
P5
8
P4
9
P3
10
P2
11
P1
12
P0
1
3
D
V
D
D
14
XTALP
15
XTALN
1
6
P
V
D
D
17
AIN1
18
AIN2
19
VREFP
20
VREFN
2
1
A
V
D
D
22
AIN3
23
AIN4
24
INTRQ
25
RESET
26
ALSB
27
SDATA
28
SCLK
29
VS/FIELD/SFL
30
HS
31
PWRDWN
32
LLC
3
3
E
P
A
D
U2
ADV7182/7280
INTRQ
Y
1
2
8
.
6
3
6
3
6
M
H
z
C18
47pF
C17
47pF
R
1
N
I
C
2
N
I
C
3
N
I
R5
4K7
C14
0.1uF
R6
33r
C37
0.1uF
C38
10nF
C39
0.1uF
C40
10nF
C41
0.1uF
C42
10nF C44
0.1uF
C45
10nF
C46
10nF
C47
0.1uF
R37
4K7
C63
4.7uF
S2
R41
4K7
R30-A 33r
R30-B 33r
R30-C 33r
R30-D 33r
R31-A 33r
R31-B 33r
R31-C 33r
R31-D 33r
J3
J2
C
5
0
.
1
u
F
C
6
0
.
1
u
F
J4
J6
R28
430r
R29
430r
R33 1K3
R35 1K3 C
8
0
.
1
u
F
C
1
9
0
.
1
u
F
R20
75r
R2
75r
R7 1K3
R8 1K3
R9
430r
R10
430r
GND
DVDD_1.8V PVDD_1.8V
PF0
PF1
AIN1
AIN2
AIN3
AIN4
SDA
SCL
GND
DVDDIO_3.3V
DUT_RESET
DVDD_1.8V
GND
AVDD_1.8V
GND
DVDDIO_3.3V PVDD_1.8V
GND
GND
DUT_RESET
GND
DVDDIO_3.3V
G
N
D
G
N
D
PJ1/PPICLK
DVDDIO_3.3V
AVDD_1.8V
DVDDIO_3.3V
GND
GND
GND
GND
GND
G
N
D
PF2
PF3
PF4
PF5
PF6
PF7
PF8
PF9
1
1
4
8
5
-
0
0
4

Figure 4. ADV7182 Connection to Blackfin


Application Note AN-1191

Rev. 0 | Page 5 of 8
BLACKFIN AS A DATA GRABBER
The Blackfin family features a parallel port interface (PPI)
allowing for bidirectional parallel data transfers of various
types. Those include video transfers such as BT656, raw data
with and without additional external synchronization signals.
Since the ADV7182 is configured in raw ADC mode (without
processing synchronization signals), the Blackfin must be
configured to receive incoming raw data, without external
synchronization signals, with a clock rate 27.0 MHz or
28.6363 MHz. The built-in PPI interface is configured to
perform data transfers facilitating DMA mechanism allowing
for direct transfer to external SDRAM memory. The Blackfins
core does not participate therefore in receiving data and can be
occupied to execute other code.
Displaying and Analyzing Data on the PC
One of the easiest ways of performing FFT and displaying
graphical representation without buying an expensive math-
ematical package is Python(x, y). This software package
contains tools and libraries for mathematical calculations and
provides visual representation (charts, plots, and so on). The
package allows the performance of fast Fourier transforms and
displays this information in a very quick and convenient way on
a PC.
Blackfin Connection to PC over USB
The Blackfin DSP processor family offers a USB interface and a
UART connectivity that can be used for data transfer to the PC
and to maintain link. Blackfins USB interface. It can be
programmed to work in a number of various modes, including
CDC, HID, mass storage, or general bulk.
This application note outlines how to modify existing Visual
DSP++ 5.0 USB examples into general bulk mode allowing for
data transfer with a PC. The example is based on the ADSP-
BF527, but can be easily transferred to suit other USB
interfaces.
Blackfin Code
The original source code covered in the VDSP++ examples
allows for a number of certain USB commands. In order to
facilitate ADV7182 programming via an I
2
C interface and
setting Blackfins PPI mode that grabs the data, three additional
commands were added into the code: CONFIGURE_ADV,
GRAB_DATA, and READ_VIDEO_DATA. The first one
configures the ADV part using the I
2
C interface (See Listing 1)
into RAW-ADC mode in which data is sampled at the XTAL
clock frequency and output to the pixel output port without
processing syncs. The next function configures the PPI interface
to read data from the pixel port (refer to Listing 2). The last one
(READ_VIDEO_DATA) allows data to be sent to the host
computer.
AN-1191 Application Note

Rev. 0 | Page 6 of 8
Listing 2. PPI Configuration
/ / Conf i gur i ng PPI pi ns PF0. . PF15 t o PPI
*pPORTF_MUX = 0x0000;
*pPORTF_MUX | = ( 1 << 12) ; / / Enabl e PPI CLK pi n
*pPORTF_FER = 0xFFFF; / / PF0. . PF15 t o PPI f unc.
/ / Zer oi ng r egi st er s i n case t he hol d pr evi ous val ues
*pPPI _CONTROL = 0;
ssync( ) ;
*pDMA0_CONFI G = 0;
ssync( ) ;
/ / Conf i gur i ng PPI and DMA:
/ / X_COUNT: 1024 sampl es * 2 byt es = 2048 byt es per l i ne
/ / Y_COUNT: 1024 l i nes * 2048 byt es = 2097152 byt es t ot al
*pDMA0_START_ADDR = f r ame_r aw_buf f er 1;
*pDMA0_X_COUNT = 1024;
*pDMA0_Y_COUNT = 1024;
*pDMA0_X_MODI FY = 2; / / 2 byt e dat a
*pDMA0_Y_MODI FY = 2;
*pDMA0_CONFI G=FLOW_STOP| DMA2D| WDSI ZE16| WNR;
ssync( ) ;
/ / PPI Conf i gur at i on ( uses onl y PPI CLK, no f r ame syncs)
/ / 16- bi t dat a, 0 f r amesync wi t h i nt er nal t r i gger , PPI r ecei ver
*pPPI _CONTROL=DLEN_16| FLD_SEL| PORT_CFG| XFR_TYPE;
*pPPI _DELAY = 0;
*pPPI _COUNT = 1024 - 1;
ssync ( ) ;
/ / Enabl i ng DMA and PPI
*pDMA0_CONFI G | = DMAEN; / / Enabl e DMA0
ssync( ) ;
*pPPI _CONTROL | = PORT_EN; / / Enabl e PPI
ssync( ) ;
The VDSP++ project can be downloaded from Analog Devices
EngineeringZone.
Host Application
The host application has been simply extended to match
additional functions that Blackfin offers. CONFIGURE_ADV,
GRAB_DATA require no additional data to be transferred,
whereas function READ_VIDEO_DATA splits the 2 megabytes
buffer into a number of 65536-byte long transmission bulks.
All functions were implemented in Visual C++ in a manner
allowing for execution from the command line.
host app. exe - b
Configures ADV7182 part
host app. exe - g
Configures Blackfin for grabbing
data
host app I FI LE
START COUNT
Dumps the COUNT-bytes from the
device to FILE at START address

The received file contains 16-bit data grouped into 2-byte codes,
with the first byte representing the less significant byte (PF7 to
PF0) and then the most significant byte (PF15 to PF8).
Processing the Received Data
Once received, data can be processed and its frequency
spectrum can be shown using the PC. Listing 3 shows the
simplified processing of a file containing captured data and
displaying its frequency spectrum. The code is written in
Python(x,y). For simplicity, the example does not apply to
windowing or any filtering.
Application Note AN-1191

Rev. 0 | Page 7 of 8
Listing 3. Example Python(x,y) Script
i mpor t t i me
f r ompyl ab i mpor t pl ot , show, t i t l e, xl abel , yl abel , subpl ot
f r omsci py i mpor t f f t , ar r ange
f r ommat h i mpor t l og10
Fs = 28. 6363E6
pi x_scal e = 4
def newl og10( x) :
# Returns -90dB for log10(0) - in case FFT outputs zeros
i f x == 0:
r et ur n - 90 # - 90dB
r et ur n l og10( x)
def scal e_down( dat a, pi x_scal e) :
out put = [ ]
i f pi x_scal e <> 1:
f or i i n r ange( 0, l en( dat a) , pi x_scal e) :
out put . append( r ound( sum( dat a[ i : i +pi x_scal e] ) / f l oat ( pi x_scal e) ) )
r et ur n out put
r et ur n dat a
def show_pl ot s( dat a, t , Fs=28. 6363E6, f ct r =242) :
gl obal pi x_scal e
subpl ot ( 2, 1, 1) # plotting signal in time-domain
pl ot ( t [ : : pi x_scal e] , scal e_down( dat a, pi x_scal e) )
xl abel ( ' Ti me' )
yl abel ( ' Ampl i t ude' )
subpl ot ( 2, 1, 2)
Y = abs( f f t ( dat a) )
f or i i n r ange( 0, l en( Y) / 2) :
Y[ i ] = ( ( f l oat ( Y[ i ] ) ) / ( l en( Y) ) ) / f ct r
Y = Y[ r ange( l en( Y) / 2) ] # t r i mmi ni g t o f i r st hal f
f r q = ar ange( l en( Y) ) / f l oat ( l en( Y) ) * ( Fs / 2)
f or i i n r ange( 0, l en( Y) ) : # displaying in semi-log-scale
Y[ i ] = 20 * newl og10( Y[ i ] )
pl ot ( f r q, Y, ' r ' ) # plotting signal in frequency-domain
xl abel ( ' Fr eq ( Hz) ' )
yl abel ( ' l og10| Y( f r eq) | ' )
show( )

def r ead_f i l e( f i l ename, nbi t s=10) :
f = open( f i l ename, ' r b' )
bi n_dat a = f . r ead( )
dat a = [ ]
f or i i n r ange( 0, l en( bi n_dat a) - 1, 2) :
bi t _mask = ( 2<<( nbi t s- 1) ) 1
cur _val ue = ( ( or d( bi n_dat a[ i ] ) + ( or d( bi n_dat a[ i +1] ) *\ 256) ) & bi t _mask)
dat a. append( cur _val ue)
r et ur n dat a

# Main part:
dat a = r ead_f i l e( ' dat a. bi n' , 10)
f or i i n r ange( 0, l en( dat a) ) : # remove DC component
dat a[ i ] = dat a[ i ] 512
t = ( ar ange( 0, l en( dat a) ) ) / ( Fs) # 1Msampl es
show_pl ot s( dat a, t )
AN-1191 Application Note

Rev. 0 | Page 8 of 8
50
200
150
100
50
0
0 16 14 12 10 8 6 4 2
S
P
E
C
T
R
U
M

(
d
B
)
FREQUENCY (MHz)
1
1
4
8
5
-
0
0
1

Figure 5. Frequency Spectrum 0 MHz to 14.31 MHz for 10 kHz Sine Wave
50
150
100
50
0
0 40 30 20 10
S
P
E
C
T
R
U
M

(
d
B
)
FREQUENCY (kHz)
1
1
4
8
5
-
0
0
6

Figure 6. Frequency Spectrum 0 kHz to 50 kHz for 10 kHz Sine Wave







































I
2
C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

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registered trademarks are the property of their respective owners.
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