Hardware

Description
Languages
Outline
HDL Overview
Why not use C?
Concurrency
Hardware datatypes / Signa resoution
Connectivity / Hierarchy
Hardware si!uation
"asic #HDL Concepts
"asic #eriogHDL Concepts
Syste!C $ntroduction
Syste!#eriog $ntroduction
CMOS VLSI Design
4th Ed.
HDL Overview
Hardware Description Languages
%sed to !ode digita syste!s
Can !ode anything &ro! a si!pe gate to a
co!pete syste!
Support design hierarchy
Support Hardware Design 'ethodoogy
Can !ode rea hardware (synthesi)a*e+
Can !ode *ehavior ony (e,g, &or test+
"oth are non-proprietary. $/// standards
"ehaviora and structura coding styes
CMOS VLSI Design
4th Ed.
Basic Design Methodology
Requirements
RTL Model Simulate
Device Libraries
Synthesize
Gate-level
Model
Simulate Test Bench
ASI or !"GA
"lace # Route
Timin$
Model
Simulate
CMOS VLSI Design
4th Ed.
Why Not Use C or C++?
HDLs need to support characteristics o& rea
hardware
Concurrency
Hardware datatypes / Signa resoution
Connectivity / Hierarchy
Circuit ti!ing
HDLs !ust support hardware si!uation
0i!e
Cyce-accurate or /vent-driven (&or si!uation
speed+
1ote2 C33 has *een e4tended &or hardware
Syste!C
CMOS VLSI Design
4th Ed.
Basic Coparison
Verilog
Si!iar to C
5opuar in co!!ercia.
on coasts o& %S
Designs contained in
!odues
VHDL
Si!iar to 6da
5opuar in 'iitary.
!idwest %S
Designs contained in
entity architecture
pairs
CMOS VLSI Design
4th Ed.
Concurrency
HDLs must support concurrency
7ea hardware has !any circuits running at the
sa!e ti!e8
0wo *asics pro*e!s
Descri*ing concurrent syste!s
/4ecuting (si!uating+ concurrent syste!s
CMOS VLSI Design
4th Ed.
Descri!ing Concurrency
'any ways to create concurrent circuits
initia/aways (#eriog+ and process (#HDL+
*oc9s
Continuous/concurrent assign!ent state!ents
Co!ponent instantiation o& other !odues or
entity/architectures
0hese *oc9s/state!ents e4ecute in parae in every
#HDL/#eriog design
CMOS VLSI Design
4th Ed.
"#ecuting Concurrency
Si!uations are done on a host co!puter e4ecuting
instructions se:uentiay
Soution is to use ti!e-sharing
/ach process or aways or initia *oc9 gets the
si!uation engine. in turn. one at a ti!e
Si!iar to ti!e-sharing on a !uti-tas9ing OS. with
one !a;or di&&erence
0here is no i!it on the a!ount o& ti!e a given
process gets the si!uation engine
7uns unti process re:uests to give it up (e,g,
wait+
CMOS VLSI Design
4th Ed.
$rocess %ules
$& the process has a sensitivity ist. the process is
assu!ed to have an i!picit wait state!ent as the
ast state!ent
/4ecution wi continue (ater+ at the &irst
state!ent
6 process with a sensitivity ist must not contain an
e4picit wait state!ent
CMOS VLSI Design
4th Ed.
&ensitivity List
With Explicit List
XYZ_Lbl: process (S1, S2)
begin
S1 <= 1;
S2 <= 0 after 10 ns;
end process XYZ_Lbl;
Without Explicit List
XYZ_Lbl: process
begin
S1 <= 1;
S2 <= 0 after 10 ns;
wait on S1, S2;
end process XYZ_Lbl;
CMOS VLSI Design
4th Ed.
!o"#lete
#ro!1: process (a, b, !)
begin
$ <= a and b and !;
'ncoplete &ensitivity Lists
Logic si!uators use
sensitivity ists to
9now when to
e4ecute a process
5er&ecty happy not
to e4ecute proc<
when c changes
1ot si!uating a =-
input 61D gate
though8
What does the
synthesi)er create?
end process;
in!o"#lete
#ro!2: process (a, b)
begin
$ <= a and b and !;
end process;
CMOS VLSI Design
4th Ed.
!
Datatypes
CMOS VLSI Design
4th Ed.
#eriog has two groups o& data types
1et 0ype physica connection *etween
structura ee!ents
#aue is deter!ined &ro! the vaue o& its drivers.
such as a continuous assign!ent or a gate output
wire/tri. wor/trior. wand/triand. trireg/tri>/tri?. suppy?.
suppy>
#aria*e (7egister+ 0ype represents an
a*stract data storage ee!ent
6ssigned a vaue in an aways or initia state!ent.
vaue is saved &ro! one assign!ent to the ne4t
reg. integer. ti!e. rea. reati!e
Datatypes
CMOS VLSI Design
4th Ed.
#HDL categori)es o*;ects in to &our casses
Constant an o*;ect whose vaue cannot *e
changed
Signa an o*;ect with a past history
#aria*e an o*;ect with a singe current vaue
@ie an o*;ect used to represent a &ie in the host
environ!ent
/ach o*;ect *eongs to a type
Scaar (discrete and rea+
Co!posite (arrays and records+
6ccess
@ie
Hierarchy
CMOS VLSI Design
4th Ed.
1on-trivia designs are deveoped in a hierarchica
&or!
Co!pe4 *oc9s are co!posed o& si!per *oc9s
VHDL Verilog
/ntity and architecture 'odue
@unction @unction
5rocedure 0as9
5ac9age and pac9age *ody 'odue
Hardware &iulation
CMOS VLSI Design
4th Ed.
6 concurrent anguage aows &or2
'utipe concurrent ee!ents
6n event in one ee!ent to cause activity in
another
6n event is an output or state change at a
given ti!e
"ased on interconnection o& the ee!entAs
ports
Logica concurrency B so&tware
0rue physica concurrency B e,g,. CD in #eriog
Discrete (ie &iulation
'odes evauated and state updated ony at
ti!e intervas B n
/ven i& there is no change on an input
/ven i& there is no state to *e changed
1eed to e4ecute at &inest ti!e granuarity
'ight thin9 o& this as cyce accurate B things ony
happen
E(posedge coc9+
Fou coud do ogic circuits this way. *ut either2
Lots o& gate detai ost B as with cyce accurate
a*ove (no gates8+
Lots o& si!uation where nothing happens B every
gate is e4ecuted whether an input changes or not,
CMOS VLSI Design
4th Ed.
Discrete "vent &iulation
Discrete /vent Si!uationGaso 9nown as
/vent-driven Si!uation
Ony e4ecute !odes when inputs change
5ic9s up si!uation e&&iciency due to its seective
evauation
Discrete /vent Si!uation
/vents B changes in state at discrete ti!es, 0hese
cause other events to occur
Ony e4ecute so!ething when an event has occurred
at its input
/vents are !aintained in ti!e order
0i!e advances in discrete steps when a events &or a
given ti!e have *een processed
CMOS VLSI Design
4th Ed.
Discrete "vent &iulation
Huic9 e4a!pe
Iate 6 changes its output,
Ony then wi " and C e4ecute
O*servations
"J
6J
CJ
0he ee!ents in the diagra! donAt need to *e ogic
gates
D/ si!uation wor9s *ecause there is a sparseness
to gate e4ecution B !ay*e ony ><K o& gates
change at any one ti!e,
0he overhead o& the event ist then pays o&&
CMOS VLSI Design
4th Ed.
&ynthesis
0ransates register-trans&er-eve (70L+ design into
gate-eve netist
7estrictions on coding stye &or 70L !ode
0oo dependent
CMOS VLSI Design
4th Ed.
Basic )erilog Concepts
$nter&aces
"ehavior
Structure
CMOS VLSI Design
4th Ed.
* +ate Level Model
6 #eriog description o& an S7 atch
6 !odue is de&inedJ
na!e o& the !odueJ
!odue nandLatch
(output :. :"ar.
input set. reset+L
nand M<
0he !odue has ports
that are typedJ
type and deay o&
pri!itive gatesJ
g> (:. :"ar. set+.
g< (:"ar. :. reset+L
end!odue
pri!itive gates with
na!es and
interconnectionsJ
CMOS VLSI Design
4th Ed.
* Behavioral Model , -&M
H<J
NJ
H>J
H< J
coc9J
resetJ
D>J
H>J
OJ
resetJ
D<J
H<J
resetJ
CMOS VLSI Design
4th Ed.
Organi.ation /or -&M
0wo aways *oc9s
One &or the co!*inationa ogic B ne4t state and
output ogic
One &or the state register
CMOS VLSI Design
4th Ed.
Behavioral &peci/ication
module FSM (x, z, clk, reset);
input clk, reset, x;
outputz;
reg [1:2] , d;
reg z;
aways J
E(posedge c9 or negedge reset+J
i& (Preset+J
: CD ?LJ
ese : CD dLJ
aways E(4 or :+J
*eginJ
dQ>R D :Q>R S 4 T :Q<R S 4LJ
dQ<R D :Q>R S 4 T P:Q<R S 4LJ
) D :Q>R S :Q<RLJ
endJ
endmodule
!"e seuenti#l p#rt
(t"e $ %lip %lop)
!"e com&in#tion#l
logic p#rt
next st#te
output
CMOS VLSI Design
4th Ed.
&ysteC
C33 cass i*rary deveoped to support syste! eve
design (/ectronic Syste! Leve. /SL+
$ntended to cope with *oth hardware and so&tware
$/// >UUU Standard
Supports concurrency. hierarchy. signas. ti!e
Supports transaction eve !odeing
Supported nativey *y 'odesi!
CMOS VLSI Design
4th Ed.
&yste)erilog
CMOS VLSI Design
4th Ed.
)erilog,01
CMOS VLSI Design
4th Ed.
)HDL %icher (han )erilog
CMOS VLSI Design
4th Ed.
C Can2t Do Hardware
CMOS VLSI Design
4th Ed.
)erilog,3445
CMOS VLSI Design
4th Ed.
)eri/ication and Modeling
CMOS VLSI Design
4th Ed.
&yste)erilog6 Uni/ied Language
CMOS VLSI Design
4th Ed.
Constrained %ando
CMOS VLSI Design
4th Ed.
Basic Constraints
CMOS VLSI Design
4th Ed.
Weighted %ando Case
CMOS VLSI Design
4th Ed.
$rogra Bloc7
CMOS VLSI Design
4th Ed.
Why Use *ssertions?
Li!itations o& Directed testing
0o *e practica. testing has to *e high eve
Locating a ogic error can ta9e a ot o& ti!e
1ew tests !ay need to *e written to cose in on
&aiure
Signa reationships are co!pe4 and ower eve,
6ssertions target interesting signa
reationships
Li9e handsha9e signas. *us protocos etc,
/4ecute in parae with #eri&ication tests
/&&icienty capture #eri&ication $5 (*us protocos etc+
O&ten reusa*e across design and/or pro;ect
CMOS VLSI Design
4th Ed.
What *ssertions Can Do
@ind ogic errors earier
Detect ow-eve errors that &unctiona tests !iss
/4picity indicate ti!e when a &aiure occurs
/4picit hierarchica ocations and signa na!es
Coverage o& e4pected or une4pected events
6ssertions coverage per!its uses *eyond
chec9ing
How !any ti!es an event occurs
5roo& that a negative event did 1O0 happen
CMOS VLSI Design
4th Ed.
*ssertions
CMOS VLSI Design
4th Ed.
More Concise (han )HDL
CMOS VLSI Design
4th Ed.
*ssertion Based )eri/ication
'a9e 6ssertions part o& Design and #eri&ication &ows
V /!*ed design assu!ptions into the design
V 5ace protoco S &unctiona spec chec9s outside (*ind+
V 'a9e use o& 6ssertion Coverage data
Consider 6ssertions in 0est 5an
V $denti&y 9ey protocos and target-a*e *oc9s
V $nput assu!ptions. Output e4pectations
V Leverage 6ssertion Li*raries &irst
V O#L. H#L. Chec9erware
V Write custo! 6ssertions (e,g S#6+
V /4pertise and training
CMOS VLSI Design
4th Ed.
*ssertion Characteristics
6uto!ated chec9s on signa *ehavior S
&unctionaity
"ooean state!ent that speci&ies the ogica
reationship *etween a set o& signas over a
speci&ied period o& ti!e
Chec9s per&or!ed at user-speci&ied intervas
(sa!pe points+
property pWoneWhotL
E(posedge C9+ disa*e i&&(7eset+
Xonehot( Yvar>. var<. var=Z +L
endproperty
r4W&s!WoneWhot 2 assert property( pWoneWhot +L
CMOS VLSI Design
4th Ed.
"!edded *ssertions
0hese are assertions e!*edded in procedura
code
$dea &or designers a!ost i9e active
co!!ents
'ust have write access to the source-code to
add these
Li9ey to *e o& use O1LF to si!uator toos
aways E (posedge c9+
i& (cond>WisW!et+G
i& (cond<WisW!et+*egin
accessWgrant D re:uest> TT re:uest<L
assert(accessWgrant+L
CMOS VLSI Design
4th Ed.
Concurrent *ssertions
0hese are assertions outside o& procedura code
$dea &or #eri&ication - 1o source-code access
re:uired,
0otay independent o& design (*ac9-*o4
chec9ing+
%sed *y si!uation and other toos
property pWoneWhotL
E(posedge C9+ disa*e i&&(7eset+
Xonehot( Yvar>. var<. var=Z +L
endproperty
r4W&s!WoneWhot 2 assert property( pWoneWhot +L
CMOS VLSI Design
4th Ed.
De!ugging *ssertions
6ssertions are co!pact code structures
Chaenging to write. even !oreso to de*ug
1eed good toos to hep visuai)e the assertion
Huesta has power&u visuai)ation and de*ug toos
6naysis pane
V Lists a assertions at current hierarchica eve and their
stats,
Wave&or! #iew o& assertion and itAs signas
V Cear indication o& status2 active/inactive/pass/&ai
0hread #iew
V deco!poses assertions cause *y cause &or easy de*ug
CMOS VLSI Design
4th Ed.
*ssertion &uary
Li!ited visi*iity to signas within SOCAs
One contri*utor to the #eri&ication gap
6ssertion "ased #eri&ication is a soution
Huesta supports 6ssertion "ased #eri&ication
$ndustry eading i!pe!entation o& S#
V OO5. @unctiona Coverage etc,
V "roadest 6ssertion Li*rary support
V S# 6ssertions
Co!prehensive de*ug toochain
V 6ssertion 5ane
V Wave&or! dispay o& assertions
V 6ssertion 0hread #iewer
CMOS VLSI Design
4th Ed.