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11.

3 A Variable Gain CMOS Amplifier with Exponential Gain Control

Christopher W. Mangelsdorf
Analog Devices, Japan
1-16-1 Kaigan, Minato-ku
Tokyo 105-6891 Japan
phone: 8 1-3-5402-8254
fax: 81-3-5402- 1065
chris.mangelsdorf@analog.com

Abstract

A variable gain amplifier architecture suitable for foundry


CMOS is constructed using linearized transconductance
blocks. The use of a four-transistor transconductance cell
allows for wider gain range and larger signal swing under low
supply conditions than the simple differential pair used in
previous work. Experimental results with 0.6 um CMOS
show -5 to 35 dB gain and 20 MHz bandwidth at 21 mW.

Introduction

High speed analog signal processing channels in hard disk Figure 1


drives and CCD imaging equipment make use of variable
gain amplifiers (VGAs) for adaptive control of signal If the bias is arranged so that the current in one pair
amplitudes under a wide variety of conditions. System increases as the current in the other pair decreases, the
requirements dictate that the best choice for such VGAs is an resulting equations have the form,
exponential control characteristic (i.e. linear in dB).
Gml= k * G
Switched capacitor techniques can be used to create
digitally programmable gain, but because the VGA is part of
a system wide gain control servo, monotonicity is essential.
Also, real time image processing systems need very smooth
gain transitions to prevent jumps in picture brightness as an
image is scanned. These requirements translate to a very high Gain = G ~ I / G)=
-~/, Z
level of gain "resolutions" and gain linearity or "DNL". (3)
Consequently, a switched capacitor implementation requires a where Gml is the input stage transconductance, Gm2 is
large number of capacitors and tight controls on mismatch. A the conductance of the diode connected load, x is a control
continuously variable analog control scheme, on the other variable which varies between +1 and -1, and k is a constant.
hand, efficiently provides a monotonic characteristic which is Over a limited range, this last expression is a very good
free from jumps or steps. For this reason, analog gain control approximation to an exponential. For the present application,
was chosen instead of a switched-cap implementation. If the however, this approach has two drawbacks. Because current
ultimate application requires digital control, an external DAC control of transconductance is used, the gain is limited by the
can be used, allowing the designer to concentrate on handling square-root nature of the device to a fairly small range. Also,
the linearity problems in a low speed control channel rather the signal path linearity is not very good unless large Vgs
than in the signal path. voltages are used.
The requirements of the particular application presented A solution more suitable for the present requirements of
were for a range from 0 to 34 dB (1X to 50X) which could wide gain range, large signal swing and low supply voltage is
handle signals as large as 1 volt p-p with reasonable to use two "linearized" transconductors rather than simple
distortion (approx. 1%). Of course this amp had to be high differential pairs. Researchers developing CMOS multipliers
speed, low noise, low power and 3 volt compatible using have come up with variable transconductors that are not only
foundry CMOS. linear for fairly large signals, but the transconductance is also
a linear function of the control signal. Hence,
Exponential Control
(4)
For disk drive applications, variable gain amplifiers have
been developed using variable MOS transconductances (1). A Cm2 = k * (1 - x)
standard differential pair with variable tail current is used to
drive a pair of diode-connected devices, also with variable
bias current as shown in Fig. 1. m(12+ x)/(l- x )
Gain = ~ m 1 / ~ =

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which approximates an exponential over a larger gain (Z4 - I , ) + ( [ , -I3)=k*(4ViVs)+k*(4ViVb-4ViVs)
range. = k * (4ViVb)
Linear Transconductors (10)

The linearization scheme chosen here is similar to one Amplifier Topology


published by Wang and Guggenbuhl of the Swiss Federal
Institute of Technology (2,3). The basis of the linearization is The differential current output of the Gm stage shown in
shown in Fig. 2, where all of the transistors are the same size. Fig. 2 can be passed to a similar, diode-connected stage
r Pot
acting as a load. Fig. 3 shows how this can be achieved.
Notice that the source node of the output stage is connected to
a fixed voltage, not a current source.

in1
1°C

IPS
1 '

Figure 2
Q Figure 3
If the voltage Vb is large, transistors M2 and M3 carry all There are now two sets of controlling voltages, Vbf ("f'
the current and the transconductance is that of a simple for "front") and Vbb ("b" for "back'). By making these
differential pair. As Vb is decreased, M1 and M 4 carry more voltages vary linearly in opposite directions, i.e. one increases
current and decrease the net transconductance of the cell. (At as the other decreases, we can get the desired (l+x)/(l-x)
Vb=O, the transconductance goes to zero.) In fact, the behavior required to approximate the exponential.
transconductance is Alternatively, if we fix one of the control voltages, we get a
simple linear, or l/x control characteristic for the stage.
G m = C * Vb
(7) The circuit is improved by putting more sophisticated
until you start to turn the outer pair off. (Here C is a feedback around the output stage. For one thing, a much more
constant de ending on bias and device size.) This can be seen predictable gain characteristic at the high and low gains can
as follows. P be achieved if the impedance at the output is reduced using
the loop gain. Although there are several ways to handle the
For the outer pair: feedback, Fig. 4 shows how it is done in the present
application. Here the two transconductance stages are
I , - I , =k*(-Vi-Vs)2-k*(Vi-Vs)2 configured as an "ads-amp"* architecture with a voltage gain
stage, A, closing the loop. The output Gm is servoed to match
the differential current from the input Gm.

= k * (4vivs)

For the outer pair:

= * 1r2 1
Vi2+Vb2 +Vs2
+ 2ViVb - 2VbVs - 2ViVs
+ Vb2+ Vs
- 2ViVb - 2VbVs
= k * (4ViVb - 4ViVs)
+ 2ViVs
(9)
Figure 4
One drawback of this implementation is the fact that the
loop gain will vary as the output transconductance is
changed. To avoid this, another Gm stage is connected as a
simple diode as shown in Fig. 5 . Here the voltage gain stage
of Fig. 4 is replaced by a fixed transconductance, "GM', and
a copy of the original output transconductor, "Gmo". Both of
the Gmo transconductors in the output stage are controlled by
So the total differential current is: the same signals so that they track each other and keep the
gain of the loop constant as the gain varied. Note that this

' To simplify the calculations, a threshold voltage of 0 volts is used for all This topology lacks a unique name, but Banie Gilbert has recently dubbed
devices. it "active feedback'.

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diode connected Gmo does not really create the output Results
voltage as in Fig. 3, it merely loads the loop. The output
voltage is created by the servo action of the loop and is thus Fig. 9 shows measured results for 0.6 um CMOS and 3
much more accurate. volt supplies. The plot is in dB, and is relatively straight for
-
the 0.5V 2.5V range indicating exponential behavior. Table
1 summarizes the circuit parameters and performance.
Input output 35

30 -
25 -
20 -

Figure 5
. A simplified version of the differential topology is shown
in' Fig. 6 and the complete schematic is in Fig. 7. The control
voltages (the Vb's) are created by variable currents through
- Vpb,
polysilicon resistors. Vpf, - Vnf, and Vnb are all variable 0 0.5 1 1.5
Control Voltage (v)
2 2.5 3

control voltages. The others, Vbpl, Vbp2, Vbn2, and VbnO


are all fixed bias levels. The two output transconductance
Figure 9
stages shown in Figs. 5 and 6 have been merged in Fig. 7 so
that they use the same control signals.
Table 1
process: 0.6um CMOS, 2-poly, 2-AI
gain range: Oto34dB
power supply: 2.7 to 3.3 V
dissipation: 21 mW (VGA, 3V)
2.3 mW (control ckt, 3V)
bandwidth: 20 MHz
die area: 680 sq. mil

References

I I (1) R. Harjani, "A Low-Power CMOS VGA for 5OMb/s Disk


Drive Read Channels", IEEE Transactions on Circuits and
Systems 11, vol. 42, no. 6, June 1995, pp. 370-376.
(2) Wang and Guggenbuhl, "A VariableXontrollable Linear MOS
Transconductor Using Bias Offset Technique", IEEE Journal of
Solid-state Circuits, vol. 25, no. 1, Feb. 1990, pp. 315-317.
Figure 6
(3) Z. Wang, "A CMOS Four-Quadrant Analog Multiplier with
The last refinement evident in Fig. 7 is to tweak the loop Single-Ended Voltage Output and Improved Temperature
gain a bit to do an even better job of compensation. The Performance", IEEE Journal of Solid-state Circuits, vol. 26,
resistors in the output stage marked with "*" have the effect no. 9, Sept. 1991, pp. 1293-1301.
of making the diode connected Gm vary a bit faster than the
feedback Gm. This makes for more constant closed-loop
bandwidth as the gain is changed.

Control Circuit
The circuit which generates the variable control voltages
is shown in Fig. 8. This is designed to yield the (l+x)/(l-x)
function, that is, Vbf decreases as Vbb increases. If the
resistor attached to the "gain control voltage" terminal is
made of the same material as the resistors in Fig. 7, the gain
control characteristic will be independent of sheet rho
variations.

I 48 o 2000 lEEE
0-7803-6309-4/00/$10.00 2000 Symposium on VLSl Circuits Digest of Technical Papers

Authorized licensed use limited to: NATIONAL INSTITUTE OF TECHNOLOGY WARANGAL. Downloaded on November 2, 2008 at 07:03 from IEEE Xplore. Restrictions apply.
1
i9

]E m

>
n

a0
l
0

i;
c
3
n
c
3
0

Figure 8

Control Circuit Schematic


L

01
0
0
i;
c
IJ
n
C
I

Figure 7
VGA Schematic

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