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IN VLSI SYSTEMS
M.RaviKishan M.V.SurendraBabu
2ndECE 2ndECE
raviece007@yahoo.co.in
Abstract:
In this paper we have presented in detail about the strength
reduction techniques.
That are needed to reduce the number of additions and multiplications
i.e., we have explained the use of these techniques for reducing the
strength of DSP computation.
By these techniques power, area of implementation can be
reduced. Strength reduction reduces the total capacitance and, therefore
reduces power consumption.
Introduction:
Number splitting can be additive or multiplicative, is a
numerical transformation that can be used to reduce the hardware
complexity or power consumption of linear circuits. Typically number
splitting is performed on the infinite precision version of the constant
coefficients before they are reduced to binary representation. This leads
to strength reduction at a higher level. Additive number splitting can be
either row based or column based.
Number splitting is an iterative technique used
in optimization of algorithm. The optimization algorithm guides the
number of splitting algorithm through the use of a cost function. At each
iteration, the number splitting that leads to the largest reduction in the
cost function of chosen. The process is repeated until no further
optimizations can be achieved through the use of number splitting.
The notion defined for linear circuit as,
Where
y=Tx
y0(n+1)
Y= y1(n+1)
……
yn-1(n+1)
y0(n)
…….
…….
x = yj-1(n)
X0(n)
…..
xK-1(n)
T=w* T’
AG
y0(n+1) .4 .7 .4 .8 y0(n)
y1(n+1) = .3 .6 .2 .9 y1(n)
y2(n+1) .5 .3 .2 .7 y2(n)
x0(n)
T′ = 0 .7 0 .8
.3 .6 .2 .9
.5 .3 .2 .7
AG= .4 0 .4 0
W= 1 0 0 1
01 0 0
00 1 0
0 .7 0 .8
T′ = .3 .6 .2 .9
.5 .3 0 .5
AG= .4 0 .4 0
0 0 .2 .2
W= 100 10
01000
00101
0 .7 0 .8
.4 .7 .4 .8 10010 .3 .6 .2 .9
.3 .6 .2 .9 = 01000 .5 .3 0 .5
.5 .3 .2 .7 00101 0 0 .2 .2
.4 .7 .4 .8
T′ = .3 .6 0 .9
.5 .3 0 .7
AG = 0 0 .2 0
1000
W = 0101
0011
.4 .7 .4 .8
.4 .7 .4 .8 1000 .3 .6 0 .9
.3 .6 .2 .9 = 0101 .5 .3 0 .7
.5 .3 .2 .7 0011 0 0 .2 0
T=T1T2
T=T1T2T3
CONCLUSIONS:
Similar to the strength reduction at algorithm
level, numerical strength reduction can reduce the hardware complexity
significantly. This chapter has addressed various numerical strength
reduction approaches based on sub expression elimination or sub structure
sharing. These approaches can be exploited to reduce the implementation
complicity of fixed – coefficient digital filters such as FIR and IIR, militate
filters and wavelet filters. It may be noted that sub expression elimination
techniques are commonly used in compliers.