EECS240 Spring 2008

Lecture 4: Design-Driven Small Signal Models

Elad Alon
Dept. of EECS
EECS240 Lecture 4 2
MOSFET Models for Design
SPICE (BSIM)
For verification
Device variations
Hand analysis
Velocity-sat model (good mostly for intuition)
Small-signal model
Challenge
How to accurately design when hand analysis
models may be way off?
EECS240 Lecture 4 3
Parameters Designers Care About
Layout designer:
Mostly care about just W and L
Circuit designer:
Gain g
m
, r
o
Bandwidth g
m
, C
GS
, C
GD
,
Power I
D
Voltage swing minimum V
DS
Noise
Can get many of the circuit parameters without
resorting to BSIM
Or rather, by just using BSIM as a look-up table
EECS240 Lecture 4 4
Low Frequency Model
1
st
order Taylor expansion of I
D
:
Just need to know the coefficients
EECS240 Lecture 4 5
V
od
Square Law Model
In saturation:
EECS240 Lecture 4 6
Weak Inversion g
m
In weak inversion we have bipolar behavior
Good model if transistor is actually used in weak
inversion
EECS240 Lecture 4 7
Transconductance
weak
inversion
strong inversion
( -V
T
)
EECS240 Lecture 4 8
Transconductance (cont)
Compare g
m
of MOSFET and BJT:
Since V
od
>>V
t
, BJT has larger g
m
for same I
D
Why cant we make V
od
~ V
t
?
You can if you work in subthreshold
Gives great g
m
per unit current
But pay a penalty in speed (will see shortly)
V
od
EECS240 Lecture 4 9
Output Resistance r
o
Hopeless to model this with a simple equation
(e.g. g
ds
= I
D
)
EECS240 Lecture 4 10
Open-loop Gain a
v0
Represents maximum attainable
gain from a transistor
May be more useful than r
o
Simulation Notes:
Bias current i
dc
sets V
GS
- V
T
Use feedback to find correct V
GS
while sweeping V
DS
Use relatively small gain (100) for
fast DC convergence
EECS240 Lecture 4 11
Gain, a
v0
= g
m
r
o
Strong tradeoff:
a
v0
versus V
DS
range
Create plots for
several device
lengths
L = 0.18m
EECS240 Lecture 4 12
Long Channel Gain
L a
v0

L = 0.35m
EECS240 Lecture 4 13
Technology Trend
0
10
20
30
40
50
60
70
80
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
V
DS
[V]
g
m

r
o
0.18m
0.25m
0.35m
0.5m
Short channel devices usually have lower
peak gain
EECS240 Lecture 4 14
Transistor Gain Detail
For practical V
DS
gain penalty is less severe
(remember: worst case V
DS
is what matters!)
0
5
10
15
20
25
30
35
40
45
0.0 0.1 0.2 0.3 0.4
VDS [V]
g
m

r
o
0.18m
0.25m
0.35m
0.5m
EECS240 Lecture 4 15
Small-Signal AC Model
r
o
g
m
v
gs
Drain
Source
Bulk = Substrate
Gate
EECS240 Lecture 4 16
PMOS AC Model
EECS240 Lecture 4 17
SPICE Charge Model
Charge conservation
MOSFET:
4 terminals: S, G, D, B
4 charges: Q
S
+ Q
G
+ Q
D
+ Q
B
= 0 (3 free variables)
3 independent voltages: V
GS
, V
DS
, V
SB
9 derivatives: C
ij
= dQ
i
/ dV
j
, e.g. C
G,GS
~ C
GS
C
ij
!= C
ji
Ref: HSPICE manual, Introduction to Transcapacitance, pp.
15:42, Metasoft, 1996.
EECS240 Lecture 4 18
Small Signal Capacitances
C
jDB
C
jDB
+ C
CB
/2 C
jDB
C
DB
C
jsB
+ 2/3 C
CB
C
jsB
+ C
CB
/2 C
jSB
C
SB
0 0 C
GC
|| C
CB
C
GB
C
ol
C
GC
/2 + C
ol
C
ol
C
GD
2/3 C
GC
+ C
ol
C
GC
/2 + C
ol
C
ol
C
GS
Strong inversion
saturation
Strong inversion
linear
Weak inversion
WL
x
C
WL C C
d
Si
CB
ox GC

=
=
m fF/ 48 . 0
m fF/ 24 . 0
m fF/ 3 . 5
2

=
=
=
olP
olN
ox
C
C
C
0.35u Process
EECS240 Lecture 4 19
Layout
HSPICE geo = 0 (default)
HSPICE geo = 3
EECS240 Lecture 4 20
Source/drain Parasitics and HSPICE
HSPICE geo = 0 (default)
HSPICE geo = 3
ACM=3 model (not in our current library)
HDIF = half of heavily doped diffusion length
GEO = 0: No sharing
GEO = 1: Drain shared
GEO = 2: Source shared
GEO = 3: Both shared
EECS240 Lecture 4 21
Figure of Merit: g
m
/I
D
How much g
m
per unit current
Purely a DC metric
Weak and moderate inversion region clearly the most
efficient regions to operate in
EECS240 Lecture 4 22
Efficiency g
m
/I
D
In weak or moderate inversion,
approaches BJT
g
m
/I
C
= 1/V
t
~ 40 V
-1
Largely independent of device type
NMOS/PMOS about the same
EECS240 Lecture 4 23
Efficiency as a Design Parameter
Why not use g
m
/I
D
for design?
Can always determine value (from I
D
and g
m
)
Can do this independently of short channel effects
(using simulator)
Units (V
-1
) and physical interpretation a little
strange
But well just redefine things slightly to fix this
EECS240 Lecture 4 24
Substitute for g
m
/I
D
: V*
Define:
e.g. V* = 200mV g
m
/I
D
= 10 V
-1
Square-law devices: V* = V
GS
-V
TH
= V
od
Remember: real devices do not obey the square
law!
*
2 2
: law Square
V
I
V V
I
g
D
TH GS
D
m
=

=
*
2

2
*
V I
g
g
I
V
D
m
m
D
= =
EECS240 Lecture 4 25
V
od
vs V*
Overdrive voltage V
od
Cannot be measured
Complex equations
Long channel devices:
V
od
= V
dsat
= V*
I
D
~ V*
2
Boundary between
triode and saturation
r
o
large for V
DS
> V*
C
GS
, C
GD
change
V* =2I
D
/g
m
Measure (simulate) easily
Complex equations
Short channel devices:
All interpretations of V* are
approximations
Except V* = 2 I
D
/ g
m
(but V*
V
dsat
)
EECS240 Lecture 4 26
Dynamic Figure of Merit
Unity current-gain bandwidth
For degenerate short channel device
(Long channel model, C
gd
=0)
od
EECS240 Lecture 4 27
Efficiency g
m
/I
D
versus f
T
Speed-
Efficiency
Tradeoff
NMOS faster
than PMOS
0.35u Process
EECS240 Lecture 4 28
Device Scaling
0
10
20
30
40
50
60
-0.1 0.0 0.1 0.2 0.3 0.4 0.5
V
GS
-V
TH
[V]
f
T

[
G
H
z
]
0.18m
0.25m
0.35m
0.5m
Short channel devices significantly faster
EECS240 Lecture 4 29
Composite Figure-of-Merit: f
T
g
m
/I
D
Peak performance for low V
GS
-V
TH
(implies low V*)
0
50
100
150
200
250
300
350
400
-0.1 0.0 0.1 0.2 0.3 0.4 0.5
VGS-VTH [V]
f
T

g
m
/
I
D

[
G
H
z
/
V
]
0.18m
0.25m
0.35m
0.5m
EECS240 Lecture 4 30
Design Example
Example: Common-source amp
a
v0
> 70, f
u
= 100MHz for C
L
= 5pF
a
v0
> 70 L =0.35m

High f
T
(small C
GS
): V* =
200mV

mS 14 . 3 2 =
L u m
C f g
A 314
2
*
= =
V g
I
m
D
EECS240 Lecture 4 31
Device Sizing
Pick L 0.35m
Pick V* 200mV
Determine g
m
3.14mS
I
D
= 0.5 g
m
V* = 314A
W from graph
(generate with SPICE)
W = 10m (314A /141A)
= 22m
Create these graphs for
several device lengths
141uA
NMOS
EECS240 Lecture 4 32
Common Source Verification
Amplifier gain > 70
Amplifier unity gain frequency is dead on
Output range limited to 0.6 V 1.5 V to maintain gain
(about 0.45V swing)
EECS240 Lecture 4 33
Small Signal Design Summary
Determine g
m
(from design objectives)
Pick L
Short channel high f
T
Long channel high r
o
, a
v0
, better matching
Pick V* = 2I
D
/g
m
based on qualitative interpretation
Small V* large signal swing, high current efficiency
High V* high f
T
Also affects noise (see later)
Determine I
D
(from g
m
and V*)
Determine W (SPICE / plot) takes care of short channel
effects, etc.
Accurate for short channel devices key for design
EECS240 Lecture 4 34
Device Sizing Chart
Generate these curves for a variety of Ls and device flavors
(NMOS, PMOS, thin oxide, thick oxide, different V
TH
)