Latchup

1
Latchup
A latchup is a type of short circuit which can occur in an improperly designed integrated circuit (IC). More
specifically it is the inadvertent creation of a low-impedance path between the power supply rails of a MOSFET
circuit, triggering a parasitic structure which disrupts proper functioning of the part, possibly even leading to its
destruction due to overcurrent. A power cycle is required to correct this situation.
The parasitic structure is usually equivalent to a thyristor (or SCR), a PNPN structure which acts as a PNP and an
NPN transistor stacked next to each other. During a latchup when one of the transistors is conducting, the other one
begins conducting too. They both keep each other in saturation for as long as the structure is forward-biased and
some current flows through it - which usually means until a power-down. The SCR parasitic structure is formed as a
part of the totem-pole PMOS and NMOS transistor pair on the output drivers of the gates.
The latchup does not have to happen between the power rails; it can happen at any place where the required parasitic
structure exists. A spike of positive or negative voltage on an input or output pin of a digital chip, exceeding the rail
voltage by more than a diode drop, is a common cause of latchup. Another cause is the supply voltage exceeding the
absolute maximum rating, often from a transient spike in the power supply, leading to a breakdown of some internal
junction. This frequently happens in circuits which use multiple supply voltages that do not come up in the proper
order after a power-up, leading to voltages on data lines exceeding the input rating of parts that have not yet reached
a nominal supply voltage. Latchups may also be caused by an Electrostatic discharge event.
Intrinsic BJTs in the CMOS technology
Yet another common cause of latchups
is ionizing radiation which makes this
a significant issue in electronic
products designed for space (or very
high-altitude) applications.
CMOS latchup
Equivalent circuit of CMOS latchup
In CMOS technology, there are a number of intrinsic Bipolar junction
transistors. In CMOS processes, these transistors can create problems
when the combination of n-well/p-well and substrate results in the
formation of parasitic n-p-n-p structures. Triggering these thyristor-like
devices leads to a shorting of the Vdd and gnd lines, usually resulting in
destruction of the chip, or a system failure that can only be resolved by
power-down.
[1]
Consider the n-well structure in the first figure. The n-p-n-p structure is
formed by the source of the NMOS, the p-substrate, the n-well and the
source of the PMOS. A circuit equivalent is also shown. When one of the
two bipolar transistors gets forward biased (due to current flowing
Latchup
2
through the well, or substrate), it feeds the base of the other transistor. This positive feedback increases the current
until the circuit fails or burns out.
Latchup prevention
It is possible to design chips that are latchup-resistant, where a layer of insulating oxide (called a trench) surrounds
both the NMOS and the PMOS transistors. This breaks the parasitic SCR structure between these transistors. Such
parts are important in the cases where the proper sequencing of power and signals cannot be guaranteed (e.g., in hot
swap devices).
Devices fabricated in lightly doped epitaxial layers grown on heavily doped substrates are also less susceptible to
latchup. The heavily doped layer acts as a current sink where excess minority carriers can quickly recombine.
[2]
Another possibility for a latchup prevention is the Latchup Protection Technology circuit. When a latchup is
detected, the LPT circuit shuts down the chip and holds it powered-down for a preset time.Wikipedia:Citation
needed
Most silicon-on-insulator devices are inherently latchup-resistant. Latchup is the low resistance connection between
tubWikipedia:Please clarify and power supply rails.
Also to avoid the latch, we have to put separate tap connection for each transistor. But this will increase the size of
device so fabs give a minimum space to put a tap, for example, 10u in 130nm technology.Wikipedia:Please clarify
Testing for latchup
See EIA/JEDEC STANDARD IC Latch-Up Test EIA/JESD78.
This standard is commonly referenced in IC qualification specifications.
References
[1] Jan M. Rabaey, University of California,Berkeley;Anantha Chandrakasan, Massachusetts Institute of Technology,Cambridge;Borivoje
Nikolic, University of California, Berkeley; Digital Integrated Circuits (2nd Edition) ISBN 978-0-13-090996-1
[2] [2] Stephen A. Campbell, The Science and Engineering of Microelectronic Fabrication, Oxford University Press (Indian Edition 2007) p.461
ISBN 978-0-19-568144-4
External links
Latch-up in CMOS designs (http:/ / www. ece. drexel. edu/ courses/ ECE-E431/ latch-up/ latch-up. html)
Analog Devices: Winning the battle against latchup in CMOS analog devices (http:/ / www. analog. com/ library/
analogDialogue/ archives/ 35-05/ latchup/ index. html)
Single-event latchup protection of integrated circuits (http:/ / www. techbriefs. com/ component/ content/ article/
1836)
Maxwell Technologies Microelectronics: Latchup Protection Technology (http:/ / www. maxwell. com/ products/
microelectronics/ latchup-protection)
SCR Latchup Video Tutorial (http:/ / www. eevblog. com/ 2009/ 07/ 04/ eevblog-16-all-about-cmos-scr-latchup/ )
Article Sources and Contributors
3
Article Sources and Contributors
Latchup Source: http://en.wikipedia.org/w/index.php?oldid=607144214 Contributors: Alan Liefting, Alistair1978, Anthonyjameswood, Betacommand, Brighterorange, Colonies Chris, David
Haslam, Deepon, DexDor, Drbreznjev, Foogod, Fratrep, Gsimard, Jamo spingal, Kathovo, Locos epraix, Mcorazao, Mdd4696, Mlewis000, Music Sorter, Ploum's, R'n'B, Rilak, RyanCu,
RyanEberhart, Sabih omar, Shaddack, SoledadKabocha, Startrooper101, StealthFox, Toffile, Whitemountainlabs, Woohookitty, Younesmaia, 32 anonymous edits
Image Sources, Licenses and Contributors
File:Latchup.png Source: http://en.wikipedia.org/w/index.php?title=File:Latchup.png License: Creative Commons Attribution-Sharealike 3.0 Contributors: User:Deepon
File:Latchup ckt.png Source: http://en.wikipedia.org/w/index.php?title=File:Latchup_ckt.png License: Creative Commons Attribution-Sharealike 3.0 Contributors: User:Deepon
License
Creative Commons Attribution-Share Alike 3.0
//creativecommons.org/licenses/by-sa/3.0/