SHRI VAISHNAV INSTITUTE OF TECHNOLOGY &

SCIENCE, INDORE




Project Report
On

CMOS BASED 4-BIT ANALOG TO DIGITAL CONVERTER (ADC)
DESIGN USING 0.25m TECHNOLOGY FOR ECG APPLICATIONS

Submitted as partial fulfillment for the award of the degree
Of
Bachelor of Engineering

SESSION 2013-14

ELECTRONICS & INSTRUMENTATION DEPARTMENT


PROJECT GUIDE: SUBMITTED BY:

MRS.NEHA MAHESHWARI VAIBHAV RATNAWAT
(0802EI101086)

VAIBHAVI KILLEDAR
(0802EI101087)

SHRI VAISHNAV INSTITUTE OF TECHNOLOGY &
SCIENCE, INDORE





CERTIFICATE

This is to certify that the project entitled CMOS BASED 4-BIT ANALOG TO DIGITAL
CONVERTER (ADC) DESIGN USING 0.25m TECHNOLOGY FOR ECG APPLICATION is the
benefited work carried out by VAIBHAV RATNAWAT & VAIBHAVI KILLEDAR, in partial
fulfillment of the requirements for the award of the degree of Bachelor Of Engineering in
Electronics And Instrumentation engineering from Rajiv Gandhi Prodyogiki
Vishwavidyalaya,Bhopal M.P. ,is a record of students own work carried by them under my
guidance and supervision. To the best of my knowledge the matter presented in this report
has not been submitted for the award of any other degree certificate.


Prof. NAMIT GUPTA Mrs. NEHA MAHESHWARI
Head of Department Project Guide, EI Dept.
SVITS, INDORE SVITS, INDORE





SHRI VAISHNAV INSTITUTE OF TECHNOLOGY & SCIENCE,
INDORE




DECLARATION

We hereby declare that the project work entitled CMOS BASED 4-BIT ANALOG TO DIGITAL
CONVERTER (ADC) DESIGN USING 0.25m TECHNOLOGY FOR ECG APPLICATION
submitted to the Rajiv Gandhi Proudyogiki Vishwavidyalaya,Bhopal,M.P. by VAIBHAV
RATNAWAT and VAIBHAVI KILLEDAR during the academic year 2013-14,as a partial
fulfillment for the award of degree of the bachelor of engineering in electronics and
instrumentation, is a record of an original work carried out under the supervision of our
guide,in EI department, SVITS and other references to the project work are clearly specified
by us.


Internal guide:-

MRS.NEHA MAHESHWARI VAIBHAV RATNAWAT

VAIBHAVI KILLEDAR




ACKNOWLEDGEMENT

We take a great pleasure in expressing our deep sense of gratitude to our
esteemed institute Shri Vaishnav Institute Of Technology And Science,Indore
for providing opportunity to fulfill our project.

We owe a great many thanks to a great many people who helped and supported us during
this project work. Our deepest thanks to Mrs. NEHA MAHESHWARI (Assistant Prof.), the
Supervisor of the project for guiding us and for her benevolence, can do inspiration and
constructive criticism through the entire period of our association with her .

We would like to express gratitude to Prof. NAMIT GUPTA (Head, EI dept.), for extending his
support. We would like to thank our Institution and our faculty members without whom this
project would have been a distant reality.

We are also grateful to our principal for providing excellent atmosphere in the institution,
which made the endeavor possible.


VAIBHAV RATNAWAT

VAIBHAVI KILLEDAR









CONTENTS

1. Abstract
2. Introduction
3. Literature review
Understanding Flash ADCs
Flash ADC vs. other ADCs
4. Block diagram & description of project
5. Schematics and simulation
6. About the software
Tanner EDA version 13
7. Discussion and conclusion
Project challenges
Future scope
Conclusion
8. References
9. Research papers




ABSTRACT




Abstract
A CMOS based 4-bit Flash Analog to Digital Converter (ADC) design with
reduced number of comparators than the conventional Flash Analog to Digital
Converter and multiplexer based architecture is proposed. For improving the
conversion rate, both the analog and digital parts of the ADC are fully modified
and the architecture uses only 4 comparators instead of 15 as used in
conventional flash ADC, thus saving considerable amount of power. The
proposed 4-bit ADC is designed and simulated in TANNER tools with 1.2 V
supply voltage using T-Spice simulation.
Keywords Flash ADC, Comparators, CMOS, TANNER, T-Spice.




















INTRODUCTION


Analog-to-digital converter architecture has become more advanced. Digital
clock signal has been incorporated within A/D converter components to meet
high-speed design specification. However, digital signal produces much noise
and need to be separated from analog circuits which is sensitive to noise. The
integration between analog and digital circuit design within a chip introduces
mixed signal IC design environment.

Various ADC architectures have been developed over the years, each with
different tradeoffs with respect to power, speed, and accuracy . Most ADC
architectures however are in some form a variant of the Flash ADC. Flash ADCs
operate much like a ruler: a ruler with a fixed resolution (e.g. can measure
accurately to millimeters) measures an infinite precision length to a finite
accuracy. Flash ADCs measure an analog signal into a digital signal by
comparing an analog input to fixed reference values as shown in Fig.. The
number of fixed references used determines the accuracy of the digital output
(e.g.) 4-bit accuracy is obtained by comparing against 2
4
=16 reference values,
10-bit accuracy by comparing against 2
10
=1024 reference values. Determining
which reference values the input is in-between forms a length 2
N
bit (where N
is the accuracy of the ADC) thermometer code representation of the analog
input. Mapping the unique thermometer code to its binary equivalent forms a
length N, binary representation of the analog input.

The performance of biomedical data acquisition systems such as ECG is
generally limited by precision of the digital input data, which is achieved at the
interface between analog and digital signals. ECG is a common bio-potential
signal with low amplitudes of 1000- -100Hz .

In ECG applications the design with minimum power dissipation is always the
key while fabricating the integrated circuit for such an ADC. The main problem
of flash ADC architecture is that they consume much power and the complexity
of the design increases proportionally with the resolution. Successive
approximation architectures which have a logarithmic dependence on
resolution are alternative approaches to reduce the complexity and the power
consumption of flash ADC. On the other hand, its not desirable to use those
kinds of ADCs in high-speed applications since they consume multiple clock
cycles to implement the conversion algorithm, which needs more time
interleaving to increase the conversion speed.
The main concern of this paper is to reduce the power consumption for flash
ADC to be suitable for usage in low voltage applications. Flash ADCs are still the
architecture of choice, where maximum sample rate and low to moderate
resolution is required [9].Speed, resolution and power dissipation are the three
main parameters for ADC [5] and they cant be changed once an ADC is
designed. This paper presents a CMOS based 4-bit ADC that uses only
4comparatorsinstead of 15 comparators so it dissipates minimum power and
can operate at higher speed at low resolution


Project Objective

The objective of this project is to design a CMOS based 4-bit Flash Analog to
Digital Converter (ADC) design with reduced number of comparators than the
conventional Flash Analog to Digital Converter. A multiplexer based design is
proposed .The proposed 4-bit ADC is designed and simulated in TANNER tools
with 1.2 V supply voltage using T-Spice simulation


LITERATURE REVIEW

Understanding FLASH ADC
Flash analog-to-digital converters, also known as parallel ADCs, are the fastest
way to convert an analog signal to a digital signal. Flash ADCs are suitable for
applications requiring very large bandwidths. However, these converters
consume considerable power, have relatively low resolution, and can be quite
expensive. This limits them to high-frequency applications that typically cannot
be addressed any other way.
Typical examples include data acquisition, satellite communication, radar
processing, sampling oscilloscopes, and high density disk drives.
Architectural Details
Flash ADCs are made by cascading high-speed comparators. Figure 1 shows a
typical flash ADC block diagram. For an N-bit converter, the circuit employs 2
N
-
1 comparators. A resistive-divider with 2
N
resistors provides the
reference voltage. The reference voltage for each comparator is one least
significant bit (LSB) greater than the reference voltage for the comparator
immediately below it. Each comparator produces a 1 when its analog input
voltage is higher than the reference voltage applied to it. Otherwise, the
comparator output is 0. Thus, if the analog input is between V
X4
and V
X5
,
comparators X
1
through X
4
produce 1s and the remaining comparators produce
0s. The point where the code changes from ones to zeros is the point at which
the input signal becomes smaller than the respective comparator reference-
voltage levels.
This architecture is known as thermometer code encoding. This name is used
because the design is similar to a mercury thermometer, in which the mercury
column always rises to the appropriate temperature and no mercury is present

above that temperature. The thermometer code is then decoded to the
appropriate digital output code.
The comparators are typically a cascade of wideband low-gain stages. They are
low gain because at high frequencies it is difficult to obtain both
wide bandwidth and high gain. The comparators are designed for low-voltage
offset, so that the input offset of each comparator is smaller than an LSB of the
ADC. Otherwise, the comparator's offset could falsely trip the comparator,
resulting in a digital output code that is not representative of a thermometer
code. A regenerative latch at each comparator output stores the result. The
latch has positive feedback, so that the end state is forced to either a 1 or a 0.
Given these basics, some adjustments are needed to optimize the flash
converter
Figure 1. Flash ADC architecture.


architecture.
Sparkle Codes
Normally, the comparator outputs will be a thermometer code, such as
00011111. Errors can cause an output like 00010111, meaning that there is a
spurious zero in the result. This out-of-sequence 0 is called a sparkle, which is
caused by imperfect input settling or comparator timing mismatch. The
magnitude of the error can be quite large. Modern converters employ an input
track-and-hold in front of the ADC along with an encoding technique that
suppresses sparkle codes.

Metastability
When the digital output from a comparator is ambiguous (neither a 1 nor a 0),
the output is defined as metastable. Metastability can be reduced by allowing
more time for regeneration. Gray-code encoding, which allows only 1 bit in the
output to change at a time,can greatly improve metastability. Thus,the
comparator outputs are first converted to gray-code encoding and then later
decoded to binary , if desired.Another problem occurs when a metastable
output drives two distinct circuits. It is possible for one circuit to declare the
input a 1, while the other circuit thinks that it is a 0. This can create major
errors. To avoid this conflict, only one circuit should sense a potentially
mestatable output.

Input Signal-Frequency Dependence
When the input signal changes before all the comparators have completed
their tasks, the ADC's performance is adversely impacted. The most serious
impact is a drop-off in signal-to-noise ratio (SNR) plus distortion (SINAD) as the
frequency of the analog input frequency increases.
Measuring spurious-free dynamic range (SFDR) is another good way to observe

converter performance. The "effective bits" achieved by the ADC is a function
of input frequency; it can be improved by adding a track-and-hold (T/H) circuit
in front of the ADC. The T/H circuit allows dramatic improvement, especially
when input frequencies approach the Nyquist frequency, as shown in Figure 2.
Parts without T/H show a significant drop-off in SFDR.


Figure 2. Spurious-free dynamic range as a function of input frequency.

Clock Jitter
SNR is degraded when there is jitter in the sampling clock. This becomes
noticeable for high analog-input frequencies. To achieve accurate results, it is
critical to provide the ADC with a low-jitter, sampling clock source.

Architectural Trade-Offs
ADCs can be implemented by employing a variety of architectures. The
principal trade-offs among these alternatives are:
The time it takes to complete a conversion (conversion time). For flash
converters, the conversion time does not change materially with

increased resolution. The conversion time for successive approximation
register (SAR) or pipelined converters, however, increases approximately
linearly with an increase in resolution (Figure 3a). For integrating ADCs,
the conversion time doubles with every bit increase in resolution.
Component matching requirements in the circuit. Flash ADC component
matching typically limits resolution to around 8 bits. Calibration and
trimming are sometimes used to improve the matching available on
chip. Component matching requirements double with every bit increase
in resolution. This pattern applies to flash, successive approximation, or
pipelined converters, but not to integrating converters. For integrating
converters, component matching does not materially increase with an
increase in resolution (Figure 3b).
Die size, cost, and power. For flash converters, every bit increase in
resolution almost doubles the size of the ADC core circuitry. The power
also doubles. In contrast, a SAR, pipelined, or sigma-delta ADC die size
will increase linearly with an increase in resolution; an integrating
converter core die size will not materially change with an increase in
resolution (Figure 3c). Finally, it is well known that an increase in die size
increases cost.











Figure 3. Architectural trade-offs.


Flash ADC vs. Other ADC Architectures
Flash vs. SAR ADCs
In a SAR converter, a single high-speed, high-accuracy comparator determines
the bits, one bit at a time (from the MSB down to the LSB).This is done by
comparing the analog input with a DAC whose output is updated by previously
decided bits and thus successively approximates the analog input.
This serial nature of the SAR limits its speed to no more than a few mega-
samples per second (Msps),while flash ADCs exceed giga-samples per
second(Gsps) conversion rates.

Flash vs. Pipelined ADCs
A pipelined ADC employs a parallel structure in which each stage works on one
to a few bits of successive samples concurrently. This design improves speed at

the expense of power and latency, but each pipelined stage is much slower
than a flash section. The pipelined ADC requires accurate amplification in the
DACs and inter stage amplifiers, and these stages have to settle to the desired
linearity level. By contrast, in a flash ADC the comparator only needs to be low
offset and to resolve its inputs to a digital level; there is no linear settling time
involved. Some flash converters require preamplifiers to drive the
comparators. Gain linearity needs to be specified carefully.

Pipelined converters convert at speeds of around 100Msps at 8- to 14-bit
resolutions. An example of a pipelined converter is theMAX1449, a 105MHz,
10-bit ADC. For a given resolution, pipelined ADCs are around 10 times slower
than flash converters of similar resolution. Pipelined converters are possibly
the optimal architecture for ADCs that need to sample at rates up to around
100Msps with resolution at 10 bits and above. For resolutions up to 10 bits and
conversion rates above a few hundred Msps, flash ADCs dominate.
Interestingly, there are some situations where flash ADCs are hidden inside
converter employing architecture to increase its speed.
Flash vs. Integrating ADCs
Single, dual, and multislope ADCs achieve high resolutions of 16 bits or more,
are relatively inexpensive, and dissipate materially less power. These devices
support very low conversion rates, typically less than a few hundred samples
per second. Most applications are for monitoring DC signals in the
instrumentation and industrial markets. This architecture competes with
sigma-deltaconverters.
Flash vs. Sigma-Delta ADCs
Flash ADCs do not compete with a sigma-delta architecture because currently
the achievable conversion rates differ by up to two orders of magnitude. The

sigma-delta architecture is suitable for applications with much lower
bandwidth, typically less than 1MHz, and with resolutions in the 12- to 24-bit
range. Sigma-delta converters are capable of the highest resolution possible in
ADCs. They require simpler anti-alias filters (if needed) to band limit the signal
prior to conversion.Sigma-delta ADCs trade speed for resolution by
oversampling, followed by filtering to reduce noise. However, these devices
are not always efficient for multichannel applications. This architecture can be
implemented by using sampled data filters, also known as modulators, or
continuous-time filters. For higher frequency conversion rates the continuous-
time architecture is potentially capable of reaching conversion rates in the
hundreds of Msps range with low resolution of 6 to 8 bits.
This approach is still in the early research and development stage and offers
competition to flash alternatives in the lower conversion rate range.
Another interesting use of a flash ADC is as a building block inside a sigma-
delta circuit to increase the conversion rate of the ADC.

Sub ranging ADCs
When higher resolution converters or smaller die size and power for a given
resolution are needed, multistage conversion is employed. This architecture is
known as a sub ranging converter, also sometimes referred to as half-
flash converter.
This approach combines ideas from successive approximation and flash
architectures.
Sub ranging ADCs reduce the number of bits to be converted into smaller
groups, which are then run through a lower-resolution flash converter. This
approach reduces the number of comparators and reduces the logic
complexity compared to a flash converter (Figure 4).

The trade-off results in a slower conversion speed compared to flash.
















Figure4.Sub ranging ADC architecture.

For applications requiring modest resolutions, typically up to 8-bits, at
sampling frequencies in the high hundreds of MHz, the flash architecture may
be the only viable alternative. The user must supply a low-jitter clock to ensure
good ADC performance. For applications with high analog-input frequencies,
the ADC chosen should have an internal track-and-hold.







BLOCK DIAGRAM AND DESCRIPTION OF PROJECT
The block diagram of proposed 4-bit flash ADC is shown in Fig.A. It uses
multiplexer and reduced number of comparator for ADC operation. The
multiplexer is used for generation of reference voltages while the comparators
are used for comparing different reference voltages. In comparison to the
conventional flash ADC which uses 2N-1 comparators for N- bit ADC, the
proposed one uses only N comparators and N-1 multiplexers to generate the
required binary code resulting in saving of power and area. The principle
behind this proposed work is to use analog multiplexer to change the
reference voltage in accordance to the previous significant bit and to exploit
the properties of comparators. As comparators are the fast element and
consume most of the power hence to reduce the power, the reduction of
comparators is the only alternative and the proposed design follows the same
path.

The most significant part of ADC architecture is comparator. Comparator is a
circuit that compares two analog input signals and decodes the signal into
single digital output signal. Flash type ADC usually referred as direct conversion
ADC has a bank of comparators sampling the input signal in parallel, each firing
for their decoded voltage range. The comparator bank feeds a logic circuit and
generates a code for each voltage range. Direct conversion is very fast, capable
of gigahertz sampling rate. The schematic design of comparator is shown in
Fig.B. The input voltage is compared with the reference voltage and the output
is 1 when input voltage is greater than the reference voltage. Output is 0 when
input voltage is lesser than the reference voltage.




If the input step is sufficiently small the output should not slew and the
transient response will be a linear response.
The settling time is the time needed for the output to reach a final value within
a predetermined tolerance, when excited by a small signal. Small-signal settling
time is determined by the gain bandwidth product of the amplifier. If the input
step magnitude is sufficiently large, the comparator will slew by virtue of not
having enough current to charge or discharge the compensating and/or load
capacitances. The slew rate is determined from the slope of the output
Fig-A: BLOCK DIAGRAM

waveform during the rise or fall of the output. Slew rate is limited by the
current-sourcing/sinking capability in charging the output capacitor.
In comparator there are two stages, first stage is composite cascade
differential amplifier N channel input devices in series with combination of
cascade active PMOS based current mirror load that compares the two input
but provide smaller gain while the second stage is common source provide
larger swing and greater gain similar to OPAMP based conventional two stage
open loop comparator and one NMOS is provided below which act as current
sink for stabilization. Amplifiers are usually employed to achieve linear
operation in closed loop configuration which requires careful compensation to
avoid unstable operation. On the contrary the comparator does not require
stability criteria as in two stage amplifier so it eliminated need for
compensation capacitor.


Fig-B: COMPARATOR CIRCUIT

For providing different reference voltages to the comparator, CMOS based
transmission gate is used as analog multiplexer. Multiplexers are key
components in CMOS memory elements and data manipulation structures. A
multiplexer chooses the output from among several inputs based on a select
signal. The conventional multiplexer has at least two inputs, at least one
output and at least one control select line terminal. Each of the inputs is
associated with a separate and distinct path through the multiplexer. One
source terminal of the multiplexer circuit is connected to high voltage source
Vdd. Another source terminal is connected to ground or Vss. The conventional
multiplexer are mostly built in complementary metal-oxide-semiconductor
technology to perform logic functions. The CMOS-based multiplexers have
leakage power that tends to increase with a reduction of their dimensions. The
conventional multiplexers are volatile; they can lose their logic states when the
power is off. The choice of employing transmission gates in preference to pass
transistors is because of its effect on dynamic range. A CMOS inverter is one of
the key elements of multiplexer. The inverter includes a p-type MOS transistor
and an n-type MOS transistor. Gate terminal of PMOS and NMOS are
connected in common to serve as input terminal. Drains of PMOS and NMOS
are connected in common to serve as output terminal. The multiplexer
comprises of transmission gates which make the multiplexer non-restoring.
Transmission gate consists of NMOS and PMOS connected in parallel. The
input terminal of the gate is composed by source terminals of the transistors
PMOS and NMOS connected in common. The output terminal of the
transmission gate is made of drain terminals of PMOS and NMOS also
connected in common. Selection signals S and S are applied to gate terminals
of PMOS and NMOS transistors respectively. The select signal S and its
complement S can enable simultaneously one of the two transmission gates at
any given time when both the PMOS and NMOS transistors of the gate are on.

The magnitude of input signals is substantially similar to value of V
dd
or V
ss

when logic 1 or logic 0respectively is applied to the input
terminals.Fig.4presents the schematic of 2to1 multiplexer. This multiplexer is
preceded by a set of three NMOS transistors (M1, M2 and M3) for providing
the input (V/4 and 3 V/4) to the 2to1 multiplexer which is required for 2to1
multiplexer as can be seen from Fig. C.



Fig-C: 2X1 MULTIPLEXER CIRCUIT

Fig.D. presents the schematic design of 4to1 analog multiplexer. Here five
NMOS transistors (M1, M2, M3, M4 and M5) are used for providing four
different reference voltages as required by 4to1 multiplexer. It requires four
inputs and two selection lines.



Fig-D: 4X1 MULTIPLEXER CIRCUIT

The schematic design of 8 to 1 multiplexer is shown in Fig.E.It requires eight
inputs and three selection lines.






Fig-E: 8X1 MULTIPLEXER CIRCUIT

SCHEMATICS AND SIMULATION

1) COMPARATOR



























2) 2 X 1 MULTIPLEXER

SCHEMATIC(S-EDIT)








NETLIST (T-SPICE)










WAVEFORM(W-EDIT)










3) 4 X 1 MULTIPLEXER

SCHEMATIC(S-EDIT)
































NETLIST (T-SPICE)










WAVEFORM (W-EDIT)










4) 8 X 1 MULTIPLEXER

SCHEMATIC(S-EDIT)










NETLIST (T-SPICE)












WAVEFORM (W-EDIT)









































































































ABOUT THE SOFTWARE

Tanner EDA version 13

S-EDIT

With S-Edit, Tanner Tools brings to the front-end design capture the ease-of-
use and design productivity for which Tanner Tools are known. It is tightly
integrated with Tanner's T-Spice simulation and verification tool and the
company's L-Edit layout tool. S-Edit designs can be laid out using L-Edit's SDL
(Schematic Driven Layout) and verified with L-Edit's LVS (Layout versus
Schematic).

S-Edit is Tanner Tools completely re-architected schematic entry tool, a design
environment that provides schematic capture, net list input and output, and
integrated analog simulation.
Powerful and easy-to-use interface
Tight integration with SPICE simulation, supporting dynamic
analysis, verification, and debugging throughout the design process
Easy interoperability with legacy data and third-party tools,
including Cadence and View Draw EDIF
Complete schematic features-libraries, buses, arrays, rubber band
connectivity editing, evaluated parameters with waveform probing and
back annotation of operating point voltages and currents
Fully user-programmable design environment, allowing a high
degree of customization and productivity

T-SPICE

Tanner Tools powerful T-Spice Circuit Simulator generates fast and accurate

simulations of analog and mixed-signal IC designs. The T-Spice Circuit Simulator
includes the Tanner Wave Tool, Simulation Manager, and Device Modeling
features.
H-SPICE and P-Spice compatible
Support for the latest industry models, including Penn State Philips
Model (PSP), BSIM3.3, BSIM4.5, BSIM SOI, EKV, MOS11, MOS20, VBIC
and MEXTRAM
Superior numerical techniques achieve convergence for circuits that are
often impossible to simulate with other SPICE programs.
Sophisticated device modeling algorithms allow designers to switch
from the fastest (table-based model evaluation) to the most accurate
method (direct model evaluation) to control solution performance and
accuracy on a per device basis.

Takes advantage of T-Spice Pro's behavioral modeling options to allow creation
of custom models using algebraic expression voltage and current controlled
sources, data from external tables, or the C programming language. Amplified
by the folding blocks. In summary, folding reduce the number of latch
comparators needed as compared to a flash converter.

W-EDIT

The W-Edit waveform analysis tool is a comprehensive viewer for displaying,
comparing, and analyzing simulation results.
Provides an intuitive multiple-window, multiple-chart interface for easy
viewing of waveforms and data in highly configurable formats.
Dynamically linked to T-Spice with a run-time update feature that

displays simulation results as they are being generated.
Automatically calculates and displays FFT results in a variety of
formats, including dB or linear magnitude, wrapped or unwrapped
phase, and real or imaginary parts.
Creates new traces based on mathematical expressions of other
traces






































DISCUSSION AND CONCLUSION


Project Challenges

The most challenging factor in completing this project is to realize the ADC itself. It took
about one whole semester to understand the concept of folding and interpolating ADC.
Moreover, in the process of designing the ADC, a lot of problem arose especially to come up
with good folding and interpolating signals. The folding and interpolating signals are realized
in two months later on second semester. The unexpected difficulty is because of the
problems due to sensitivity of the analog folding signals and common problem when
cascading circuits.

Besides that, the circuit analysis also took much more time than expected. The simulation of
the complete ADC takes about 40 minutes per simulation because of the large number of
devices. This makes the problem troubleshooting becomes so time consuming. Therefore,
design optimization also took plenty of time when optimizing the ADC to increase the speed
and reduce the power of the design.

Lastly, the exposure to CMOS analog design comes on the last semester. It was all try-and-
error game in designing the ADC until the knowledge of designing proper analog circuit is
gained from the class. Therefore, the understanding of the design came later than it should
be. It will be great if the CMOS analog subject is taught earlier by one semester.

Future Works

In the future, this project can be improved by:
Increasing the design reliability by improving the noise margin of the ADC. This can
be done by improving the isolation between analog and digital components.
Improving the ADC performance in term of speed and power consumption. The
folding and interpolating architecture is meant to create high-speed and low power
ADC. Therefore, by selecting different component (especially the comparator)
architecture, it will greatly affect the performance of the ADC.
Characterizing and testing the ADC vigorously to determine the performance of the

ADC. This can be done by using software-based (i.e. MATLAB) ideal DAC. The
characterization shall include various ADC design tests such as SNR, ENOB, INL and
DNL test.
Designing the layout for the circuit. Therefore, the ADC can be fabricated and the
practical performance of the ADC can be extracted.

Conclusion

Number of comparators reduced from 15 to 4 in comparison to
conventional 4 bit flash
Adc.
Power consumption reduced, as most of the power id consumed by the
comparators.































REFERENCES


CMOS VLSI DESIGN
By NEIL H.E. WESTE, DAVID HARRIS, AYAN BANERJEE
[PDF] A/D Converter
[PDF] Folding and Interpolation
Research Papers IEEE