Ces User PDF

Constraint Editor System
(CES) Users
Manual
Software Version EE 7.9
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Constraint Editor System (CES) Users Manual, EE 7.9 3
Table of Contents
Chapter 1
CES Quick References and Work Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Quick Help. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Quick Reference - CES Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Quick Reference - CES GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
File Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Edit Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
View Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Setup Menu. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Filters Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Tools Menu. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Data Menu. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Output Menu. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Quick Reference - CES Constraint Spreadsheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Trace and Via Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Clearances Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Z-Axis Clearances Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Nets Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Parts Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Noise Rules Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
CES Work Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Schematic-Design Work Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
PCB-Layout Work Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Chapter 2
CES Overview and Setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
CES Constraint-Driven Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
CES Constraint-Driven Design Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Concurrent Design Process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Creating PCB Rule Areas Through Rule-Area Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Creating Net Classes to Group Rule-Area Nets More Extensively . . . . . . . . . . . . . . . . . . 46
Creating Constraint Classes to Group and Define Net Constraints . . . . . . . . . . . . . . . . . . 47
Verifying Design Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Verifying Simulated Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Before You Begin Using CES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Differential Pairs Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Importing a Layout Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Importing a 2005.x Ces.prefs File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Design Architect/Board Architect-CES-Board Station XE . . . . . . . . . . . . . . . . . . . . . . . . 51
Design Architect/Board Architect-CES-Board Station RE . . . . . . . . . . . . . . . . . . . . . . . . 51
DxDesigner-CES-Expedition PCB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Keyin Netlist-CES-Expedition PCB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table of Contents
4 Constraint Editor System (CES) Users Manual, EE 7.9
Expedition TeamPCB and XtremePCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Starting and Exiting From CES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Starting CES in Standalone Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Viewing Constraint Database Log Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Cross Probing Between Design Systems and CES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Cross Probing From the Navigator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Setting Up CES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Specifying Design Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Setting Display Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Setting General Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Setting Units for the CES Spreadsheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Reusing Settings in External Designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Modifying Simulation Settings and Stimulus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Modifying Simulation Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Modifying Simulation Stimulus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Customizing the Display of CES Windows. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Customizing CES Toolbars . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Modifying Toolbars to Create Custom Sets of Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Creating New Toolbars. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Specifying General Toolbar Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Resetting a Toolbar to the Default Grouping of Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Running Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Creating or Opening a Script File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Importing Designs Into CES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Specifying General Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Specifying Reference Designator Prefixes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Specifying Power and Ground Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Customizing the Constraint Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Creating Custom Spreadsheet Pages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Sharing Your Constraint Set With Other Users . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Adding Custom Menu Selections to the Tools Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Customizing Command Shortcut Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Chapter 3
CES Constraint Spreadsheet Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Defining Constraints With CES Spreadsheets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Understanding Constraint Hierarchy and Overrides. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Organization of CES Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Selecting CES Spreadsheet Pages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Identifying Spreadsheet Icons. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Resizing Spreadsheet Columns and Rows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Zooming the Display of Spreadsheet Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Expanding and Collapsing Spreadsheet Rows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Sorting Constraint Pages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Deleting Constraint Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Copying and Pasting Constraint Values Between Separate Invocations of CES . . . . . . . . 94
Searching for Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Filtering Spreadsheet Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table of Contents
Filtering the CES Spreadsheet by Row Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Resetting the Spreadsheet to its Default View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Creating Constraint Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Working Concurrently With Other Users . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Adding Comments to Your Constraint Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Viewing Constraint Reference Information and Cell Properties . . . . . . . . . . . . . . . . . . . . . . 103
Viewing Cell Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Viewing Design Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Checking Constraints and Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Correcting CES Diagnostics Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Validating Constraints Against PCB Actuals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Viewing All Constraint Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Updating Actuals Displayed in CES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Clearing Actuals From the CES Spreadsheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Highlighting Constraint Differences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Sharing PCB Actuals With Front-End CES Sessions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Updating Electrical Net Data and Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Resolving Existing Constraint Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Painting Rules to Reuse Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Rolling Back and Undoing Constraint Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Supported Undo/Redo Actions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Saving Constraint Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Overwriting the Board Station RE Log File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Chapter 4
Rule-Area Scheme Creation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Creating Schemes to Represent PCB Rule Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
(Minimum) Scheme Clearances and Widths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Specifying Trace and Via Rules for Rule-Area Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Defining Via Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Creating Clearance Rule Sets for Rule-Area Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Defining Embedded Resistor Clearance Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Defining SMD Clearance Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Assigning Class-To-Class Clearance Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Assigning Z-Axis Class-To-Class Clearance Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Assigning Package Clearance Type Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Determining Package Side and End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Creating New PCB Layout Package Types in a Board Station Flow. . . . . . . . . . . . . . . . . 132
Specifying General Clearance Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Copying, Renaming, and Deleting Rule-Area Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Resetting Clearance Rules to the Master Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Chapter 5
Net Class Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Creating Net Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Creating Net Class Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Adding Nets to a Net Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Adding Power Nets to a Net Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table of Contents
Determining Net Class Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Creating a Net Class From an Existing Net Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Deleting Net Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Chapter 6
Constraint Class Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Creating Constraint Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Creating Constraint Class Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Adding Nets to a Constraint Class. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Defining Bus Constraint Classes Automatically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Determining Nets That Comprise a Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Creating a Constraint Class From an Existing Constraint Class . . . . . . . . . . . . . . . . . . . . . . 153
Deleting Constraint Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Chapter 7
Net Constraint Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Specifying General Net Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Specifying Topologies for Nets and Constraint Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
From-Tos, Pin Pairs, or Both? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Handling Multiple Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Creating Pin Sets to Construct Advanced Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Overriding Trace Width Constraints for From-Tos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Defining Pin Pairs for Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Including Internal Component-Pin Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Defining Discrete Component Pin Pairs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Specifying Delay Rules for Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Defining a Routing Tolerance for All Nets Within a Constraint Class . . . . . . . . . . . . . . . 165
Specifying Maximum Length as a Percentage Above Manhattan Length . . . . . . . . . . . . . 165
Net Delay Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Matching Delay Rules Among Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Matching Delay Tolerance at the Constraint Class Level . . . . . . . . . . . . . . . . . . . . . . . . . 169
Defining Formulas to Create Net Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Including Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Entering Multiple Formulas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Solving Formulas to Check for Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Creating Constants and Variables for Delay Rules and Formulas. . . . . . . . . . . . . . . . . . . . . 173
Using Free Variables to Constrain Delay by Group Only . . . . . . . . . . . . . . . . . . . . . . . . . 173
Specifying Simulated Delay Rules for Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Signal Edge Rates and Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Matching Simulated Delay Rules Among Nets or Constraint Classes. . . . . . . . . . . . . . . . 176
Defining Overshoot and Ringback Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Understanding Static and Dynamic Overshoot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Modifying I/O Designer FPGA Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Updating FPGA Constraints Between Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Defining Constraints for Single-Pin Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Table of Contents
Chapter 8
Parallelism and Crosstalk Rule Creation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Determining When to Use Parallelism or Crosstalk Rules . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Rule Precedence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Parallelism Rules Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Choosing Between Noise Rule Types for AutoActive . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Defining Parallelism Rules for Stack-Up Layers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Parallelism Rule Definition Methodologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Assigning Parallelism Rules to Nets and Constraint Classes . . . . . . . . . . . . . . . . . . . . . . . . 186
Navigating to Assigned Parallelism Rules From the Nets Page. . . . . . . . . . . . . . . . . . . . . 188
Defining Crosstalk Rules for Nets and Constraint Classes . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Chapter 9
Differential-Pair Net and Rule Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Defining Differential Pairs Manually . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Defining Differential Pairs Automatically. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
IBIS Model [Diff_Pin] Section Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Assigning Rules to Differential Pairs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Differential-Pair Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Chapter 10
Constraint Template Definition and Reuse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Defining Constraint Templates to Capture Net Constraints . . . . . . . . . . . . . . . . . . . . . . . . . 197
Developing Libraries of Constraint Templates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Constraints and Values Stored With Each Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Applying Constraint Templates to Nets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Applying Constraint Templates From the Nets Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Modifying Pin Matching for an Applied Constraint Template. . . . . . . . . . . . . . . . . . . . . . 201
Updating a Net With Constraint Template Changes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Reusing Constraint Templates in External Designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Chapter 11
CES Constraints Import and Export . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Importing CES Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Exporting CES Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Chapter 12
Stackup Property Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Viewing or Modifying Stackup Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Correlating Layer Names Among Design Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Chapter 13
Part-Model Assignment Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Verifying Default Part-Model Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Automatic Assignment of IBIS Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Specifying Available Part Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
IBIS Models Delivered With CES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Table of Contents
Specifying Model File Directories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Specifying Individual Model Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Understanding Relative Paths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Assigning Models to Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
IBIS Models or Technology Models?. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Updating Part Model Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Reloading Model Directories and Individual Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Overriding IBIS Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Chapter 14
Signal Integrity Exploration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Sending Nets to HyperLynx LineSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Sending Nets to ICX Pro Explorer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Creating Constraint Templates to Capture Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . 221
Updating CES With Constraint Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Chapter 15
Design Tool Update. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Managing Design Changes Between Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Communicating Design Changes Between Schematic and Layout . . . . . . . . . . . . . . . . . . 227
CES Synchronization of Constraint Databases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Resolving Constraint Conflicts Between Front-End and Back-End Designs. . . . . . . . . . . 232
Resolving Constraint Conflicts Manually . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Viewing Constraint Resolution Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Synchronizing Constraint Data Between Schematics and CES. . . . . . . . . . . . . . . . . . . . . . . 235
Sending Schematic Data to Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Sending DxDesigner Schematic Data to Expedition PCB . . . . . . . . . . . . . . . . . . . . . . . . . 235
Synchronizing Constraint Data Between CES and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Sending Layout Data to Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Appendix A
CES Constraint Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Using This Constraint Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Supported Design Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Trace and Via Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Via Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Route. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Trace Width Minimum. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Trace Width Typical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Trace Width Expansion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Typical Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Diff Pair Spacing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Clearances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Trace To Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Table of Contents
Trace To Pad. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Trace To Via . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Trace To Plane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Trace To SMD Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Pad To Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Pad To Via . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Pad To Plane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Via To Via. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Via To Plane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Via To SMD Pad. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Plane To Plane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Embedded Resistor To Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Embedded Resistor To Pad. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Embedded Resistor To Via . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Embedded Resistor To Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
EP Mask To Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
EP Mask To Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
EP Mask To Via . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
EP Mask To Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Z-Axis Clearances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Trace To Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Trace To Pad. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Trace To Via . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Trace To Plane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Trace To SMD Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
# Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Analog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Net Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Template Name. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Template Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Topology Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Topology Ordered. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Stub Length Max. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
# Vias Max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Max Restricted Layer Length External. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Max Restricted Layer Length Internal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
From To Constraints Layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
From To Constraints Trace Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
From To Constraints Z0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Jumpers Allowed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Length or TOF Delay Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Length or TOF Delay Min . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Length or TOF Delay Max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Length or TOF Delay Manhattan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Length or TOF Delay Min Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Length or TOF Delay Match. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Table of Contents
Length or TOF Delay Tol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Length or TOF Delay Delta . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Length or TOF Delay Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Formulas Formula. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Formulas Violation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Static Low Overshoot Max. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Static High Overshoot Max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Dynamic Low Overshoot Max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Dynamic High Overshoot Max. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Ringback Margin High Min . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Ringback Margin Low Min . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Non-Monotonic Edge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
Single Ended Characteristic Impedance Value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Single Ended Characteristic Impedance Tol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Simulation Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
Simulation Stimulus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
Simulated Delay Edge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Simulated Delay Min . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
Simulated Delay Max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
Simulated Delay Max Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
Simulated Delay Match To. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
Simulated Delay Match. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
Simulated Delay Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
Simulated Delay Tol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
Pair Tol Max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
Convergence Tolerance Max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
Distance to Convergence Max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Separation Distance Max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
Differential Spacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
Differential Impedance Target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Differential Impedance Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
I/O Designer I/O Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Hierarchical Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
Part Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Qty. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Part Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
Series. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
IBIS Component Name. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
IBIS Pin Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
Schematic Pin Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
Topology Pin Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
Pin Package Length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
Thermal Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
Thermal Power Scaling Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
Thermal Theta-jc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
Thermal Casing Temperature Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
Table of Contents
Thermal Junction Temperature Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
I/O Designer I/O Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
Noise Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
Noise Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
Constraint Class or Electrical Net Name Victim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Constraint Class or Electrical Net Name Aggressor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
Parallelism Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
Crosstalk Max. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
Crosstalk Est Actual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
Crosstalk Sim Actual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
Crosstalk Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
Crosstalk Auto Route Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
Index
End-User License Agreement
Table of Contents
Chapter 1
CES Quick References and Work Flows
Welcome to the Constraint Editor System
(CES) Users Manual. This section includes quick

references and work flows that will help you get up, running, and comfortable with CES in a
minimal amount of time.
Quick Help
Please click within the following illustration for single-click access to a wide variety of topics
covered in this manual.
Figure 1-1. Constraint Editor System (CES) Quick Help
Quick Reference - CES Commands
You can use this reference to quickly find specific CES commands. They are organized
alphabetically by design object and then action/task. You can also print this quick reference to
keep it handy while you use CES.
Click within the Topic column to jump to the corresponding topic for one of the following
commands. When viewing this documentation from your web browser, to open this quick
reference in a standalone browser window, click here.
Table 1-1. CES Commands
Design
Object
Action CES Command Topic
Bus
constraint
class
Define (auto) CES Spreadsheet > Nets tab >
Edit menu > Auto Bus
Defining Bus
Constraint Classes
Automatically on
page 150
Clearance
rule set
Assign CES Spreadsheet > Clearances tab
> Clearances toolbar >
Assigning Class-To-
Class Clearance
Rules on page 125
Clearance
rule set
Create Navigator > expand Schemes >
right-click a scheme > New
Clearance Rule
Creating Clearance
Rule Sets for Rule-
Area Schemes on
page 120
Constant Create CES Spreadsheet > Nets tab >
Edit menu > Variables > Edit
Creating Constants
and Variables for
Delay Rules and
Formulas on
page 173
Constraint Export File > Export > Constraints Exporting CES
Constraints on
page 205
Constraint Import File > Import > Constraints Importing CES
Constraints on
page 205
Constraint Rollback File > Rollback Changes Rolling Back and
Undoing Constraint
Changes on
page 113
Constraint Search Find toolbar > Searching for
Constraints on
page 94
Constraint View Info CES Spreadsheet > right-click a
constraint cell > Cell Info
Viewing Constraint
Reference
Information and Cell
Properties on
page 103
Constraint
class
Add nets CES Spreadsheet > Nets tab >
Main toolbar >
Adding Nets to a
Constraint Class on
page 149
Constraint
class
Copy
constraints
Navigator > expand Constraint
Classes > right-click a constraint
class > Clone
Creating a
Constraint Class
From an Existing
Constraint Class on
page 153
Constraint
class
Create Navigator > right-click Constraint
Classes > New Constraint Class
Creating Constraint
Classes on page 147
Constraint
class
Rename Navigator > expand Constraint
Classes > right-click a constraint
class > Rename
To Rename a
Constraint Class on
page 148
Constraint
group
Create CES Spreadsheet > Nets, Parts, or
Constraint Templates tab> Group
pulldown > Edit User Groups >
Creating Constraint
Groups on page 100
Constraint
template
Apply CES Spreadsheet > Nets tab >
Edit menu > Apply Constraint
Template
Applying Constraint
Templates to Nets on
page 199
Constraint
template
Define CES Spreadsheet > Nets tab >
right-click an electrical net ( ) >
Create Constraint Template
Defining Constraint
Templates to Capture
Net Constraints on
page 197
Constraint
template
Reuse
(external)
File > Export > Constraints Reusing Constraint
Templates in External
Designs on page 203
Default rules Revert Navigator > expand Schemes >
click a scheme > Main toolbar >
Resetting Clearance
Rules to the Master
Scheme on page 136
Design
configuratio
n
Set up Edit > Design Preferences Specifying Design
Preferences on
page 56
Table 1-1. CES Commands (cont.)
Design
Object
Differential
pair
Create (auto) CES Spreadsheet > Nets tab >
Pairs toolbar >
DefiningDifferential
Pairs Automatically
on page 192
Differential
pair
Create
(manual)
CES Spreadsheet > Nets tab >
select two nets > Pairs toolbar >
DefiningDifferential
Pairs Manually on
page 191
Differential
pair
Specify
delay rules
Group pulldown > Delays and
Lengths
Specifying Delay
Rules for Nets on
page 164
Discrete pin
pair
Define CES Spreadsheet > Parts tab >
right-click a top-level discrete >
Create Pin Pairs
Defining Pin Pairs
for Nets on page 161
Formula Define CES Spreadsheet > Nets tab >
design object row > Formulas
Formula cell
Defining Formulas
to Create Net
Relationships on
page 170
Formula Solve CES Spreadsheet > Nets tab >
Pairs toolbar >
Solving Formulas to
Check for Errors on
page 172
From-to Define CES Spreadsheet > Nets tab > set
Topology Type to Custom >
Topology toolbar >
To Manually Define
Netline Ordering
(From-Tos) for a
Specific Net on
page 157
General
clearance
rules
Specify CES Spreadsheet > Clearances tab
Specifying General
Clearance Rules on
page 133
Net Explore SI CES Spreadsheet > Nets tab >
Display Net in > HyperLynx
LineSim
Sending Nets to
HyperLynx LineSim
on page 219
Net Explore SI CES Spreadsheet > Nets tab >
Display Net in > ICX Pro
Explorer
Sending Nets to ICX
Pro Explorer on
page 220
Net Specify
delay rules
Lengths
Specifying Delay
Rules for Nets on
page 164
Design
Object
Net class Add Nets CES Spreadsheet > Trace & Via
Properties tab > Main toolbar >
Adding Nets to a Net
Class on page 141
Net class Copy
constraints
Navigator > expand Net Classes >
right-click a net class > Clone
Creating a Net Class
From an Existing Net
Class on page 144
Net class Create Navigator > right-click Net
Classes > New Net Class
Creating Net
Classes on page 139
Net class Rename Navigator > expand Net Classes >
right-click a net class > Rename
To Rename a Net
Class on page 140
Package
clearance
type rules
Assign CES Spreadsheet > Clearances tab
Assigning Package
Clearance Type
Rules on page 128
Parallelism
rules
Assign CES Spreadsheet > Noise Rules
tab > Pairs toolbar >
Assigning
Parallelism Rules to
Nets and Constraint
Classes on page 186
Parallelism
rules
Define Edit > Parallelism Rules > Define
Parallelism Rules
Defining Parallelism
Rules for Stack-Up
Layers on page 184
Parallelism
rules
Navigate CES Spreadsheet > Nets tab >
right-click a net or constraint class
> Navigate to Parallelism Rule
Navigating to
Assigned Parallelism
Rules From the Nets
Page on page 188
Part model Assign CES Spreadsheet > Parts tab >
IBIS Component Name and
Technology cells >
Assigning Models to
Parts on page 215
Part model Make
available
Edit > Simulation > Model Search
Path
SpecifyingAvailable
Part Models on
page 213
Part model Verify
Assignments
Data > Model Audit Report Verifying Default
Part-Model
Assignments on
page 211
Pin pair Define (auto) CES Spreadsheet > Nets tab >
Pairs toolbar >
To Define All Pin
Pairs Automatically
on page 162
Design
Object
Pin pair Define
(manual)
CES Spreadsheet > Nets tab > net
row > Edit menu > Pin Pairs >
Add Pin Pairs
To Define Pin Pairs
Manually on
page 162
Pin pair Specify
delay rules
Lengths
Specifying Delay
Rules for Nets on
page 164
Pin set Create CES Spreadsheet > Nets tab > net
row > Topology toolbar > >
> , , , , or > select pins
> Finish
Creating Pin Sets to
Construct Advanced
Topologies on
page 158
Rule-area
scheme
Create CES Spreadsheet > Trace & Via
Properties tab or Clearances tab >
Main toolbar >
Creating Schemes to
Represent PCB Rule
Areas on page 117
Stackup Edit File toolbar > Viewing or
Modifying Stackup
Properties on
page 209
Topology Specify
(custom)
row > Topology toolbar > >
Specifying
Topologies for Nets
and Constraint
Classes on page 156
Topology Specify (pre-
defined)
row > Topology toolbar > , ,
, , or
Specifying
Topologies for Nets
and Constraint
Classes on page 156
Trace & via
rules
Override
widths
(from-to)
FromTo Constraints Trace Width
cell
Overriding Trace
Width Constraints for
From-Tos on
page 161
Trace & via
rules
Specify CES Spreadsheet > Trace & Via
Properties tab > expand a scheme
Specifying Trace
and Via Rules for
Rule-Area Schemes
on page 118
Units Set Setup > Options > expand Units >
Display Units and Notation
Setting Units for the
CES Spreadsheet on
page 62
Design
Object
Variables Create CES Spreadsheet > Nets tab >
Edit menu > Variables > Edit
Creating Constants
and Variables for
Delay Rules and
Formulas on
page 173
Variables Find
references
Edit menu > Variables > Find
Variables Reference
To Find Variable
References on
page 174
Z-axis
clearance
rule set
Assign CES Spreadsheet > Z-Axis
Clearances tab > Clearances
toolbar >
Assigning Z-Axis
Class-To-Class
Clearance Rules on
page 126
Z-axis
clearance
rule set
Create CES Spreadsheet > Z-Axis
Clearances tab > right-click
existing rule set > New Z-Axis
Clearance Rule
Creating Clearance
Rule Sets for Rule-
Area Schemes on
page 120
Design
Object
Quick Reference - CES GUI
You can use this reference to quickly determine the purpose of specific menu selections
available through the CES graphical user interface. You can also print this quick reference to
keep it handy while you use CES.
Click within the right column of the tables below to view the topic associated with a specific
menu selection. When viewing this documentation from your web browser, to open this quick
reference in a standalone browser window, click here.
File Menu
Read a commands purpose or click within the Topic/Purpose column to view the
documentation associated with a specific File menu command.
Table 1-2. File Menu Selections
Menu Command Topic/Purpose
File > Rollback Changes Rolling Back and Undoing Constraint Changes on
page 113
File > Open Project Open a .prj file when you launch CES in standalone mode.
File > New Script Create a scripting form.
File > Open Script Open a scripting form.
File > Print Setup Set up your printer.
File > Print Preview View preview of a print job.
File > Print Print CES Spreadsheet content.
File > Log Viewer Viewing Constraint Database Log Files on page 55
File > Import > Layout
Template
Importing a Layout Template on page 50
File > Import > Constraints Importing CES Constraints on page 205
File > Import > Constraint
Template
Reusing Constraint Templates in External Designs on
page 203
File > Import > Settings Reusing Settings in External Designs on page 65
File > Import > Preferences
File
Importing a 2005.x Ces.prefs File on page 50
File > Export > Constraints Exporting CES Constraints on page 205
File > Export > Constraints
to ASCII
Exporting CES Constraints on page 205
Edit Menu
documentation associated with a specific Edit menu command.
File > Export > Constraint
Template
Reusing Constraint Templates in External Designs on
page 203
File > Export > Settings Reusing Settings in External Designs on page 65
File > Export > Actuals Sharing PCB Actuals With Front-End CES Sessions on
page 111
File > Exit Exit CES.
Table 1-3. Edit Menu Selections
Edit > Undo Undo last operation.
Edit > Redo Redo last undo operation.
Edit > Cut Cut selection.
Edit > Copy Copy selection.
Edit > Paste Paste selection.
Edit > Delete Delete selection.
Edit > Find Searching for Constraints on page 94
Edit > Replace Searching for Constraints on page 94
Edit > Pin Pairs > Add Pin
Pairs
Defining Pin Pairs for Nets on page 161
Edit > Pin Pairs > Auto Pin
Pair Generation
To Define All Pin Pairs Automatically on page 162
Edit > Pin Pairs > Auto
Simulation Pin Pair
Generation
To Define Only Simulation Pin Pairs Automatically on
page 162
Edit > Netline Order To Manually Define Netline Ordering (From-Tos) for a
Specific Net on page 157
Edit > Diff Pairs > Diff Pair
from Selected Nets
Defining Differential Pairs Manually on page 191
Edit > Diff Pairs > Auto
Assign Diff Pairs
Defining Differential Pairs Automatically on page 192
Table 1-2. File Menu Selections (cont.)
Edit > Assign Nets to
Classes
Adding Nets to a Net Class on page 141
Edit > Auto Bus Defining Bus Constraint Classes Automatically on
page 150
Edit > Parallelism Rules >
Define Parallelism Rules
Defining Parallelism Rules for Stack-Up Layers on
page 184
Edit > Parallelism Rules >
Assign Parallelism Rules
Assigning Parallelism Rules to Nets and Constraint
Classes on page 186
Edit > Clearances > Assign
Package Type Clearances
Assigning Package Clearance Type Rules on page 128
Edit > Clearances > Reset to
Master
Resetting Clearance Rules to the Master Scheme on
page 136
Edit > Clearances > General
Clearances
Specifying General Clearance Rules on page 133
Edit > Clearances > Class to
Class Clearance Rule
Assigning Class-To-Class Clearance Rules on page 125
Edit > Clearances > Z-Axis
Clearances
Creating Clearance Rule Sets for Rule-Area Schemes
on page 120
Edit > Clearances > Z-Axis
Class to Class Clearance
Rule
Assigning Z-Axis Class-To-Class Clearance Rules on
page 126
Edit > Variables > Edit Creating Constants and Variables for Delay Rules and
Formulas on page 173
Edit > Variables > Find
Variables Reference
To Find Variable References on page 174
Edit > Via Assignments Defining Via Assignments on page 119
Edit > Simulation >
Simulation Settings
Modifying Simulation Settings on page 66
Edit > Simulation >
Simulation Stimulus
Modifying Simulation Stimulus on page 71
Edit > Simulation > SI
Library Search Paths
Specifying Model File Directories on page 213
Edit > Apply Constraint
Template
Applying Constraint Templates to Nets on page 199
Edit > Constraints
Definition
Customizing the Constraint Set on page 82
Table 1-3. Edit Menu Selections (cont.)
View Menu
documentation associated with a specific View menu command.
Edit > Stackup Viewing or Modifying Stackup Properties on page 209
Table 1-4. View Menu Selections
View > Expand Expanding and Collapsing Spreadsheet Rows on
page 93
View > Collapse Expanding and Collapsing Spreadsheet Rows on
page 93
View > Reset Row Heights To Reset Rows to Their Default Heights on page 92
View > Reset Column
Widths
To Reset Columns to Their Default Widths on page 92
Views > Tabs To Toggle the Display of Specific Windows and
Window Elements on page 74
View > Navigator To Toggle the Display of Specific Windows and
View > Output To Toggle the Display of Specific Windows and
View > Scripting To Toggle the Display of Specific Windows and
View > Status Bar To Toggle the Display of Specific Windows and
View Properties Displays the properties associated with the active CES
spreadsheet cell.
View > Toolbars To Toggle the Display of Specific Windows and
View > Toolbars >
Customize
Customizing CES Toolbars on page 74
Table 1-3. Edit Menu Selections (cont.)
Setup Menu
documentation associated with a specific Setup menu command.
Filters Menu
documentation associated with a specific Filters menu command.
Tools Menu
documentation associated with a specific Tools menu command.
Note
Most Tools menu selections are only available in standalone CES sessions that are
launched on an Expedition Enterprise Flow: DxDesigner design.
Table 1-5. Setup Menu Selections
Setup > Settings Specifying Design Preferences on page 56 and Setting
Up CES on page 56
Setup > Cross Probing Cross Probing Between Design Systems and CES on
page 55
Setup > Shortcuts Customizing Command Shortcut Keys on page 85
Table 1-6. Filters Menu Selections
Filters > Enabled Filtering Spreadsheet Data on page 97
Filters > Cumulative Mode To Enable Cumulative Mode on page 98
Filters > Drill-down
Filtering
Filtering Spreadsheet Data on page 97
Filters > Levels To Filter the Spreadsheet by Row Type on page 99
Filters > Reset To Reset the View of Data Rows to All on page 98
Table 1-7. Tools Menu Selections
Tools > Dashboard Launch the Mentor Graphics Dashboard.
Data Menu
documentation associated with a specific Data menu command.
Tools > DxDesigner Launch DxDesigner.
Tools > ICX Pro Explorer Launch ICX Pro Explorer.
Tools > Constraint
Template Editor
Launch Constraint Template Editor.
Tools > CES Diagnostics Checking Constraints and Synchronization on page 105
Tools > Server Manager Launch Server Manager.
Tools > Auto Backup
Utility
Launch Auto Backup Utility.
Tools > Customize Adding Custom Menu Selections to the Tools Menu on
page 84
Table 1-8. Data Menu Selections
Data > Constraint
Violations
Viewing All Constraint Violations on page 109
Data > Solve All Formulas Solving Formulas to Check for Errors on page 172
Data > Update > Simulation
Results
To Update ICX Pro Verify Simulation Results on
page 112
Data > Update > IBIS Pin
Type & Defaults
Updating Part Model Constraints on page 216
Data > Actuals > Import
Layout Actuals
Sharing PCB Actuals With Front-End CES Sessions on
page 111
Data > Actuals > Import
Thermal Actuals
Sharing PCB Actuals With Front-End CES Sessions on
page 111
Data > Actuals > Clear All
Pages
Clearing Actuals From the CES Spreadsheet on
page 110
Data > Actuals > Clear This
Page
Clearing Actuals From the CES Spreadsheet on
page 110
Data > Actuals > Update
All
To Update All Net Actuals on page 110
Table 1-7. Tools Menu Selections (cont.)
Output Menu
documentation associated with a specific Output menu command.
Data > Actuals > Update
Selected
To Update Selected Net Actuals on page 110
Table 1-9. Output Menu Selections
Output > Model Audit
Report
Verifying Default Part-Model Assignments on page 211
Output > Design Statistics Viewing Design Statistics on page 105
Output > Check Constraints
Synchronization
Checking Constraints and Synchronization on page 105
Output > Show iCDB
Clients
Provides a short report of clients and sub-clients who are
currently working on the same design.
Output > Report Comments To View Comments on page 103
Table 1-8. Data Menu Selections (cont.)
Quick Reference - CES Constraint Spreadsheet
You can use this reference to quickly determine how to best utilize the design constraints you
can define through CES. Constraints are grouped by CES Spreadsheet page and ordered as they
appear on a specific spreadsheet page. You can also print this quick reference to keep it handy
while you use CES. When viewing this documentation from your web browser, to open this
quick reference in a standalone browser window, click here.
CES Constraint Reference: To get more information about a specific constraint, click the CES
Constraint name as it appears in one of the quick-reference tables below. Clicking a
constraint name brings you to the corresponding topic for a constraint, all of which are located
in the CES Constraint Reference (appendix A in the table of contents).
CES Constraint Spreadsheet Pages
Click one of the following links to go to a specific constraint spreadsheet quick-reference:
Trace and Via Properties Summary on page 27
Clearances Summary on page 28
Z-Axis Clearances Summary on page 30
Nets Summary on page 31
Parts Summary on page 38
Noise Rules Summary on page 40
Trace and Via Properties Summary
Please refer to the following table for trace and via property constraint quick-reference
information.
Table 1-10. Trace & Via Properties
CES Constraint Purpose
Index on page 240 Displays the layer number for a board layer. This
constraint is also displayed on the Clearances page and Z-
Axis Clearances page.
Type on page 241 Displays the type of printed circuit board layer (e.g.
signal, power, and ground). This constraint is also
displayed on the Clearances page.
Via Assignments on
page 242
Defines the via assignment for a net class.
Clearances Summary
Please refer to the following table for clearance constraint quick-reference information.
Route on page 243 Defines whether the board layer is routed during PCB
fabrication. You can define Route individually or for all
board layers of a net class.
Trace Width Minimum
on page 244
Defines the minimum acceptable trace width. You can
define Trace Width Minimumindividually or for all board
layers of a net class.
Trace Width Typical on
page 245
Defines the typical acceptable trace width. You can define
Trace Width Typical individually or for all boards layers
of a net class.
Trace Width Expansion
on page 246
Defines the expansion, or maximum acceptable trace
width.You can define Trace Width Expansion individually
or for all board layers of a net class.
Typical Impedance on
page 247
Defines signal impedance for the Trace Width Typical
constraint. When you enter a value into the Trace Width
Typical cell, impedance at this width is calculated and
placed into the Typical Impedance cell.
Diff Pair Spacing on
page 248
Defines the required parallel distance between trace
segments that comprise a differential pair. You can define
Diff Pair Spacing individually or for all board layers of a
net class.
Table 1-11. Clearances
constraint is also displayed on the Trace & Via Properties
page and Z-Axis Clearances page.
Type on page 251 Displays the type of printed circuit board layer (e.g.
signal, power, and ground). This constraint is also
displayed on the Trace & Via Properties page.
Trace To Trace on
page 252
Defines the minimum clearance distance between trace
segments. You can define Trace to Trace individually or
for all board layers of a clearance rule.
Trace To Pad on page 253 Defines the minimum clearance distance between traces
and pads. You can define Trace To Pad individually or for
all board layers of a clearance rule.
Table 1-10. Trace & Via Properties (cont.)
Trace To Via on page 254 Defines the minimum clearance distance between traces
and vias. You can define Trace To Via individually or for
Trace To Plane on
page 255
Defines the minimum clearance distance between traces
and planes. You can define Trace To Plane individually or
Pad To Pad on page 257 Defines the minimum clearance distance between pads.
You can define Pad To Pad individually or for all board
layers of a clearance rule.
Pad To Via on page 258 Defines the minimum clearance distance between pads
and vias. You can define Pad To Via individually or for all
board layers of a clearance rule.
Pad To Plane on page 259 Defines the minimum clearance distance between pads
and planes. You can define Pad To Plane individually or
Trace To SMD Pad on
page 256
Defines the minimumclearance distance between the pads
of surface mount devices and traces. You can define Trace
To SMD Pad individually, or for all board layers of a
clearance rule.
Via To SMD Pad on
page 262
of surface mount devices and vias. You can define Via To
SMD Pad individually, or for all board layers of a
clearance rule.
Via To Via on page 260 Defines the minimum clearance distance between vias.
You can define Via To Via individually or for all board
Via To Plane on page 261 Defines the minimumclearance distance between vias and
planes. You can define Via To Plane individually or for all
Plane To Plane on
page 263
Defines the minimum clearance distance between planes.
You can define Plane To Plane individually or for all
Embedded Resistor To
Trace on page 264
Defines the minimum clearance distance between the
resistive material of embedded thick-film resistors and
traces. You can define Embedded Resistor To Trace
individually or for all board layers of a clearance rule.
Table 1-11. Clearances (cont.)
Z-Axis Clearances Summary
Please refer to the following table for z-axis clearance constraint quick-reference information.
Pad on page 265
pads. You can define Embedded Resistor To Pad
Via on page 266
vias. You can define Embedded Resistor To Via
Resistor on page 267
resistive material of embedded thick-film resistors. You
can define Embedded Resistor To Resistor individually or
EP Mask To Trace on
page 268
production mask of embedded thin-film resistors and
traces. You can define EP Mask To Trace individually or
EP Mask To Pad on
page 269
production mask of embedded thin-film resistors and
pads. You can define EP Mask To Pad individually or for
EP Mask To Via on
page 270
production mask of embedded thin-filmresistors and vias.
You can define EP Mask To Via individually or for all
EP Mask To Resistor on
page 271
production mask of embedded thin-film resistors and the
resistive material of embedded thick-film resistors. You
can define EP Mask To Resistor individually or for all
Table 1-12. Z-Axis Clearances
constraint is also displayed on the Trace & Via Properties
page and Clearances page.
Table 1-11. Clearances (cont.)
Nets Summary
Please refer to the following table for net constraint quick-reference information.
Trace To Trace on
page 274
Defines the minimum clearance distance between trace
segments located on different signal layers. You can
define Trace To Trace individually or for all board layers
of a clearance rule.
Trace To Pad on page 275 Defines the minimum clearance distance between traces
and pads located on different signal layers. You can define
Trace To Pad individually or for all board layers of a
clearance rule.
Trace To Via on page 276 Defines the minimum clearance distance between traces
and vias located on different signal layers. You can define
Trace To Via individually or for all board layers of a
clearance rule.
Trace To Plane on
page 277
Defines the minimum clearance distance between traces
and planes located on different signal layers. You can
define Trace To Plane individually or for all board layers
Trace To SMD Pad on
page 278
of surface mount devices and traces located on internal
signal layers. You can define Trace To SMD Pad
individually, or for all board layers of a clearance rule.
Table 1-13. Nets
CES Constraint Group Purpose
# Pins on page 280 Displays the number of pins that comprise the
net.
Analog on page 281 Defines the net as analog and prevents physical
nets that comprise an electrical net or differential
pair from being merged into an electrical net or
differential pair. You can define Analog
individually or for all nets of a constraint class.
Bus on page 282 Defines the constraint class as a bus. Nets within
the constraint class should be limited to those
nets that comprise the bus.
Net Class on page 283 Displays the net class name to which the net
belongs.
Table 1-12. Z-Axis Clearances (cont.)
Template Name on
page 284
Optionally, defines the constraint template to
which the net is assigned. You can define
Template Name individually or for all nets of a
constraint class.
Template Status on
page 285
Displays the synchronization status of the net
with regard to the current values stored in the
constraint template.
Topology Type on
page 286
Defines the topology type used for routing,
which can be an automatic routing pattern, or
custom routing pattern that you define. You can
define Topology Type individually or for all nets
of a constraint class.
Topology Ordered on
page 288
For Topology Type Custom or Complex,
displays whether the custom topology type has
undergone netline ordering, which is required for
each user-specific topology type.
Stub Length Max on
page 289
Defines the maximum stub length that can be
created when routing this net as a custom,
complex, or chained Topology Type. You can
define Stub Length Max individually or for all
nets of a constraint class.
# Vias Max on page 290 Defines the maximumnumber of vias that can be
created when routing a net. This constraint value
must be between 1 and 1000. You can define #
Vias Max individually or for all nets of a
constraint class.
Max Restricted Layer
Length External on
page 291
Defines the maximum trace length that can be
routed on external restricted board layers. You
can define Max Restricted Layer Length External
Max Restricted Layer
Length Internal on
page 292
Defines the maximum trace length that can be
routed on internal restricted board layers. You
can define Max Restricted Layer Length Internal
From To Constraints
Layer on page 293
Defines the board layer on which to route a from-
to that uses Topology Type Custom. You can
define From To Constraints Layer individually
for each from-to.
Table 1-13. Nets (cont.)
FromTo Constraints Trace
Width on page 294
Optionally defines the trace width to which to
route a from-to. You can define From To
Constraints Trace Width individually for each
from-to.
From To Constraints Z0
on page 295
Displays an impedance calculation based on the
trace width override value defined in From To
Constraints Trace Width.
Jumpers Allowed on
page 296
Displays whether jumpers are allowed on a net.
Length or TOF Delay
Type on page 297
Defines the delay type for a net, which can be
controlled electrically (TOF) or physically
(Length). You can define Length or TOF Delay
Type individually, for pin pairs, for differential
pairs, or for all nets of a constraint class.
Length or TOF Delay
Min on page 298
Defines the minimum acceptable physical
routing length or signal propagation delay (e.g.
time) between design connections. You can
define Length or TOF Delay Min individually,
for pin pairs, for differential pairs, or for all nets
Length or TOF Delay
Max on page 299
Defines the maximum acceptable physical
routing length or signal propagation delay (e.g.
time) between design connections. You can
define Length or TOF Delay Max individually
individually, for pin pairs, for differential pairs,
or for all nets of a constraint class.
Length or TOF Delay
Manhattan on page 301
Displays the Manhattan net length. This length is
replaced with Length or TOF Delay Actual when
the net is routed.
Length or TOF Delay Min
Length on page 302
Displays the straight line length between two pin
pairs when both components are placed. This
length is replaced with Length or TOF Delay
Actual when the net is routed.
Length or TOF Delay
Match on page 303
Defines a match character or string (e.g. 1) you
can use to group nets for similar length or time of
flight delay routing. You can apply Length or
TOF Delay Match individually, for pin pairs, or
for differential pairs.
Length or TOF Delay Tol
on page 304
Introduces a tolerance range around the net
routing delay requirements for nets that duplicate
a Length or TOF Delay Match (e.g. 1). You can
also define this constraint at the constraint class
level without the pre-requirement of defining a
match character or string.
Length or TOF Delay
Delta on page 305
Displays estimates for routing results that can be
achieved without constraint modification.
Length or TOF Delay
Range on page 306
Displays the range of length or time of flight
actuals for all nets and/or constraint classes that
are part of the same match group.
Formulas Formula on
page 307
Defines a formula that can be used to create delay
relationships between nets and pin pairs. You can
define Formulas Formula individually or for pin
pairs.
Formulas Violation on
page 308
Displays formula violation information based on
the Formulas Formula constraint.
Static Low Overshoot
Max on page 309
Defines the standard acceptable maximum low
operating voltage (i.e. minimum) for the signal.
You can define Static Low Overshoot Max
individually, for differential pairs, or for all nets
Static High Overshoot
Max on page 311
Defines the standard acceptable maximum high
operating voltage (i.e. maximum) for the signal.
You can define Static High Overshoot Max
Dynamic Low Overshoot
Max on page 313
Defines an acceptable smaller maximum low
operating voltage (i.e. below minimum) for the
signal for a specific duration. You can define
Dynamic Low Overshoot Max individually, or
for all nets of a constraint class.
Dynamic High Overshoot
Max on page 315
Defines an acceptable larger maximum high
operating voltage (i.e. above maximum) for the
signal for a specific duration. You can define
Dynamic High Overshoot Max individually, for
differential pairs, or for all nets of a constraint
class.
Ringback Margin High
Min on page 317
Defines the minimum allowed difference
between the high switching threshold (Vinh) and
a ringback wave. You can define Ringback
Margin High Min individually, for differential
Ringback Margin Low
Min on page 318
Defines the minimum allowed difference
between the low switching threshold (Vinl) and a
ringback wave. You can define Ringback Margin
Low Min individually, for differential pairs, or
Non-Monotonic Edge on
page 319
Defines a non-monotonicity requirement for the
rising edge, falling edge, or both signal edges.
You can define Non-Monotonic Edge
of a constraint class. For example, when you set
Non-Monotonic Edge to Rising, an error is
reported only if the rising signal edge is non-
monotonic.
Single Ended
Characteristic Impedance
Value on page 320
Defines the single-ended characteristic
impedance for net traces. You can define Single
Ended Characteristic Impedance Value
Single Ended
Characteristic Impedance
Tol on page 321
Introduces a tolerance range around Single
Ended Characteristic Impedance Value. You can
define Single Ended Characteristic Impedance
Tol individually, for differential pairs, or for all
Simulation Settings on
page 322
, Defines the simulation settings to use when
generating actual values for Nets Spreadsheet
Overshoot/Ringback and Simulated Delays
groups. You can define Simulation Settings
Simulation Stimulus on
page 324
, Defines the simulation stimulus to use when
generating actual values for Nets Spreadsheet
Overshoot/Ringback and Simulated Delays
groups. You can define Simulation Stimulus
Simulated Delay Edge on
page 325
Defines the simulated delay edge to constrain,
which controls the switching time between signal
states. You can define Simulated Delay Edge
individually, for differential pairs, for pin pairs,
Simulated Delay Min on
page 327
Defines the minimumacceptable simulated delay
for the Simulated Delay Edge value (e.g. Rise,
Fall). You can define Simulated Delay Min
Simulated Delay Max on
page 328
Defines the maximum acceptable simulated
delay for the Simulated Delay Edge value (e.g.
Rise:Fall, Both). You can define Simulated
Delay Max individually, for differential pairs, for
pin pairs, or for all nets of a constraint class.
Simulated Delay Max
Range on page 329
Defines a maximum acceptable range of
difference between Simulated Delay Actual Min
and Simulated Delay Actual Max for the
Simulated Delay Edge value (e.g. Fall, Both).
You can define Simulated Delay Max Range
Simulated Delay Match
To on page 330
Defines the hierarchical level of matching for the
Simulated Delay Match constraint. You can
match to the constraint class, net, or pin-pair
level. You can define Simulated Delay Match To
on page 331
Defines the electrical net, pin pair, or constraint
class to which to match the Simulated Delay
constraints (e.g. Simulated Delay Edge,
Simulated Delay Min, Simulated Delay Max).
You can define Simulated Delay Match
Simulated Delay Offset
on page 333
Introduces a positive or negative offset (e.g. 50
ns, -50 ns) from Simulated Delay Min and
Simulated Delay Max when matching the
simulated delay of an electrical net or constraint
class (Simulated Delay Match). You can define
Simulated Delay Offset individually, for
differential pairs, for pin pairs, or for all nets of a
constraint class.
Simulated Delay Tol on
page 334
Introduces a tolerance range (e.g. 5 ns) around
Simulated Delay Min and Simulated Delay Max
when matching the simulated delay of an
electrical net or constraint class (Simulated Delay
Match). You can define Simulated Delay Tol
Pair Tol Max on page 335 Defines the tolerance of the time of flight or
length delay between differential pair nets. You
can define Pair Tol Max individually for each
differential pair.
Convergence Tolerance
Max on page 336
Defines the maximumallowed difference in trace
length from pads to the point where traces start
routing differentially at the Differential Spacing
constraint. You can define Convergence
Tolerance Max individually for each differential
pair.
Distance to Convergence
Max on page 337
Defines the maximum distance that differential
traces are allowed to route before they converge
as a differential pair. Convergence is met when
traces start routing at the Differential Spacing
constraint.You can define Distance to
Convergence Max individually for each
differential pair.
Separation Distance Max
on page 338
Defines the maximum allowed distance that
differential traces are allowed to route at a
spacing greater or less than the Differential
Spacing constraint. You can define Separation
Distance Max individually for each differential
pair.
Parts Summary
Please refer to the following table for part constraint quick-reference information.
Differential Spacing on
page 339
Displays the required parallel distance between
trace segments that comprise a differential pair.
When separate spacing values are defined for
each board layer, CES displays the values as a
colon-separated list (e.g. 5:8).
Differential Impedance
Target on page 340
Defines the target differential impedance. You
can define this constraint for differential-pair
electrical nets, and differential pairs.
Differential Impedance
Tolerance on page 341
Introduces a tolerance range around Differential
Impedance Target. You can define this constraint
for differential-pair electrical nets, and
differential pairs.
I/O Designer I/O
Standard on page 342
Defines the technology standard for an FPGA
signal net. You can define I/O Designer I/O
Standard individually, or for all nets of a
constraint class.
Table 1-14. Parts
Hierarchical Path on
page 344
Displays the hierarchical component path, when
applicable.
Part Number on page 345 Displays the part number for a design component.
Qty on page 346 Displays the number of times a part is used throughout
your design.
Part Type on page 347 Displays the part-type value associated with a design
component.
Series on page 348 Defines whether a series-class component (e.g. resistor)
should actually be considered a series element, and
therefore not used for electrical net generation. You can
define Series for parts and part instances.
IBIS Component Name
on page 349
Defines the IBIS model used for a part. You can define
IBIS Component Name individually, or for all instances of
a part.
Technology on page 350 Defines the technology model used for a part. You can
define Technology individually, or for all instances of a
part.
Value on page 351 Defines the electrical value associated with a discrete part,
which can be resistance, inductance, or capacitance. You
can define Value individually or for all instances of a part.
IBIS Pin Type on
page 352
Displays the IBIS pin type for a pin instance.
Schematic Pin Type on
page 353
Displays the schematic pin type for a pin instance.
Topology Pin Type on
page 354
Defines the chaining pin type for a pin instance. Chaining
pin types are source, load, or terminator (i.e. S, L, T).
Pin Package Length on
page 355
Defines a pin's internal package length between the
substrate and dielectric layers of the component. This
constraint is commonly used to define wire bonding
length.
Thermal Power
Dissipation on page 356
Defines a parts power dissipation as a subset of the total
amount of power needed to run the component.
Thermal Power Scaling
Factor on page 357
Defines a part instances scaling factor with regard to
power dissipation.
Thermal Theta-jc on
page 358
Defines a parts junction-to-casing thermal resistance.
This is also commonly referred to as die-to-package heat
resistance.
Thermal Casing
Temperature Limit on
page 359
Defines a parts maximum allowable temperature for the
component casing or package.
Thermal Junction
Temperature Limit on
page 360
Defines a parts maximum allowable temperature for
component junctions. A component junction is also
commonly referred to as a die.
I/O Designer I/O
Standard on page 361
Displays the defined technology standard for an FPGA
signal net. When on the CES Spreadsheet Nets page, you
can define I/O Designer I/O Standard individually, or for
all nets of a constraint class.
Table 1-14. Parts (cont.)
Noise Rules Summary
Please refer to the following table for noise rule constraint quick-reference information.
Table 1-15. Noise Rules
Noise Type on page 363 Defines the noise type for a specific parallelism rule
and/or Crosstalk Max constraint and Crosstalk Level.
Constraint Class or
Electrical Net Name
Victim on page 364
Defines the victim constraint class or electrical net of the
aggressor-victim relationship.
Constraint Class or
Electrical Net Name
Aggressor on page 365
Defines the aggressor constraint class or electrical net of
the aggressor-victim relationship.
Parallelism Rule on
page 366
Defines the parallelism rule for a class-to-class or net-to-
net parallelism relationship.
Crosstalk Max on
page 367
Defines the maximumacceptable crosstalk that a net or all
nets within a constraint class can be subjected to as victim
nets. You can define Crosstalk Max individually or for all
Crosstalk Est Actual on
page 369
Displays the actual value for Crosstalk Max based on
AutoActive calculations.
Crosstalk Sim Actual on
page 370
Displays the actual value for Crosstalk Max based on ICX
Pro Verify calculations.
Crosstalk Level on
page 371
Defines the signal state of the victim net in a crosstalk
relationship.
Crosstalk Auto Route
Usage on page 372
Defines the noise rule type that should be used during auto
routing.
CES Work Flows
CES Work Flows
The two main work flows for CES are illustrated below. Although these work flows indicate the
typical order of constraint entry and modification for schematic and PCB engineers, your order
of operations may be different.
The following work flows are included:
Schematic design This work flow begins with creating and defining constraint classes,
which hold electrical, signal integrity, and high-speed signal integrity constraints. Along
the way, different types of constraint assignments are made. Some of these include
topology types, simulated delay rules, and overshoot and ringback requirements. The
final step is to send schematic constraint data to your layout design representation
through forward annotation.
PCB layout This work flow starts with creating and defining both rules-area schemes
and net classes. These groupings hold physical constraints for board layers and nets.
Along the way, different types of constraint assignments are made. Some of these
include trace and via rules, clearance rule sets, and package-type clearances. The final
step is to send layout constraint data to your schematic design representation through
back annotation.
CES Work Flows
Schematic-Design Work Flow
Click within the following illustration to view the topic for a specific step within this work
flow.
Figure 1-2. Schematic-Design Work Flow
CES Work Flows
PCB-Layout Work Flow
Click within the following illustration to view the topic for a specific step within this work
flow.
Figure 1-3. PCB-Layout Work Flow
Related Topics
CES Constraint-Driven Design on page 45
CES Work Flows
Chapter 2
CES Overview and Setup
This section is an introduction to CES that provides an overview of CES and constraint-driven
design flows. It also includes information about invocation, setup, application customization,
and script deployment. At a minimum, please make sure to read Before You Begin Using
CES on page 47. It includes important information for each PCB design flow that uses CES.
Please refer to the table of contents for the full listing of topics included in this section.
CES Constraint-Driven Design
Constraint Editor System(CES) gives you the ability to define and refine design constraints in a
common environment that is accessible from many Mentor Graphics Corporation schematic
entry and PCB layout design systems. By using CES, you can bridge the gap between specific
front-end and back-end design systems to efficiently streamline and maintain the design
constraints that result in bringing PCB solutions to market. All without much of the costly
research and development expenses that are associated with multiple design revisions for a
single product release.
Figure 2-1. Common Constraint Environment Resulting in Accurate Schematic
Design and PCB Layout Views
See also: Click within the above illustration to view related CES topics.
CES Constraint-Driven Design Flows
CES supports the following constraint-driven design flows:
DxDesigner
-Expedition
PCB
CES Constraint-Driven Design
Design Architect
/Board Architect
-Board Station
XE
Design Architect/Board Architect-Board Station RE
Design Capture
/DesignView
-Expedition PCB
Keyin netlist-Expedition PCB
Note
CES is only available in concurrent design flows. CES is not available in any DxDesigner
Netlist flows (e.g. DxDesigner netlisting to Expedition PCB).
Concurrent Design Process
CES supports concurrent design process, the ability to have multiple engineers work on
schematic-entry or PCB-layout design constraints simultaneously. This means that a front-end
or back-end database can be modified at the same time by multiple engineers. Design efficiency
increases while design time is lowered. Forward and back annotation is still used to
communicate changes between schematic and layout design representations. For more
information, please refer to Working Concurrently With Other Users on page 102.
Creating PCB Rule Areas Through Rule-Area Schemes
Beginning with the Master scheme, rule-area schemes give you the ability to segment areas of a
board into distinct regions and then apply physical/manufacturing rules to each area using the
default net class in the Trace & Via Properties spreadsheet (Default) and the default rules in the
Clearances spreadsheet (Default Rule).
For example, when a certain area of a board contains many critical connections between
components, you can define a board area that encompasses this region, and then apply trace and
via rules (e.g. trace width, number of vias) that promote signal integrity within this critical
board area. For more information, please refer to Creating Schemes to Represent PCB Rule
Areas on page 117.
Creating Net Classes to Group Rule-Area Nets More
Extensively
After you define (Default) class and (Default Rule) constraints for a rule-area scheme, which
creates the general constraint values for a scheme, you can create additional net classes within a
scheme to further group nets with physical requirements that are not fully satisfied by the
scheme's default net class constraints.
There is no limit to the number of classes, or hierarchical classes within a specific net class. You
can separate nets into increasingly constrained sub-groupings to implement requirements for
Before You Begin Using CES
nets that generate the most demanding signal integrity challenges. For more information, please
refer to Creating Net Classes on page 139.
Creating Constraint Classes to Group and Define Net
Constraints
Starting with the (All) constraint class, you can define net constraints and then create additional
constraint classes and hierarchical constraint classes under a particular constraint class. Unlike
net classes, which give you the ability to group and define board property constraints, you use
constraint classes to group and define electrical and signal integrity constraints such as net
properties, crosstalk estimations, and length or time of flight delays. For more information,
please refer to Creating Constraint Classes on page 147.
Verifying Design Constraints
When physical routing results are back-annotated from a router (e.g. Board Station RE,
Expedition PCB) into CES, the physical routing results can be used to verify specific CES
constraints. Physical routing results that are brought into CES are called actuals.
When CES is connected in such a manner, the CES Constraint Spreadsheet is updated to include
the actual value/routing results as well as a clear visual indication of how well the constraint(s)
associated with an actual are performing. For example, when the actual delay for a net is too
close to either its minimum or maximum delay constraint, or exceeding either value, the CES
field that displays the actual is backlighted in red or yellow to indicate that the actual exceeds,
or comes close to exceeding, the constraint threshold. For more information, please refer to
Validating Constraints Against PCB Actuals on page 108.
Verifying Simulated Constraints
When you use ICX
Pro
Verify as part of your constraint-driven design flow, you can

generate actuals for simulated constraints like edge-rate delays, and overshoot/ringback
voltages. On the CES Spreadsheet Nets page, the Simulated Delays and Overshoot/Ringback
constraint groups require ICX Pro Verify for actuals generation. For more information, please
refer to Updating Electrical Net Data and Results on page 112.
In preparation for using CES, please make sure that you are aware of the following general
considerations and requirements:
During invocation, CES checks to see if your WDIR variable includes at least one
writable location. When this requirement is not met, CES will not be launched, and will
provide a message box stating that CES cannot be launched. At least one entry in the
environment variable WDIR must be a writable directory. To fix this, you must adjust
your WDIR variable to include at least one writable location.
When you launch CES on a read-only .prj file, CES will open in read-only mode. When
CES unexpectedly opens in read-only mode, you should check to ensure that the .prj file
is not flagged as read-only and is instead writable.
In the event that CES reports an error message that includes a UID number (e.g.
507,692,52), you should run CES Diagnostics to check constraints and attempt to fix
the error. For more information, please refer to Checking Constraints and
Synchronization on page 105.
When your design includes them, single-pin nets are represented as a unified net called
(Net0)-1:X. You must access this special net when assigning Net0 nets to a constraint
class and net class, or when defining single-pin net constraints. For more information,
please refer to Defining Constraints for Single-Pin Nets on page 181.
CES documentation now refers to board-area schemes as rule-area schemes. This
change is for the purpose of being consistent with the nomenclature used in the PCB
layout software and documentation used in CES design flows.
When rolling back constraint changes made in CES, the forward and back annotation
indicator lights for your design flowdo not reflect these undo actions. For example, after
you make a single change in back-end CES and then rollback that change, your back-
end system will still indicate that you need to perform back annotation.
In the event that you receive the following message (or a similar message): Violations
in the iCDB have been detected. Affected objects and constraints will remain disabled in
the CES user interface. Please contact Customer Support for assistance. You must
contact customer support to resolve the database issue and return to your normal CES
operating environment.
Depending on the design flow you are using, the invocation tool from which you
launched CES may or may not save your changes by default. In order to keep from
losing CES data, please ensure that you understand the unique save process of your
design system, and use it appropriately to save CES constraints within each applicable
session. For example, DxDesigner automatically saves schematic data and CES
constraints, but PCB layout tools require an explicit save before they will write PCB
layout changes and CES constraints to disk. When making CES change in a session
launched from a PCB layout tool, it is important understand the following:
o All changes made in CES are reflected in the layout invocation tool after you exit
CES.
o You can send pending CES changes to the layout tool during the active CES session.
To do so, at the bottom-right corner of your PCB layout tool, click the rightmost
status indicator to load the changes into the back-end.
When you update your PCB board stackup after already having defined z-axis
clearances in CES, the clearance rules will become corrupted or lost. You must re-enter
them in CES.
When working in CES sessions launched from Expedition PCB, you cannot change
reference designator prefixes through the CES settings dialog box. To update these
prefixes in your back-end CES database, please modify them in a CES session launched
from the front-end, and then forward annotate.
A constraint cell will show # when the precision is too low to display a meaningful
value. For example, 0.000435 V shows # when the precision is set to 3. With precision
set to 4, it shows 0.0004. To set precision, please refer to To Set Notation on
page 64.
When exporting constraints, CES uses the native concurrent unit type. When
reimporting constraints into CES, you must set the unit type afterward.
When running a script that does not account for key presses of OK/Cancel message
boxes, you can set the following user environment variable that chooses OK by default:
VBAE_NO_DIALOGS = 1
This version of CES includes the following additional keyboard shortcuts:
o To highlight all data on a spreadsheet page, press Ctrl+A.
o To switch between dockable windows, press Ctrl+Tab.
In this version, z-axis clearances are not applied between segments of the same net.
For this version, only I/O Designer I/O Standard is accessible and modifiable through
CES. All other I/O Designer constraints are not available for this version.
An electrical net will not be created when both ends of a resistor are connected to the
same instance of a device.
For this version, cross probing will not work correctly when multiple cross probe servers
are running. To make sure that just one cross probe server is running, turn on cross
probing fromCES (Setup > Cross Probing) or the schematic or layout design tool from
which you launched CES.
Differential Pairs Conversion
When CES converts differential pairs between CES database formats, some differential pairs
may not convert successfully; however, they are preserved in the old format and are still valid.
In the event that this occurs, CES provides a dialog box that indicates that some differential
pairs could not be converted, and CES has marked these with the pin icon. In order to redefine
one or more of these differential pairs, you must delete them.
Note
You do not need to redefine differential pairs that could not be converted to the EE 7.x
CES database format. Although CES preserves these differential pairs in the previous
format, they are still applicable to your 7.x design.
Figure 2-2. Differential Pair That was not Converted
When deleting differential pairs marked with a pin icon, another dialog box is displayed that
indicates that each net that comprises the differential pair might be merged into another
electrical net, removing the ability to recreate the current differential pair.
Importing a Layout Template
When your design data is limited to just schematic data, you can import a layout template into
CES sessions launched from your front-end design system. For example, a DxDesigner design
with no back-end data is a candidate for this import option. Doing so is useful when a logic
engineer wants to define physical constraints based on an accurate board-layer configuration
before the first forward annotation has occurred, or a back-end design exists at all.
To Import a Layout Template
1. From the File menu, click Import, and then click Layout Template.
2. From the Import Layout Template dialog box, next to Select layout template, click the
dropdown, and then click the template you want to use.
3. After you are sure of your selection, click OK.
Importing a 2005.x Ces.prefs File
In versions of CES prior to 7.x, CES stored some settings in a preferences file called Ces.prefs
that was written to the top level of your WDIR location. To make the transition between a
2005.x release and 7.x easier, you can import your preferences file into CES 7.x. It is important
to note that CES no longer writes this preferences file. Importing a Ces.prefs file is intended to
be an optional, one-time transition step between releases.
To Import 2005.x CES Preferences
1. From the File menu, click Import, and then click Preferences File.
2. From the Open dialog box, navigate to the .prefs file that you want to load, and then
click OK.
Design Architect/Board Architect-CES-Board Station XE
When using this flow, please be aware of the following considerations and requirements:
When the Er for a conductive layer is "0", the Er of the adjacent dielectric layer is passed
on to the CES Stackup Editor.
When the environment variable DES_ARCH_PKGS_TO_LOAD the order of
arguments must abide by the following conventions:
o ces_da must be before xprobe_da
o xprobe_da must be the last argument
When your HOME variable includes spaces, cross probing fromDesign Architect/Board
Architect to CES will not work.
The MGC_PKG_XINFO environment variable must not be set for use in this flow. This
is a legacy environment variable that will cause problems during design annotation.
When you change your Board Station XE license to ICX_pro HSR, Board Station XE
comes up in the same mode (i.e. without the previous net classes and/or net properties).
For Design Architect, during initial creation of the CES database, net_type properties on
schematic nets will trigger the creation of a net class in CES using the default values
when a rule is not defined in the TECH file. After initial creation of the CES database,
additional net_type properties that do not have corresponding rules in the TECHfile will
be ignored.
When using $change_design_property in Design Architect, you may have to close a
sheet and then re-open it to see the changes.
For this version, prior to cross probing between Design Architect and CES, you must
repackage.
When you need to delete the existing Board Station XE CES database but do not want to
delete the entire constraints database, back-annotate all constraints from Board Station
XE to Design Architect, delete the Board Station XE database, and then run forward
annotation to re-populate the Board Station XE CES database.
Display unit changes you make in XE-CES are just for the current CES session. To
change the units across the flow, you must do so from your layout software by
modifying board geometry units.
Design Architect/Board Architect-CES-Board Station RE
To activate CES from within an EN environment, you must enable the
MGC_ENABLE_CES environment variable. The value you use for this environment
variable is 1.
When the environment variable DES_ARCH_PKGS_TO_LOAD the order of
arguments must abide by the following conventions:
o ces_da must be before xprobe_da
o xprobe_da must be the last argument
When your HOME variable includes spaces, cross probing fromDesign Architect/Board
Architect to CES will not work.
When you change your Board Station RE license to ICX_pro HSR, Board Station RE
comes up in the same mode (i.e. without the previous net classes and/or net properties).
The MGC_PKG_XINFO environment variable must not be set for use in this flow. This
is a legacy environment variable that will cause problems during design annotation.
For Design Architect, during initial creation of the CES database, net_type properties on
schematic nets will trigger the creation of a net class in CES using the default values
when a rule is not defined in the TECH file. After initial creation of the CES database,
additional net_type properties that do not have corresponding rules in the TECHfile will
be ignored.
When using $change_design_property in Design Architect, you may have to close a
sheet and then re-open it to see the changes.
For this version, prior to cross probing between Design Architect and CES, you must
repackage.
When you need to delete the existing Board Station RE CES database but do not want to
delete the entire constraints database, back-annotate all constraints from Board Station
RE to Design Architect, delete the Board Station RE database, and then run forward
annotation to re-populate the Board Station RE CES database.
Display unit changes you make in RE-CES are just for the current CES session. To
change the units across the flow, you must do so from your layout software by
modifying board geometry units.
DxDesigner-CES-Expedition PCB
You must have a DxDesigner concurrency license (dxconcurrent) in order to use
multiple copies of DxDesigner-CES or standalone CES on the same design.
Starting and Exiting From CES
You can only define the Plane to Plane constraint at the (Master) scheme level. You
cannot define it for user-created schemes or rule areas. For more information about this
constraint, please refer to Plane To Plane on page 263.
Keyin Netlist-CES-Expedition PCB
When using a keyin netlist to represent design connectivity instead of traditional schematic
capture data, forward annotate before you begin using CES to modify constraint data. Aside
from standard communication of design changes, you only have to perform this step once. You
can do so before or after you enable CES in a keyin netlist flow.
Expedition TeamPCB and XtremePCB
TeamPCB (used for concurrent PCB design) and XtremePCB (used for dynamic/interactive
group PCB design) are integrated to use CES in this release. However, CES has limited support
with TeamPCB. Constraints you define using CES are carried forward into the split designs.
When you are editing a split design, you can change constraints on the Trace & Via Properties
and Clearance tabs inside CES. However, that information only applies to the current split
design and will not be joined into the main design. Other tabs within CES are not editable inside
a split partition.
Because CES is a design constraint system that can be used to display and modify the design
constraints produced by and intended for many of Mentor Graphic Corporation's front-end and
back-end PCB design solutions, you can start CES through a host of MGC applications. Please
refer to the table below to determine the command you must use to launch CES from an
associated MGC PCB design tool.
When users invoke multiple CES sessions from the same design tool on the same design, all
sessions are read-write. For example, after you launch CES from DxDesigner, your co-workers
can launch CES from the same DxDesigner design and concurrently make changes. This is
especially useful for large designs that require multiple schematic and layout designers working
simultaneously on each end.
Prerequisites
Your WDIR environment variable must include at least one writable location or
directory. CES will not launch until you satisfy this requirement.
To Start CES
Refer to the following table to launch CES fromone of the following schematic capture or PCB
layout design tools.,
Results
CES opens and displays the constraint set for the front-end or back-end design. When the .prj
file for the design is read-only, CES opens in read-only mode as well.
Starting CES in Standalone Mode
You can start CES in standalone mode (independently), fromboth the Windows Start menu and
the Mentor Graphics Dashboard. Please refer to the procedures below for the appropriate
instructions.
To Start CES From the Start Menu
1. From the Start menu, in your Mentor Graphics program folder, expand Constraint
Entry, and then click Constraint Editor System.
2. From the Open Project dialog box, browse to the .prj file for your design, and then click
Open.
To Start CES From the Dashboard
From the Mentor Graphics Dashboard, with a project actively selected, expand Board-Level
(PCB) Design Toolbox, and then double-click Constraint Editor System.
Table 2-1. Starting CES
Design Tool Menu Path
Board Architect Setup > Constraints
Board Station LAYOUT Setup > Constraints
Board Station RE Setup > Constraints
Board Station XE Setup > Constraints
Design Architect Setup > Constraints
Design Capture Tools > Edit Constraints
DesignView Workspace > Integration
View tab > Constraints
DxDesigner Tools > Constraint Editor
System
Expedition PCB Setup > Constraints
Cross Probing Between Design Systems and CES
To Exit From CES
From the CES main window, click x, or from the File menu, click Exit.
Viewing Constraint Database Log Files
CES uses a database to interact with the host design system and any available concurrent users.
To view the associated log files, from the File toolbar, click ; or, from the File menu, click
Log Viewer.
Tip: To learn more about using the File Viewer, from its Help menu, click Contents.
Cross Probing Between Design Systems and
CES
You can enable cross probing between CES and the design system from which you launched
CES. Cross probing, also known as cross select, works in a bi-directional fashion. When you
select a design object in your schematic capture of PCB layout design system, the design object
is also selected in CES. Selecting a design object in CES results in your design system making
the same selection.
Tip: You can set up CES to enable cross probing by default. To learn how to do this,
please refer to Setting Up CES on page 56.
Regardless of your level of experience with CES and its spreadsheet display of design objects
and constraints, cross probing is usually the most efficient method of selecting design objects.
In terms of precision, it is the most accurate way to ensure that you are modifying constraints of
the appropriate target net.
To Cross Probe From Your Design System to CES
1. From the Setup menu, click to enable Cross Probing.
Alternative: From the File toolbar, click .
2. In your schematic capture or PCB layout software, click a design object (e.g. net,
component).
Result: The design object is selected in CES.
To Cross Probe From CES to Your Design System
1. From the Setup menu, click to enable Cross Probing.
Setting Up CES
2. From the CES Constraint Spreadsheet, click the leftmost column of a design object. or
press Ctrl+J to select the current row.
Example: In the following illustration, the PCI constraint class is selected for cross
probing.
Figure 2-3. Cross Probing From CES
Cross Probing From the Navigator
When enabled, you can also cross probe from the Navigator to select all nets that are part of a
hierarchical object like a constraint class or net class. When you do so, your invocation tool will
select all associated nets from within your logic or layout environment.
Setting Up CES
You can specify CES options to customize the most appropriate CES environment for a design.
These settings, as well as the settings associated with the units that are displayed within the
spreadsheet editor, are unique to each design that you work with in CES. Because CES saves
settings as part of each design, you have the ability to maintain custom settings for each design
that you work with in CES.
Specifying Design Preferences
You can specify design configuration preferences such as default tolerances for time and
distance delay, the parallelism mode to use, reference designator prefixes, and voltage
assignments for power nets. Design preferences are settings that affect an entire design rather
than specific design objects (e.g. layers, nets).
To Set Design Configuration Preferences
1. From the Setup menu, click Settings.
2. From the Settings dialog box, click Design Configuration.
3. Under Default tolerances, specify a default physical and electrical tolerance for delay.
This is the allowable deviation for any delay constraints you define in CES.
4. Under Parallelism mode, specify whether the router should report parallelism hazards
cumulatively, or separately for each segment. When in cumulative mode, each segment
Setting Up CES
that comprises a group will report a hazard. For example, when the parallel run length
needs to be less than 400th, and each of the 3 segments in a group are 134th, each
segment will show a violation although they all appear to be 266th shorter than required.
The violations are reported because the sum of 134th + 134th + 134th is 402th, which is
greater than 400th.
Note: For cumulative calculations, segments smaller than 100th are ignored and not
used to produce the cumulative length. Using the above example, five 98th segments
result in a mathematical total of 490th, but because each segment is less than 100th, all
are ignored by the router and no hazard would be reported.
5. After you finish, click OK.
To Specify Electrical Net Preferences
Note
You can only modify electrical net preferences when in a CES session launched from the
front-end (i.e. schematic capture), or standalone CES.
2. From the Settings dialog box, under Design Configuration, click Electrical Net.
3. Specify the maximum number of electrical nets that may comprise a physical net.
4. Specify the net pin count threshold to use to determine whether a net is potentially a
signal net or a power net.
Tip: Identify the power net in your design with the smallest number of pins, and then set
this value to that number minus one. For example, if the smallest power net in a design
contains 30 pins, set this value to 29.
5. Specify whether IBIS part models should be used for electrical nets.
6. For component names, specify whether IBIS names (e.g. icx_part_model) should be
used for mapping purposes. By default, the part model name is used.
To Specify Discrete Component Prefixes
Note
You can only modify discrete component prefixes when in a CES session launched from
the front-end (i.e. schematic capture), or standalone CES.
Setting Up CES
2. From the Settings dialog box, under Design Configuration, click Discrete Component
Prefixes.
3. Specify all possible reference designator prefixes for the parts in your design.
Rule: When your design uses reference designators that are of the format YYYRNN
(i.e. schematic sheet, reference designator prefix, unique instance), append a # to each
discrete component prefix that you define here. For example, instead of using just C to
define the discrete component prefix for capacitors, use #C.
Note: When a part type has instances with multiple reference designators, CES
determines that a part is a discrete if at least one of the refdes prefixes is specified. For
example, part type RES has instances R1 -> R10 and X1 -> X10. When either R or X are
in the list, the part and its instances will all be considered resistors.
In the following example illustration, each discrete component has at least 2 defined prefixes.
Connector discretes have 3 prefixes: P, J, and PJ.
Figure 2-4. Example Reference Designator Prefixes
2-Pin Schematic Symbols
Resistor packs with 2-pin schematic symbols are properly identified as series connections.
When you are using the DxDesigner-Expedition PCB constraint-driven design flow, any
combination of 2-pin or full-pack symbols are identified as series devices. In the other flows
(e.g. Design Architect-Board Station XE), you must use 2-pin schematic symbols to ensure CES
recognition.
To Specify Powers and Grounds
2. In the Settings dialog box, under Design Configuration, click Powers and Grounds.
Setting Up CES
Tip: You can modify the voltage value for an existing power net or ground net by
clicking within its Voltage field to change it. To delete one or more existing power net
or ground net designations, use click, Ctrl-click, or Shift-click, and then click .
3. To create one or more power nets or ground nets, click .
4. Fromthe Select Power Nets dialog box, enter a net name filter, or leave the default entry
(*) to select from all nets, and then click .
5. From the list of proposed nets, click the check box associated with each power net or
ground net you want to add, and then click OK.
Tip: To select all listed nets, click . To unselect all nets, click . To clear your list of
selected nets and restart the net selection process, click . Nets with a pin count that
exceeds the threshold will be selected automatically.
6. For each power net or ground net you chose, enter a Voltage value.
Example: Each ground net will typically require a voltage value of 0.0000.
7. For each power net you chose that requires constraints, select Visible.
To Specify Other Preferences
Note
You can modify certain actuals preferences when in a CES session launched from the
back-end (i.e. PCB layout). The remaining preferences must be modified from a front-
end (i.e. schematic capture) CES session.
2. From the Settings dialog box, under Design Configuration, click Other.
3. To have CES automatically display updated actuals produced by your layout tool during
interactive routing, activate the Layout Dynamic update checkbox.
Note: To do the same for thermal actuals, click to enable Thermal Dynamic update.
4. To automatically update actuals upon CES invocation, activate the Auto update on start
up checkbox.
5. To automatically export actuals to schematic capture for display in CES, click to enable
Export actuals to front-end.
6. To show alerts in CES front-end sessions that updated actuals can be imported, click to
activate the appropriate checkbox.
7. To automatically run CES diagnostics upon exit, activate the associated checkbox.
Setting Up CES
8. To automatically update nets that use a constraint template when any of the constraint
template values are updated, click to activate Automatically apply templates. When
activated, you never need to re-apply constraint templates to individual nets to which
they are assigned.
9. To store log files generated during your CES session locally at your WDIR location,
click to enable the appropriate checkbox.
10. When cross probing from CES, to have your logic or layout tool select no more than a
maximum number of nets, enter a value in the Maximum number of selected nets field.
11. Specify how old a log file needs to be before archiving it.
12. When using the Board Station XE flow, to change the number of seconds a user can
reserve a constraint cell for editing while working concurrently, in the Maximum
locking timeout field, enter a different value.
Setting Display Options
Please use the procedure below to set display options for CES.
To Set Display Settings
2. From the Settings dialog box, click Display.
3. Under Window Settings, specify whether the browser and log windows should be
synchronized, and whether CES should crossprobe between itself and schematic-entry
or layout, by default.
Note: When setting display options for CTE, Set the default crossprobing mode to ONis
intentionally grayed out and not available.
4. To turn on cross probing from the Navigator, click to enable its checkbox.
5. Click to enable row, column, or header highlighting and indication of remotely modified
cells. Both are useful when working concurrently.
6. To show row numbers, click to enable the associated checkbox.
7. Enable or disable the CES splash screen by clicking the appropriate checkbox.
8. To automatically show differences between parent and child objects, click to enable the
associated checkbox.
Setting Up CES
Setting General Options
Please use the procedure below to set general options for CES.
To Set General Options
2. From the Settings dialog box, under Display, click General.
3. Under Initial Zoom Level, specify the default size of spreadsheet fonts and rows by
entering a percentage value. As you increase this value, the size of spreadsheet fonts
increase.
4. Under Inactive Draw Combobox Buttons, specify when CES should display
comboboxes within a spreadsheet field. When you enable this option, any cell that can
display a dropdown list will always display the down arrow box. When disabled, the
dropdown box for a cell is displayed after you click within the respective cell.
5. Under Spin Edit Control, specify whether integer value spreadsheet fields should
display up and down arrows beside them when clicked. These arrows are used to
increase or decrease the integer value within a cell without using the keyboard.
6. Choose the preferred action of the LMB when you double-click it. You can choose
expand cell, rename cell, or no action.
7. Choose the preferred action that occurs after you press the Enter key within a cell. You
can choose to move to up, down, left, or right from the current cell.
8. Under Tolerances, specify the following values:
Design tolerance of CES constraints compared against actual back-annotated design
values. In the Constraint violation warning field, enter a percentage value.
Example: When the Constraint violation warning field contains 90%, actual values
that are ninety or a greater percentage of the associated constraint value are
highlighted in yellow to indicate an actual that is close to the acceptable constraint
value. When the actual value exceeds the constraint value, the field is highlighted in
red.
Acceptable threshold CES uses when applying constraint templates to nets. In the
Template match threshold field, enter a percentage value. For less similarity, reduce
this value; for more similarity, increase this value.
To Set Fonts and Colors
Setting Up CES
2. From the Settings dialog box, under Display, click Fonts and Colors.
3. Specify the header font and cell font appearances for defaults, constraints, and
properties.
4. Specify the header font, cell font, and background color appearance settings for actuals,
read-only values, static values, and disabled cells.
5. To help you identify changes made by concurrent CES users, specify background colors
and cell fonts for edited cells and locked cells.
6. To change the appearance of cells you modify from within CES, change the current
settings for Modified cells.
7. Specify the background cell color used to indicate violations of type caution or error.
8. Specify the background color for other/hierarchical items like Different, Default Value,
and Override Value.
9. Specify the color used to indicate the presence of a comment mark.
10. Specify the color and font used to display content in the CES Output window. Although
the heading for this column of the dialog box states that all colors are background colors,
Font, Error, Warning, and Path rows are used to set textual colors.
Setting Units for the CES Spreadsheet
You can specify the units CES displays for the different types of constraint data. When you set
these units, CES uses your preferences to format the display and entry of values into CES. The
design units you use in a specific front-end or back-end systemare not modified by units setting
that you make in CES. Because units that you specify for a design in CES are used on a design-
by-design basis, you can use different units for each design that you work with in CES.
In addition to setting the units to use and display, you can also specify the precision and format
of electrical units that CES displays. For example, you can use engineering notation with a
precision of 3 digits after the decimal point, scientific notation with 2 digit post-decimal point
precision, or choose not to format electrical units and display full precision.
Note
When working in a Board Station XE or Board Station RE flow, units changes you make
in XE-CES or RE-CES are just for the current CES session. To change the units across
the flow, you must do so from your layout software by modifying board geometry units.
Setting Up CES
To Set Display Units
2. From the Settings dialog box, under Display, click Display Units.
3. From the Display Units page, for each unit type, specify the unit and precision that you
want to use. Please refer to the table below if you need help determining the meaning of
a specific unit.
Example: For linear values, to use millimeters, click within its Unit field, and then click
to select mm.
Result: After you modify the unit and precision for a specific unit type, the associated
Example field updates to show you a preview of the display unit setting as values will
appear in the CES Spreadsheet.
4. Optionally, to keep your units synchronized with the back-end design system, click to
enable the check box.
Table 2-2. Available Display Units
Unit Type Unit
Linear You can choose from the following units:
in inch
th thousandth of an inch
mm millimeter
um micrometer
nm nanometer
Angle You can choose from the following units:
deg degree
rad radian
' foot
" inch
Capacitance You can choose from the following units:
F farad
mF millifarad
uF microfarad
nF nanofarad
Voltage You can choose from the following units:
kV kilovolt
V volt
mV millivolt
uV microvolt
nV nanovolt
Setting Up CES
To Set Notation
2. From the Settings dialog box, under Display, click Notation.
3. From the Notation page, under Electrical units, specify the format and precision you
want to use for electrical units.
Inductance You can choose from the following units:
H henry
mH millihenry
uH microhenry
nH nanohenry
Power You can choose from the following units:
kW kilowatts
W watts
mW milliwatts
uW microwatts
nW nanowatts
Velocity You can choose from the following units:
in/ns inch per nanosecond
m/s meter per second
%c percentage of the speed of light
Resistance You can choose from the following units:
MOhm mega-ohm
KOhm kilo-ohm
Ohm ohm
mOhm milli-ohm
uOhm micro-ohm
Time You can choose from the following units:
s second
ms millisecond
us microsecond
ns nanosecond
ps picosecond
Current You can choose from the following units:
A amp
mA milliamp
uA microamp
pA picoamp
Table 2-2. Available Display Units (cont.)
Unit Type Unit
Modifying Simulation Settings and Stimulus
Example: To use SPICE format with a precision of 5, click the radio button next to
SPICE, and in its associated Precision field, enter 5.
Rule: When you do not want to format electrical units and want to use full precision,
click the Do not format electrical units and use full precision check box.
Rule: When the precision is too low to display a meaningful value, a constraint cell will
display # instead of a number.
4. Under Regional settings, specify the decimal point symbol to use, the number of digits
to display after the decimal point, and other associated electrical unit display properties.
5. To suppress the display of trailing zeros, click to activate the Suppress trailing zeros
check box.
Example: When using engineering format with a precision of 5, a spreadsheet value of
8.12300 would be displayed as 8.123. Without suppressing trailing zeros, all five post-
decimal values are displayed (i.e. 8.12300).
Reusing Settings in External Designs
You can reuse your CES environment settings in other designs. You do so by exporting to a file,
and then importing that file in any external CES session. This is useful for maintaining the
workgroup standards of a large design team, or reusing your own design settings.
To Reuse Settings
1. From the File menu, click Export, and then click Settings.
2. From the Export Settings dialog box, specify a path and filename, and then click Save.
3. Optionally, communicate this settings file (.ini) to other engineers.
4. In any external CES design, from the File menu, click Import, and then click Settings.
5. In the Import Settings dialog box, select the settings file saved previously (e.g.
workgroup.ini), and then click Open.
When you use ICX Pro Verify as part of your CES constraint-driven design flow, you can
modify the simulation stimulus and settings used by ICXPro Verify to generate actuals data that
are displayed on the CES Spreadsheet Nets page (Simulated Delays group and
Overshoot/Ringback group). The Noise Rules page also displays an ICX Pro Verify simulation
actual as the Crosstalk SimActual cell. Aside frommodifying existing simulation templates and
stimulus, you can also create new ones.
Note
In order to modify simulation settings and stimulus, you must be using ICX Pro Verify
within your design flow.
Common Tasks
Modifying Simulation Stimulus on page 71
Modifying Simulation Settings
You can modify simulation settings used by ICX Pro Verify to alter measurement, simulation
engine, coupling, and corner-case simulation options. For example, you can choose among
ADMS, ICXSIM, and HSPICE simulation engines while allowing for simulator substitution,
when appropriate.
To Modify Simulation Settings
1. From the Edit menu, click Simulation, and then click Simulation Settings.
Note: When the CES Spreadsheet Constraint Templates page is active, you must make
another page active to enable these menu options.
2. From the Simulation Settings dialog box, modify any appropriate settings. After you
finish, click OK. Refer to the tables below for a description of each option.
Please refer to the following table for simulation settings.
Table 2-3. Simulation Settings (Measurement Tab)
Option Description
Start cycle Determines which pulse is used to start the measurement.
The valid start cycle is an integer between 1 and 300.
End cycle Determines which pulse is the last measurement point.
The valid end cycle is an integer between 1 and 300 and
must be larger than the start cycle value.
Edge The edge is selected by using the dropdown arrow and
selecting Rising, Falling, or Both from the drop down list.
Corner case Gives you the ability to select the corner case within the
symbol model. If not selected, the model determines the
corner case.
Total crosstalk only A single simulation is used to measure crosstalk on the
victim net. During the simulation, all aggressor nets are
actively driven.
Please refer to the following table for coupling settings.
Total plus individual
contributions
The simulation described in the first mode is used to
measure total crosstalk for each of the specified victim
states. If there is more than one aggressor, simulations are
performed to find the crosstalk due to each aggressor. In
these simulations, only the aggressor whose contribution
is to be measured is transitioned, all other aggressor nets
are tri-stated or driven to a fixed logic level. In these
simulations, drivers on the driven nets are selected as in
the first mode.
Victim logic states Defines the victim logic states simulated during crosstalk
analysis.
Table 2-4. Simulation Settings (Coupling Tab)
Option Description
Include trace to trace
coupling
If checked, Delay and SI simulation include nets that are
electrically coupled to the target net for simulation.
Pin to Pin If this option is checked, coupling within the package of
devices are modeled during simulation. To use this feature
successfully requires the device to have an IBIS model
that utilizes a separate package section or file to provide
mutual inductances and capacitances between pins.
Self-coupling If this option is checked, any coupling between traces is
modeled in the simulation, and they are evaluated during
simulation. Self coupling has a significant effect for traces
that double back upon themselves (serpentines). The
disadvantage of this option is that it increases simulation
effort.
Arbitrary angles If this option is unchecked, the simulator assumes that
traces that are not parallel to each other are not electrically
coupled. If this option is checked, the electrical coupling
for traces that are in close proximity (as defined by the
remaining settings) but not parallel are modeled. Enabling
this option increases trace-modeling accuracy for traces
that are not parallel or at ninety degrees. It also
significantly increases the amount of processing that must
be performed when the trace geometries are extracted and
add additional elements to the circuit that must be
simulated, both of which increase the simulation effort.
Table 2-3. Simulation Settings (Measurement Tab) (cont.)
Option Description
Please refer to the following table for additional simulation settings.
Consider nets within Only the nets within the specified distance are considered
for electrical coupling. The values in this field is validated
as being positive and less than 500 (th).
Ignore segments shorter
than
Any aggressor net segments that are shorter than this
length are ignored during crosstalk simulation of the
analyzed net.
Trace to area fill coupling Enabling this feature improves the accuracy of trace
modeling and increases trace extraction and simulation
times.
Stimulus for neighboring
nets
This setting has the following selections:
Passive Neighboring nets are held at a fixed state. If
all the drivers on a neighboring net are tri-stated, the
neighboring net is not driven. If they cannot be tri-
stated, the neighboring nets are low logic state.
Switch with Neighboring nets are driven with the
same stimulus as the net being simulated.
Switch against Neighboring nets are driven with the
opposite stimulus as the net being simulated.
Independent The neighboring net uses the stimulus
specified when it is a target net. This option is used
when the Simulation Control dialog Simulation
settings field, Use CES net spreadsheet radio
button is selected. In this case each target net can
independently be assigned an appropriate stimulus.
Table 2-5. Simulation Settings (Settings Tab)
Option Description
Simulation engine This setting has the following selections:
Auto The system attempts to use the fastest
simulator that is compatible with the available models.
Fixed This radio button enables the dropdown list to
be displayed (ICX Sim, ADMS, and HSPICE). From
the dropdown list, select the simulator. If at simulation
time the simulator cannot be used, an error message is
reported in the Simulation Status dialog box.
Table 2-4. Simulation Settings (Coupling Tab) (cont.)
Option Description
Simulation resolution This setting has the following selections:
Auto The system determines the time step for the
simulator based on heuristics that include the fastest
driver nominal edge rate obtained from the IBIS
models of the selected nets.
Fixed You must enter the simulation time step value.
This value must be a positive, real number from 0 to
less then 1000 with no more than two decimal places.
Simulation run time This setting has the following selections:
Auto This option allows the system to determine the
simulation run time. The system ensures that the
simulation run time is as long as it is required to
simulate all specified measurement cycles. The tool
also adds additional simulation time for the net to
settle to a reasonably steady state. This additional time
is chosen using a heuristic that takes into account the
total time of flight for the net.
Fixed The option allows you to specify the
simulation time as an absolute value.
Modeling of interconnect
losses
This setting has the following selections:
Lossless The transmission lines are perfect
conductors (no loss).
DC Lossy The trace material is used to calculate
conductor DC losses.
AC Lossy The traces AC and DC losses are
calculated and has the greatest accuracy.
Non-monotonic models Because allowing simulation with non-monotonic IV
curves is dangerous and may cause non-convergence
during simulation due to loading conditions, only
advanced users should enable this checkbox. When it is
enabled, simulation preview generates warnings for these
types of curves. When it is disabled, simulation preview
generates errors, and will not allow simulation.
Table 2-5. Simulation Settings (Settings Tab) (cont.)
Option Description
To Create a New Simulation Settings Template
2. From the Simulation Settings dialog box, next to the Simulation setting template field,
click .
3. From the Create new simulation settings template dialog box, specify a name, the initial
values to use for the new template, and then click Create.
To Load an Existing Simulation Settings Template
2. From the Simulation Settings dialog box, next to the Simulation setting template field,
click .
3. From the Load into current simulation settings template dialog box, specify the use of
system defaults, or click to enable Load from the template below, and then click the
browse button to select a template.
Via modeling This setting has the following selections:
Advanced model This option allows the tool to
estimate the inductance and capacitance of each via
based on its individual geometry. The resulting values
are used to characterize a Pi network models for the
vias.
Single Pi network This option allows you to enter the
capacitance and inductance values to characterize the
Pi network model that is used for all vias with a
particular span in the design, regardless of their
geometries. The Setup > Setup Parameters dialog via
characteristics is used for modeling.
Simple star network This option allows you to enter
the capacitance and inductance values that are used to
characterize the Star network model that is used for all
vias with a particular span in the design, regardless of
their geometries.
Table 2-5. Simulation Settings (Settings Tab) (cont.)
Option Description
Note: When loading from the template below, make sure you click a template in the
Available Templates box.
4. After you finish, click Load.
Modifying Simulation Stimulus
You can modify simulation stimulus settings used by ICX Pro Verify to control cycle and pulse
times, bit patterns, and sequence repetition.
To Modify Simulation Stimulus
1. From the Edit menu, click Simulation, and then click Simulation Stimulus.
2. From the Stimulus dialog box, modify any appropriate settings. After you finish, click
OK. Refer to the tables below for a description of each option.
Note: To switch to an advanced stimulus, enable Advanced stimulus, and then click
Advanced Stimulus Editor.
Please refer to the following table for basic stimulus settings.
Table 2-6. Stimulus Settings (Basic Stimulus)
Option Description
Initial state This is the starting state of the stimulus, before the first
transition. The options are High, Low, and Model. The
Model option uses the state from the IBIS model (low for
non-inverting). Your selection may cause the Cycle and
pulse times display to change.
First transition The value is the time from the initial state to the first
transition of the stimulus (0.001 to 100).
Cycle and pulse times Look at the arrows defining a region of the waveform. The
top number defines the cycle time. The bottomtwo values
define the pulse times of the cycle (0.001 to 100 (ns)).
Frequency Signal frequency. For example, to enter 100 megahertz,
type 100M.
Duty Cycle The percentage of time the signal is in its logic high (i.e.
active) state.
Please refer to the following table for advanced stimulus settings.
Table 2-7. Stimulus Settings (Advanced Stimulus)
Option Description
Sequence This setting has the following selections:
PRBS (pseudo random bit sequence) The random
bits determined by the Bit order field. For example, if
the Bit order field is 5, the sequence length is 2 e5 -1 or
31. The initial State defines the start of the stimulus.
Toggling Is a sequence of 2-bits 0 and 1. The initial
State defines the start of the stimuli.
8B/10B or K character Is a sequence length of 10-
bits. The 8B/10B is an IBMencoding method for 8-bit
data into 10-bit transmission characters. The K
characters are control characters. The Character value
of Dxx.y is used for characters and Kxx.y is used for
control characters.
USB 2.0 compliance Is a sequence that meets the
USB 2.0 specification.
Custom Is a sequence of bits, which you create, or
you can use the Load button to select a bit pattern. Use
the cursor and right mouse button to create your own
pulse sequence. Click the rise and fall edges and drag
the mouse for number of pulses. Use the Save button
to save your custom pulse train.
Bit interval The time duration of one bit.
Period The time from rising edge to the next rising edge or from
falling edge to falling edge.
Duty cycle The percentage of time the signal is in its logic high (i.e.
active) state.
Sequence repetitions Use this field to define the number of times you want the
sequence to be repeated.
Amount (p-p) The amount of jitter, peak-to-peak, and the % of the
period or time determines the width.
Distribution The distribution is Gaussian (noise on a bell curve) or
uniform.
Skip first Skip the specified number of bits.
Show Number of signal eyes to show.
Customizing the Display of CES Windows
To Create a New Simulation Stimulus
2. From the Stimulus dialog box, next to the Name field, click .
3. From the Create new stimulus dialog box, specify a name, the use of system defaults, or
click to enable Copy from the existing stimulus below, and then click the browse button
to select a stimulus.
Note: When copying from the existing stimulus below, make sure you click a stimulus
in the Available Stimuli box.
4. After you finish, click Create.
To Load an Existing Simulation Stimulus
2. From the Stimulus dialog box, next to the Name field, click .
3. From the Load into current stimulus dialog box, specify the use of system defaults, or
click to enable Load from the stimulus below, and then click the browse button to select
a template.
Note: When loading from the stimulus below, make sure you click a stimulus in the
Available Stimuli box.
4. After you finish, click Load.
Related Topics
Validating Constraints Against PCB Actuals on page 108
Related Constraints
Simulation Settings on page 322
Simulation Stimulus on page 324
Customizing the Display of CES Windows
You can customize the display of CES windows to design the most efficient work environment
for the completion of CES tasks. You can toggle the display of specific windows, arrange
windows in a tiled or cascaded fashion, and change the position of toolbars and browser
Customizing CES Toolbars
windows. By activating preservation of display settings, you can maintain a custom work
environment.
To Toggle the Display of Specific Windows and Window Elements
From the View menu, click to toggle the display of a specific window or an element that
appears inside a certain window. You can use the following list to determine window
customization that results from the inclusion or exclusion of each selection:
Tabs Toggle this set of selections to display or exclude specific pages of the CES
Spreadsheet (e.g. Nets, Noise Rules).
Navigator Also known as the browser, toggle this set of selections to display or
exclude the hierarchical listing of CES design elements (such as schemes, net classes,
and constraint classes).
Tip: Clicking the right mouse button on browser items often displays context-sensitive
menus that give you the ability to perform operations directly from within the browser
tree.
Output Toggle this setting to display or exclude the CES log/output window.
Scripting Toggle this setting to display or exclude the CES scripting window.
Status Bar Toggle this setting to display or exclude the status bar that appears at the
very bottom of the application.
Toolbars Toggle this set of selections to display or exclude one of the many CES
toolbars.
To Change the Position of Windows and Toolbars
1. Click-hold the window or toolbar handle of the interface element you want to move.
Note: Window handles are double bars displayed horizontally or vertically depending
on the orientation of a window. Toolbar handles are located around the perimeter of
each toolbar.
2. Move the interface element to position it within CES.
You can customize CES toolbars to create custom sets and groupings of buttons, create new
toolbars, and specify general toolbar display options. In the event that you do not want to keep
your modifications to an existing toolbar, you can reset it to its default grouping of buttons.
Customization of CES toolbars can help to increase the efficiency with which you use CES by
making it easier to access just the toolbar buttons you use. This is helpful to most users because
utilizing only a subset of CES functions is common for many members of a design team.
Prerequisites
None.
General Tasks
You can customize CES toolbars in the following ways:
Modifying Toolbars to Create Custom Sets of Buttons on page 75
Creating New Toolbars on page 76
Specifying General Toolbar Options on page 77
Resetting a Toolbar to the Default Grouping of Buttons on page 78
Modifying Toolbars to Create Custom Sets of Buttons
You can modify CES toolbars to change the order of buttons displayed on a toolbar, add toolbar
buttons to it, and remove toolbar buttons from it. For example, when you only use half of the
buttons on a specific toolbar, you may find it useful to reorder the buttons on the toolbar such
that those that you use are all displayed in the leftmost position of the toolbar instead of being
spread out among the entire width of the toolbar.
Prerequisites
None.
Procedure
1. From the View menu, click Toolbars, and then click Customize.
Alternative: Right-click any CES toolbar, and then click Customize.
2. From the Customize dialog box, click the Commands tab, and then do any of the
following:
To add a button to a toolbar, click the appropriate group selection within the
Categories list box, and then in the list of buttons, double-click and drag a button to a
specific CES toolbar at the top of the GUI.
To remove a button from a toolbar, at the top of the GUI, double-click a toolbar
button and then drag it to any area below the collection of toolbars (e.g. Navigator).
To move a button within a toolbar, or from one toolbar to another, at the top of the
GUI, double-click a toolbar button, and then drag it to another toolbar location.
3. After you finish making changes to one or more toolbars, click OK.
Results
The display of one or more toolbars is now changed to reflect the modifications you have made.
Related Topics
Creating New Toolbars
You can create new toolbars that did not exist previously. Adding a new toolbar takes CES
toolbar customization to the extreme by grouping buttons based on a new set unique to you as a
user. A common use for the functionality is to create a user-based toolbar that includes all of the
buttons that you use most frequently. Because of the large number of toolbar buttons that CES
provides, making your custom set can help you be more efficient with CES when you use just a
specific subset of its functionality.
Prerequisites
None.
Procedure
2. From the Customize dialog box, click the Toolbars tab, and then click New.
3. From the New Toolbar dialog box, in the text field, enter a name for the new toolbar
(e.g. pats_CES_toolbar), and then click OK.
Results
The new toolbar is available for modification. To learn how to add buttons to it or change its
contents, please refer to Modifying Toolbars to Create Custom Sets of Buttons on page 75.
Example of Deleting a New Toolbar
In the following example, you want to delete a custom toolbar that you created but no longer
need.
Customizing CES Toolbars on page 74 Creating New Toolbars on page 76
Specifying General Toolbar Options on
page 77
Resetting a Toolbar to the Default Grouping
of Buttons on page 78
2. From the Customize dialog box, click the Toolbars tab.
3. In the Toolbars listing, click the name of the new toolbar, and then click Delete.
4. After you finish click OK.
5. As a result, the toolbar is no longer available.
Example of Renaming a New Toolbar
In the following example, you want to rename a custom toolbar that you created previously.
2. From the Customize dialog box, click the Toolbar tab.
3. In the Toolbars listing, click the name of the new toolbar.
4. In the Toolbar name text box, enter a different name for the custom toolbar.
6. As a result, the toolbar is renamed and associated with the new name.
Related Topics
Specifying General Toolbar Options
You can specify general toolbar options to control the size and appearance of toolbar buttons.
You can also control whether tooltips are displayed when you hover the mouse cursor over a
toolbar button.
Prerequisites
None.
Procedure
Customizing CES Toolbars on page 74 Modifying Toolbars to Create Custom Sets
Specifying General Toolbar Options on
page 77
Resetting a Toolbar to the Default Grouping
3. Click to enable or disable any of the following checkboxes:
Show Tooltips Displays a descriptive text box when you hover the mouse cursor
over a tooltip.
Cool Look Displays toolbar buttons with a more modern graphical appearance.
Results
Your modifications to these settings are applied.
Related Topics
Resetting a Toolbar to the Default Grouping of Buttons
You can reset a toolbar to display its default listing of buttons, as well as the default order in
which those toolbar buttons are displayed. Doing so is especially useful when you make
changes to a toolbar that are too extensive and you want to start over to capture just the useful
modifications. In some cases, you may have temporarily modified a toolbar and simply want to
reset it to its default display of buttons.
Prerequisites
The toolbar you want to reset must have been customized in some way.
The toolbar must be a default toolbar that you did not create.
Procedure
3. In the listing of toolbars, click the appropriate toolbar, and then click Reset.
Results
The toolbar now displays all of its default buttons, and all of the buttons are in the default order.
Creating New Toolbars on page 76 Resetting a Toolbar to the Default Grouping
Running Scripts
Related Topics
Running Scripts
You can run scripts in CES for the purpose of automating program tasks that you typically
perform manually. Automation is a subset of scripting. When you are interested in creating
custom reports, or software functionality that does not exist, you can create and run scripts that
accomplish your goals. CES does not include default scripts because the scripting needs of each
user can be very unique. You must create these on your own or work with programming-savvy
colleagues to come up with your scripting solutions.
Tip: When running a script that does not account for key presses of OK/Cancel message
boxes, you can set the following user environment variable that chooses OK by default:
VBAE_NO_DIALOGS = 1
To Run a Script
You can run a script in any of the following ways:
To execute a script file, from the CES command box, enter the location and filename of
the script (VBScript, JScript, or .efm script form) you want to run (or use the Open
button to navigate to it), and then click or press Enter.
To enter multiple lines of scripting code:
o In the command box, separate each line with the : character, and then click or
press Enter after the last line of code.
o In the Scripting log window, press Ctrl-Enter after each line, and then run the script
by pressing Enter after the last line of code.
Tip: To run the script again, position the text cursor at the end of the last line, and
then press Enter.
To access the list of scripts you have run in previous CES sessions, click the dropdown
button.
To Run a Command
From the CES command box, using VBScript syntax, enter the automation command you want
to run, and then click or press Enter.
Creating New Toolbars on page 76 Specifying General Toolbar Options on
page 77
Creating or Opening a Script File
Tip: To separate multiple commands or lines of code, use the : character.
Example: To display the Path property of the ActiveProject object in a message box, enter the
following: MsgBox ActiveProject.Path
Example of Running a Script From the Scripting Log Window
In the example below, a short script was entered into the scripting log window. Each code line is
separated by pressing Ctrl-Enter. To run the script, or run it again, the user just presses Enter
after the last line of code.
Figure 2-5. Scripting Log Window Code Example
Creating or Opening a Script File
You can create a new file or open an existing file. The file types you can create and open are
scripting forms (.efm). Unlike a scripting file (e.g. Visual Basic Scripting .vbs file), scripting
forms encapsulate both the graphical and code elements of a scripting dialog box, giving you
the ability to keep tight associations between these script elements and transfer just a single file
when sharing a script with other users.
Note
When modifying CES constraints, you do not need to create or open a file. By default,
when you launch CES from a schematic-capture or PCB layout design tool, the
application is already associated with a CES database. You do not need to specify a file to
modify constraints.
To Create a New Script
From the File menu, click New Script.
To Open an Existing Script
1. From the File menu, click Open Script.
2. From the CES - Open Script Form dialog box, browse to the file you want to open, and
then click OK.
Importing Designs Into CES
Importing Designs Into CES
During the design-import process, you can specify different options that control the creation of
the front-end or back-end CES database. The CES database that is created during this process
depends on whether you launched CES from a schematic capture or PCB layout design system.
Note
The first time you launch CES on a design, this process is run automatically. You do not
need to run this process manually, or repeat it, after your design has been imported
successfully.
Specifying General Options
You can specify the following general design options. Please refer to the table below for a
description of each option.
Specifying Reference Designator Prefixes
For each type of component, specify the reference designators used to identify these parts
within your design. When multiple reference designator prefixes apply, separate each prefix
with a comma. For example, to include both resistors (e.g. R) and resistor packs (e.g. RP), enter
the following in the Resistor field: R, RP
Table 2-8. General Options
Option Purpose
Class hierarchy delimiter
character
Specifies the delimiter character used to denote hierarchy
within your design.
Expedition Job Template Defines the name and location of the Expedition PCB job
template file used with your design.
ePlanner Database File When your design includes existing ePlanner/Expedition
PCB constraints, specifies the name and location of this
database file.
Max number of nets per
elect net
Defines the maximumnumber of physical nets that can be
combined to construct an electrical net.
Power net pin count
threshold
Specifies the minimumnumber of pins that must comprise
a net in order for it to be flagged as a power net.
Use IBIS models for elec
nets
Defines creation of electrical nets based on IBIS model
parameters.
Customizing the Constraint Set
Specifying Power and Ground Nets
For each power or ground net that has been identified, verify the voltage value. To change a
voltage value, click within the Voltage column, and then enter a different value.
When you use CES as standalone application that was not launched from a supported design
tool (e.g. DxDesigner), you can customize the constraint set displayed through the CES
Spreadsheet. In standalone mode, you can modify existing constraints and add new constraints.
Changes you make are stored in a file called user.cns in your WDIR location. Any changes you
make are not visible in CES until your next session.
Note
Changes to the constraint set are visible in all CES sessions, but only modifiable in
standalone CES sessions.
To Change the Constraint Set
1. From the Edit menu, click Constraints Definition.
Alternative: From the CES Spreadsheet, right-click a constraint column, and then click
Constraints Definition. Now that you are in the context of a specific constraint, please
proceed to step 4.
2. From the Constraints Definition dialog box, use the Page dropdown to select the
spreadsheet page for which you want to modify an existing constraint or a new
constraint.
Tip: To differentiate between standard constraints and user-created constraints, you can
use the Filter dropdown to select the constraint types to display.
3. At this point, you can perform any of the following tasks:
To modify an existing constraint, from the Constraint dropdown, select a base
constraint.
To create a constraint, click , type a name for the new constraint, and then click
OK.
4. For the existing constraint or new constraint, you can now specify Header, Title, Data
type, Default value, and other attributes of the constraint. The Data type field controls
whether the constraint has an associated Unit type, Min value, and Max value.
Note: To display the unit type in a constraint heading, append (%U) to the heading
text (e.g. Crosstalk (%U)).
5. When applicable, you can use Min value and Max value to set the acceptable boundaries
for a constraint. When the user enters a constraint value that is outside of this boundary,
CES uses its backlighting mechanism to visually indicate the range breach.
6. When creating or modifying a new constraint, use the Levels selection to specify the
spreadsheet-page levels for which the constraint should be associated.
7. Click the associated check box to make the constraint read only and/or hidden.
8. In the Constraint description text field, enter or modify the description for the constraint.
9. To make more adjustments to constraint set, return to step 2. After you finish changing
the constraint set, click Apply.
To Delete a User-Created Constraint
1. From the Edit menu, click Constraints Definition.
2. From the Constraints Definition dialog box, use the Page dropdown to select the
spreadsheet page for which you want to delete a user-created constraint.
3. Using the Constraint dropdown, select the constraint, and then click .
Creating Custom Spreadsheet Pages
In addition to changing the list of constraints on a preexisting spreadsheet page, you can also
create new spreadsheet pages and populate them with your own selection of constraints and
rows. Each custom spreadsheet page is different from the standard pages in that they do not
have any rows or columns by default. Much like the Noise Rules spreadsheet page, they begin
completely blank. You must add rows to start populating them.
To Create a Custom Spreadsheet Page
1. At the bottom of the CES Spreadsheet, next to the Constraint Templates tab, click .
Result: A new customtab is added to the Navigator, and the list of selectable tabs at the
bottom of the CES Spreadsheet.
2. At this point, you should rename the page. To do so, right-click the name of the page,
and then click Rename. Type a new name, and then press Enter.
3. To customize the listing of rows, you can do any of the following things:
To add a row, from the Navigator, right-click the name of the page, and then click
New Custom Object.
To copy a row, from the CES Spreadsheet, right-click a row, and then click Clone.
To change the name of a row, fromthe CES Spreadsheet, right-click a row, and then
click Rename. Type a new name, and then press Enter.
Adding Custom Menu Selections to the Tools Menu
To delete a row, from the CES Spreadsheet, right-click a row, and then click Delete.
4. To customize the listing of columns, please refer to Customizing the Constraint Set on
page 82.
Sharing Your Constraint Set With Other Users
When working with a team of engineers who need to use the same custom constraint set, you
can share your <WDIR>/user.cns file with other members of the team. To do so, simply place
the file in a public location and then provide instructions for other team members to copy it into
the WDIR directory on their respective machines.
For example, if you are the constraint administrator for a design project or team, you might want
to grant access to specific constraints to just certain members of the team while hiding them
fromthe rest or making themread-only. By default, all CES users have access to all constraints,
so reducing accessiblity to some key constraints can help to ensure constraints integrity, and
especially for large teams. In this example case, a constraint administrator might create a few
user.cns files and then provide the appropriate user.cns file to each team member.
Adding Custom Menu Selections to the Tools
Menu
You can add menu selections to the customize the Tools menu. Doing so makes it easier to
access external programs that you use in conjunction with CES, or as part of your constraint-
driven design flow. Menu selections that you add to CES are appended to the bottom of the
preexisting Tools menu selections. Any ordering changes or deletions that you make can not
include the standard menu selections.
Prerequisites
None.
Procedure
1. From the Tools menu, click Customize.
2. From the Customize dialog box, click Add, and then complete the following fields:
Menu Text The display name you want to associate with the custom menu
selection.
Command The executable file to run when the custom menu selection is clicked.
To specify the command, click the browse button, navigate to the appropriate folder
and filename, and then click Open.
Arguments Optionally, an argument string to append to the command. Your
argument string can also include the following variables:
Customizing Command Shortcut Keys
o {CESDir} CES directory of the active project.
o {ProjectDir} Top-level directory of the active project.
o {ProjectFile} Filename of the .prj for the active project.
Initial Directory Optionally, a directory to use other than the current working
directory. This is useful when the command will generate run-time files that need to
be stored in a different location. To specify an initial directory, click the browse
button, navigate to the appropriate folder, and then click OK.
3. Optionally, you can do any of the following things:
To edit an existing custom menu selection, in the Menu Contents list box, click the
appropriate row, and then modify any of the fields described in step 2 of this
procedure.
To change the order of a custommenu selection, in the Menu Contents list box, click
the appropriate row, and then click Move Up or Move Down.
To delete a custom menu selection, in the Menu Contents list box, click the
appropriate row, and then click Remove.
4. After you finish adding custom menu selections or modifying existing custom menu
selections, click OK.
Results
The bottom of the Tools menu is updated to reflect your changes.
You can customize command shortcut keys to associate key combinations with commands that
do not already have them, change existing key combinations, and assign multiple shortcut
combinations to a single command. For example, when CES does not include what you consider
to be an intuitive shortcut combination for a command, you can remove the existing command,
and then define your own shortcut combination. The alternative is to simply add an additional
shortcut combination that you consider to be more intuitive; in other words, easier to remember.
Prerequisites
To execute and test the accessibility of some CES commands through shortcut
combinations, you must have a design loaded in order to access all functionality.
Procedure
1. From the CES Setup menu, click Shortcuts.
2. From the Customize dialog box, in the list box of Commands, click to select a
command, and then do any of the following things:
To create a new shortcut combination, click New, and then do the following things:
i. When the New Shortcut dialog box appears, key-in the combination you would
like to use. It can consist of Ctrl, Shift, Alt, and then a letter key, number key, or
F# key (e.g Ctrl+Shift+Alt+F8).
ii. After you finish pressing the appropriate shortcut key combination, visually
verify that it is correct, and then click OK.
To delete a shortcut, in the Current shortcuts list box, click a shortcut, and then click
Remove.
3. Optionally, to remove all user-defined shortcuts and reset the list of shortcuts to just the
defaults, click Remove All.
4. After you finish adding, modifying, or deleting shortcut combinations, click OK. In the
event that you made changes that you do not want to keep, click Cancel.
Results
Your additions, removals, and changes to key combinations are now stored. You can now use
them to access CES commands.
Chapter 3
CES Constraint Spreadsheet Usage
This section covers CES Constraint Spreadsheet usage. Some of the topics included are
constraint definition, searching, filtering, and grouping. This section also provides information
about constraint validation, constraint reuse through rule painting, and saving constraint
changes. Please refer to the table of contents for the full listing of topics included in this section.
Defining Constraints With CES Spreadsheets
The CES interface for entry and modification of constraint data is a spreadsheet that is separated
into pages. Each page corresponds to specific types of constraint data. The constraints located
on some spreadsheet pages are further groupable by listing only a pre-defined subset of a
constraint set. For example, while working in the Nets tab of the CES Constraint Spreadsheet,
you can choose to list just Net Properties, Differential Pairs, or Delays and Lengths constraints.
Note
As you work with constraints on each CES Spreadsheet page, you will notice that some
constraints are listed on multiple pages. Changing a constraint value on any page that
includes it results in the change appearing on each page. For example, the Index and Type
constraints appear on both the Trace & Via Properties and Clearances spreadsheet pages.
While entering or modifying the data on each of these pages, you can search for net and
constraint data, filter data, sort data, and validate constraints against actuals that were produced
during routing simulation. Nets assigned to the classes you define here will obey associated
constraints during interactive routing.
Common Tasks
Understanding Constraint Hierarchy and Overrides on page 88
Selecting CES Spreadsheet Pages on page 89
Identifying Spreadsheet Icons on page 90
Resizing Spreadsheet Columns and Rows on page 91
Zooming the Display of Spreadsheet Pages on page 92
Expanding and Collapsing Spreadsheet Rows on page 93
Sorting Constraint Pages on page 93
Deleting Constraint Values on page 94
Understanding Constraint Hierarchy and Overrides
In order to make definition of design constraints as efficient as possible, you can use
hierarchical CES design objects like constraint classes, net classes, and parts/instances. These
give you the ability to group sets of nets or parts and then use same or different constraint values
as needed. For example, by grouping 64 bus nets into the same constraint class, you can quickly
assign a single constraint value to the class (e.g. rising delay) instead of manually assigning the
value to each of the 64 bus nets. When you need to deviate from a constraint class value,
though, you can enter an override value into one or more net rows while maintaining the class
value for all other nets in the class.
In important cases, to help make it clear which constraint values under a hierarchical object
have overrides, CES highlights the background of these cells. In the following illustration, you
can see that although the component row defines the same IBIS Component Name value as the
default for each component instance row, R2 and R4 have overrides that replace the default.
Figure 3-1. Component Model Overrides at the Instance Level
To set the background colors CES uses to highlight constraint overrides, please refer to To Set
Fonts and Colors on page 61.
Organization of CES Constraints
CES constraint data is organized into the following spreadsheet pages:
Trace & Via Properties Board-layer transmission constraints like via assignments,
routing, trace width, and typical impedance.
Clearances Same-layer clearance constraints like trace to trace, pad to trace, via to
plane, resistor to pad, and mask to pad.
Z-Axis Clearances Adjacent-layer clearance constraints like trace to trace, trace to
pad, trace to via, trace to plane, and trace to SMD pad.
Nets This spreadsheet page contains the largest number of constraints, which fall into
the following categories:
o I/O Designer FPGA constraints like I/O standard.
o Net properties General net constraints like analog, bus, net class, number of pins,
and topology type.
o Diff Pair Differential pair constraints like tolerance, convergence distance
tolerance, distance to convergence, and separation distance.
o Overshoot/Ringback Signal reflection constraints like simulation class, static and
dynamic low and high overshoot, high and low ringback, and monotonic edge.
o Simulated Delays Edge-rate delay constraints like simulated delay type, minimum,
maximum, and maximum range.
o Template Net template constraints like name and status.
o Delays and length Length or time of flight delay constraints like type, minimum,
maximum, match, tolerance, and formulas.
Parts Part constraints like part number, quantity, part type, value, IBIS component
name, and technology.
Noise Rules Neighboring net constraints like noise type, constraint class or electrical
net name from and to, parallelism rule, crosstalk max, and auto route usage.
Constraint Templates Superset of constraints that includes many of those from each
CES Spreadsheet page for reuse as intellectual property for other nets and designs.
Selecting CES Spreadsheet Pages
You can select the active spreadsheet page in a variety of ways. In addition, you can choose to
display only a subset of constraints displayed on large spreadsheet pages. For example, you can
temporarily display just Diff Pair constraints on the Nets page. By doing so, you can more easily
focus on the constraints related to differential pair nets.
To Select a CES Spreadsheet Page Using the Tabs
At the bottomof the current spreadsheet, click a spreadsheet tab. In the illustration below, the Z-
Axis Clearances tab is selected.
Figure 3-2. Selected Spreadsheet Page: Z-Axis Clearances
Tip: When you cannot see all spreadsheet tabs, use the arrow buttons to scroll through the tabs.
You can also resize the right edge of the tab listing to increase or decrease the amount of space
used to display these tabs.
To Select a CES Spreadsheet Page Using the Navigator
You can click within the Navigator to select among the different spreadsheet pages that are
available in CES. For example, after clicking Constraint Classes, the CES Spreadsheet Nets
page becomes active.
To Display Only Specific Constraint Types on a Spreadsheet Page
With the Nets, Parts, or Constraint Templates tab active, at the top of the spreadsheet page,
click the Group dropdown, and then select a constraint type. The group listing includes user-
created constraint groups.
Example: To display just net property type constraints of the Nets spreadsheet page, click the
Group dropdown, and then click Net Properties.
To Display All Constraint Types on a Spreadsheet Page
When applicable, from the Group dropdown, click All.
Identifying Spreadsheet Icons
As you work with the CES Spreadsheet, you will notice that each row includes an icon. Each
icon indicates a different type of design object. Icons are provided to make design-object
identification clear and efficient. For example, you can easily distinguish between electrical and
physical nets based on the icon beside a row on the Nets page of the spreadsheet. Please use the
following table to determine the type of design object that is represented by each icon.
Table 3-1. Design Object and Spreadsheet Icon Correlation
Design Object Spreadsheet Icon
Board layer
Clearance rule
Component
Component instance
Constraint class
Constraint template
Differential pair
Electrical net
From-to
Net class
Physical net
Pin
Note
Electrical nets that include two or more physical nets are indicated as such on the Nets
page of the CES Spreadsheet. A ^^^ suffix is added to the end of the net name as it
appears in the first column (Constraint Class/Net/*).
Locking of Constraints
When working in any concurrent design environment, the CES Spreadsheet automatically locks
constraint values or objects that are being changed by another user in a separate instance of
CES. After the user finishes making their change, the lock is removed, and the value is once
again editable by other users. For example, two schematic designers are modifying constraints
from within CES sessions launched from DxDesigner. Because both users are working on the
same constraint database, CES displays lock icons ( ) in the other users environment as each
applicable constraint or object is modified.
A constraint or object lock is always removed when any of the following things occurs:
The user who initiated the change finishes their modification(s).
All clients are disconnected.
The server is down.
To Determine Which User Has a Constraint Locked
Hover your mouse cursor over the locked constraint. The tooltip that is displayed shows the user
account that currently has the constraint locked for editing.
Resizing Spreadsheet Columns and Rows
As you work with CES constraint data, you may find it useful to resize specific columns or
rows. For example, by reducing the size of a column, you can provide more display room for
other columns located on the same spreadsheet page. On the other hand, by increasing the size
of a column, you can provide more display room for the content in that column.
Pin pair
Rule-area scheme
Z-axis clearance rule
Table 3-1. Design Object and Spreadsheet Icon Correlation (cont.)
Design Object Spreadsheet Icon
To Resize Spreadsheet Columns
1. In the columns heading of a spreadsheet, hover your mouse over the vertical separation
between columns until the mouse icon changes to the resize icon. This is depicted in the
following illustration.
Figure 3-3. Preparing to Resize Constraint/Class/Net/* Column
2. Click-hold and then drag right or left to increase or reduce the size of the column.
3. After the column has been resized appropriately, release the mouse button.
To Reset Columns to Their Default Widths
From the View menu, click Reset Column Widths.
To Resize Spreadsheet Rows
1. In the leftmost cell of spreadsheet row, hover your mouse over the horizontal separation
between rows until the mouse icon changes to the resize icon.
2. Click-hold and then drag up or down to increase or reduce the size of the row.
3. After the row has been resized appropriately, release the mouse button.
To Reset Rows to Their Default Heights
From the View menu, click Reset Row Heights.
Zooming the Display of Spreadsheet Pages
You can increase and decrease the magnification level of CES Spreadsheet pages. Because each
spreadsheet page stores its own zoom level, you can customize the magnification level of
specific pages for your unique display purposes.
Tip: To quickly set the same magnification level for all CES Spreadsheet pages, use the
Setup > Settings menu selection. Using the Initial Zoom Level option, you can globally
control the initial spreadsheet magnification level.
To Zoom the Display of the Active CES Spreadsheet Page
Do one of the following:
To increase magnification, press F7.
To decrease magnification, press F8.
To set magnification to 100%, press F4.
Expanding and Collapsing Spreadsheet Rows
You can expand and collapse the available rows on a CES Spreadsheet page. You can expand or
collapse just the selected rows, all rows, or a single row.
To Expand or Collapse a Single Spreadsheet Row
Click the + or - symbol to the left of the row.
To Expand Multiple Spreadsheet Rows
1. When you want to expand specific rows, use Ctrl-click to select each row that is
preceded with a + symbol.
2. From the View menu, to expand selected rows, click Expand, and then click Selected.
To expand all rows, click Expand, and then click All.
To Collapse Multiple Spreadsheet Rows
1. When you want to collapse specific rows, use Ctrl-click to select each row that is
preceded with a - symbol.
2. Fromthe Viewmenu, to collapse selected rows, click Collapse, and then click Selected.
To collapse all rows, click Collapse, and then click All.
Sorting Constraint Pages
You can sort nets/objects listed on a CES Spreadsheet page in both ascending and descending
order. Because this function is based on spreadsheet context, a sort will include all/most child
rows, or just the parent rows. For example, sorting from the Clearances page does not affect the
order of board layers ( ).
To Sort Constraint Pages
With CES Spreadsheet page that you want to sort as the active page, perform one of the
following actions:
To sort in ascending order, from the Sort toolbar, click . Or, right-click within the
spreadsheet, click Sort, and then click Ascending.
To sort in descending order, from the Sort toolbar, click . Or, right-click within the
spreadsheet, click Sort, and then click Descending.
Searching for Constraints
Deleting Constraint Values
When you want to delete one or more constraint values, CES gives you the ability to do so
through both the keyboard and the mouse. Please refer to the following procedure for deletion
of constraint values.
To Delete Constraint Values
1. From the CES Spreadsheet, click a constraint cell to select the value for deletion.
Tip: To select multiple constraint values, use Ctrl-click and Shift-click.
2. Press the Delete key, or from the Main toolbar, click .
Related Topics
Quick Reference - CES Constraint Spreadsheet on page 27
CES Constraint Reference on page 237
Copying and Pasting Constraint Values Between
Separate Invocations of CES
When you have multiple invocations of CES loaded at the same time, you can copy and paste
spreadsheet values displayed in one invocation to the same spreadsheet of one or more other
invocations. Because CES does not restrict the cells between which you can copy and paste, it is
important to make sure that you select identical cells of the appropriate spreadsheet page.
You can use the copy and paste functionality on all CES Spreadsheet pages. It is important to
note that the functionality is not available for use with tables and cells of dialog boxes.
You can search for data within CES Spreadsheet pages to locate specific nets or select multiple
nets to perform operations on groups of nets. By doing so, you can quickly find or select
specific nets within large, complex design structures. You can also search spreadsheets for
constraint data.
When searching for specific nets, you can step through the list of all nets based upon the search
criteria you provide. When selecting multiple nets, you can filter the display of CES data based
upon a net-name or constraint-value criterion.
Tip: To quickly search for the first occurrence of any text string, from the Find toolbar,
enter the text string into the text box, and then click the button to the left. To find the next
occurrence, click the search button again.
To Search for Spreadsheet Data
1. From the Edit menu, click Find.
Alternative: From the Find toolbar, click .
Note: When you want to both find and replace spreadsheet data, please refer to To
Search for and Replace Spreadsheet Data on page 96.
2. From the Find and Replace dialog box Find what field, enter the text you want to find.
Example: To find and step through all nets of the form /N$2050 - /N$2059, use
/N$205? as your search string. To find and step through all nets that begin with /N$2,
enter /N$2*. Please note that this is not a regular-expression search example.
3. Specify the direction in which you want to search by selecting Forward or Backward.
4. To view additional search preferences, click More, and then use the following options:
To search a page other than the current page, click the Page dropdown, and then
click to specify your search scope.
To search sequentially by rows or columns, click the Search dropdown, and then
click to specify the direction.
To search constraint values, or constraint comments, click the Look In dropdown,
and then click to specify the appropriate criterion.
To match the exact capitalization or case sensitivity of the search string, click to
enable Match Case.
To find only full matches and not partial ones (e.g. you do not want searches for
100 to find 1000 and 10000), click to enable Match entire cell.
To search using regular expressions, click to enable Use regular expressions, but
please keep the following in mind:
o Standard wildcard characters (e.g. * and ?) behave much differently in that they
include matching--or not--to the preceding character. For example, a regular
expression search for n*t would match at, nt, net, about, and many
other words that begin with any character and end with t. Conversely, a regular
expression search for n?t would only match at, nt and net of the results
of the above asterisk example.
o There are additional wildcard characters that you can use.
o You can search using ranges of characters.
o For more information about using regular expressions properly, please refer to
the wealth of information available on this subject that you can find on the
internet or in dedicated textbooks.
To enable searching of spreadsheet rows that are currently not expanded, click to
enable Drill-down searching
5. After you finish configuring your search, click Find Next or Find All.
When you search with Find Next, the first relevant cell is highlighted. To find the
next cell that matches your criteria, click Find Next again.
When you search with Find All, CES augments the dialog box to show a table of all
matching cells. You can cross probe between the table of search results and the
spreadsheet by clicking a cell in the results table.
To Search for and Replace Spreadsheet Data
1. From the Edit menu, click Replace.
Alternative: From the Find toolbar, click .
2. From the Find and Replace dialog box Find what field, enter the text you want to find.
3. In the Replace with box, enter the text you want to use as the replacement string.
4. Specify the direction in which you want to search by selecting Forward or Backward.
5. To view additional search preferences, click More, and then use the following options:
To search a page other than the current page, click the Page dropdown, and then
click to specify your search scope.
To search sequentially by rows or columns, click the Search dropdown, and then
click to specify the direction.
To match the exact capitalization or case sensitivity of the search string, click to
enable Match Case.
To find only full matches and not partial ones (e.g. you do not want searches for
100 to find 1000 and 10000), click to enable Match entire cell.
To find nets based upon wildcard searches (* or ?), click to enable Use regular
expressions.
Example: To find and step through all nets of the form /N$2050 - /N$2059, use
/N$205? as your search string. To find and step through all nets that begin with
/N$2, enter /N$2*.
To enable searching of spreadsheet rows that are currently not expanded, click to
enable Drill-down searching
6. After you finish configuring your search, click Replace or Replace All.
When you search with Replace, the first relevant cell contents are replaced. To
replace the next cell that matches your criteria, click Replace again.
Filtering Spreadsheet Data
When you search with Replace All, all matching cells are replaced.
Unlike search, when you filter a spreadsheet page the display of data rows is restricted to those
that match the string criteria. After you perform an initial filter, you can further restrict the
display of data rows by cumulatively filtering the remaining data rows. After you finish
working with a subset of nets, you can reset the spreadsheet page to display all data rows.
Filter is useful when you want to focus on a specific group of data rows without worrying about
modifying constraint data on rows that do not apply to a specific subset. For example, by
filtering data rows on the Nets spreadsheet page, you can display only those rows that
correspond to just the nets that comprise a data bus. With this view, it is easy to make sure that
your constraint modifications are restricted to just those bus nets.
Note
CES filters just spreadsheet rows that are expanded. To filter all rows of a spreadsheet
page, from the Filters menu, click to enable Drill-down Filtering.
Other Common Tasks
Filtering the CES Spreadsheet by Row Type on page 99
To Filter Spreadsheet Data
1. From the Filters menu, click Enabled.
Note: Make sure that Filter mode is on. When it is, the CES Spreadsheet is augmented to
include an additional row at the top for entering the filter string. Also, the Filters >
Enabled menu item includes a check mark.
2. In the column for which you want to filter spreadsheet data, click the dropdown in the
filter cell, and then perform one of the following tasks:
To use a default filter, select from among Sort Ascending, Sort Descending, (All),
and (All Non Empty).
To create a custom filter, click (Custom...), and then perform the following steps:
i. Fromthe CustomAutofilter dialog box, click the dropdown in the box to the left,
and then click to specify how the custom filter will apply to the filter string you
use.
ii. In the box to the right, enter the filter string you want to use.
iii. For additional filtering options, click the More button, and then specify any of
the following options:
- To match case sensitivity, click to enable Match case.
- To toggle cumulative mode filtering, click the appropriate check box.
- To toggle filtering of non-expanded spreadsheet rows, click Drill-down
filtering.
- To instead use a regular expression, click to enable the appropriate check box,
and then enter the regular expression you want to use.
iv. After you finishing configuring your filter, click Apply.
3. To reduce the display of spreadsheet data (i.e. rows) by adding another column criterion,
return to step 2. You can also further filter a column by which you have already filtered.
For example, after filtering the Nets spreadsheet Constraint Class/Net/* column to
display a subset of rows based upon net name, you can cumulatively filter the subset by
net name again.
Rule: You must enable cumulative mode before you can filter using additional criteria.
To Enable Cumulative Mode
From the Filters menu, click Cumulative Mode.
Result: The Cumulative Mode menu item includes a check mark.
To Reset the View of Data Rows to All
After you finish working with a subset of spreadsheet data rows, from the Filters menu, click
Reset.
Example of Filtering the Nets Page to Display Only Electrical Nets (^^^)
In this example, you are interested in displaying only true electrical nets on the CES
Spreadsheet Nets page to focus your current constraint definition task. Because net names can
often times be quite long, and the true electrical net identifier is appended to the end of a net
name (i.e. ^^^), filtering to display just these nets ensures that you are working on only
electrical nets without having to expand the column width of the Constraint Class/Net/* column
to verify the existence of the electrical net identifier.
To Filter and Display Only Electrical Nets
1. With the CES Spreadsheet Nets page active, expand the constraint class that you want to
work in.
2. With filtering enabled, in the filter row of the Constraint Class/Net/* column, click the
filtering dropdown, and then click (Custom...).
3. In the Custom Autofilter dialog box, set the filter to equals, and then in the box to the
right, enter the following: *^^^
Resetting the Spreadsheet to its Default View
4. After you finish setting the custom filter, click Apply.
Result: The spreadsheet is reduced to display just electrical nets that are part of the (All)
constraint class.
Filtering the CES Spreadsheet by Row Type
When working on CES spreadsheet pages, you can specify the row types that CES displays. For
example, when the active spreadsheet page is Nets, you can choose to display a subset of data
rows that includes only from-tos, pin pairs, and electrical nets. It is important to note that each
spreadsheet page has one more default row types are always enabled (e.g. the constraint classes
row of the Nets page is always displayed).
To Filter the Spreadsheet by Row Type
With a specific spreadsheet page active, from the Filters menu, click Levels, and then click to
choose the row types you want to display.
Alternatives:
Fromthe Filter toolbar, click a button to toggle the display of a specific row type. Those
that are active have an outline box around them.
From the Filter toolbar, click . From the Filter Levels dialog box, click to toggle the
levels that you want to display, and then click Apply.
Example: To filter the CES Spreadsheet Parts page to include part pin rows, with the Parts
page active, from the Filter menu, click Levels, and then click to turn on Part Pins.
To Displays All Row Types
From the Filters menu, click Levels, and then click All.
To Display No Row Types
From the Filters menu, click Levels, and then click None.
Resetting the Spreadsheet to its Default View
After you work with the CES Spreadsheet for one or more sessions, you may find it necessary to
return it to its default view. When you do so, you can quickly reset the appearance of the
following elements:
View of available spreadsheet tabs
Level toggling
Active constraint group
Creating Constraint Groups
Removal of filters and filtering
Row expansion
To Reset the Spreadsheet to its Default Appearance
From the Group toolbar, click .
You can create groups that include a subset of all constraints displayed on either the Nets, Parts,
or Constraint Templates CES Spreadsheet pages. For example, when your constraint
modifications are limited to a common subset of Nets spreadsheet constraints, you can create a
group that includes just those constraints. Doing so gives you the ability to increase the
efficiency with which you modify constraints. When managing other co-workers, creating
unique groups can help to ensure that their focus remains on the appropriate constraint subsets.
Note
Because constraint groups are a subset of all constraints located on a spreadsheet page,
modifying a spreadsheet constraint while in a group view results in the change appearing
in all views.
In the following illustration, a user has created two constraint groups that serve as custom
subsets of the CES Spreadsheet Nets page.
Figure 3-4. Constraint Groups Example
The My Delays Group is a subset containing all delay constraints, both simulated and time of
flight. The other group, My Actuals Group, contains all actual values that are available fromthe
Nets page of the CES Spreadsheet.
To Create a Constraint Group
1. From the CES Spreadsheet Nets, Parts, or Constraint Templates page, click the
Group pulldown, and then click Edit User Groups.
2. From the Edit Constraint Groups dialog box, click .
3. Fromthe Create New Constraint Group dialog box, enter a name for the group, and then
click OK.
4. From the All constraints list, select the constraints that you want to appear in the group
by doing any of the following:
To add one or more constraints, use click or Ctrl-click, and then click .
To add all constraints, click .
5. After you finish selecting constraints and the Constraints assigned to group list contains
the appropriate constraint subset, click OK or Apply.
To Modify a Constraint Group
2. From the Edit Constraint Groups dialog box, click the Select constraint group
dropdown, and then click the constraint group you want to modify.
3. From the Constraints assigned to group list, perform any of the following tasks:
To remove one or more constraints, use click or Ctrl-click, and then click .
To remove all constraints, click .
To add constraints, refer to step 4 of the above procedure.
To move one or more constraints up or down in the list order, use click or Ctrl-click,
and then click or .
To move one or more constraints to the top or bottom of the list, use click or Ctrl-
click, and then click or .
Tip: When moving constraints, it can be helpful to keep constraints and their actuals
together.
4. After you finish modifying a constraint group, click OK or Apply.
To Delete One or More Constraint Groups
2. From the Edit Constraint Groups dialog box, perform any of the following tasks:
Working Concurrently With Other Users
To delete one constraint group, click the Select constraint group dropdown, click the
constraint group you want to delete, and then click .
To delete all constraint groups, click .
To Restore the Contents of a Default Group
2. From the Edit Constraint Groups dialog box, click the Select constraint group
dropdown, click the default group you want to restore (e.g. Delays and Lengths), and
then click .
Working Concurrently With Other Users
When multiple users are working on the same front-end or back-end CES database, your CES
session can be updated in real time to highlight the changes of other users. You do so by
enabling indication of remotely modified cells. This causes CES to highlight the background
color of cells that change in any concurrent sessions.
Another way that CES helps ensure effective concurrent design is by temporarily locking a
constraint or object when it is being modified in a parallel session. For more information, please
refer to Locking of Constraints on page 91.
To Show Indication of Remotely Changed Constraints
From the File toolbar, click to enable highlighting.
To Refresh the Display of Remote Changes
From the File toolbar, click to refresh the display.
You can also change the background color CES uses to indicate remote modifications. For more
information, please refer to Setting Up CES on page 56.
Adding Comments to Your Constraint Changes
To help both yourself remember why you made certain changes and also make it clear to other
users working on the same constraint, you can add comments to individual cells on any page of
the CES Spreadsheet. Doing so is especially useful when you want to help ensure that another
user does not change a constraint value that is important to your individual designer goals.
To Add a Comment to a Cell
1. From the CES Spreadsheet, right-click a cell, and then click Insert Comment.
Viewing Constraint Reference Information and Cell Properties
Alternative: From the Comment toolbar, click .
2. From the Comment dialog box, in the text field, enter your comment.
3. Click Apply or Close.
Result: The cell is updated to include a red marker in its upper-right corner to indicate
that a comment has been added to it.
To Edit a Comment
1. From the CES Spreadsheet, right-click a cell that includes a comment, and then click
Edit Comment.
2. From the Comment dialog box, in the text field, modify the comment.
3. Click Apply or Close.
To Delete a Comment
From the CES Spreadsheet, right-click a cell that includes a comment, and then click Delete
Comment.
To View Comments
You can view your comments and those of all other users in the following ways:
To see a single comment, hover the mouse cursor over a cell that includes a comment.
To cycle fromone comment to the next, fromthe Comment toolbar, click (next) or
(previous).
To generate a report that lists all comments, from the Output menu, click Report
Comments.
Viewing Constraint Reference Information and
Cell Properties
The CES Users Manual includes a full constraint reference. You can access it directly fromthe
Constraint Spreadsheet, and from within the table of contents (appendix chapter A). A quick-
reference version of this reference chapter is also available. When using the quick reference, if
you need more information, click a constraint name to go to its CES Constraint Reference entry,
which usually includes a graphic to help you understand its purpose within your design. In the
illustration below, the CES Constraint Reference graphic for the differential pair constraint
Convergence Distance Tolerance is shown.
Viewing Constraint Reference Information and Cell Properties
Figure 3-5. CES Constraint Reference Example Illustration
You can also open the topic for a specific constraint while working with the CES Spreadsheet.
To do so, please refer to the appropriate procedure below. For the purpose of automation, you
can also show programmatic information like a constraints internal name and minimum and
maximum boundary values.
To Open a Constraint Topic From the CES Spreadsheet
From the Trace & Via Properties, Clearances, Z-Axis Clearances, Nets, Parts, or Noise Rules
pages, right-click a constraint cell, and then click Constraint Help.
Viewing Cell Properties
While you are working in the CES Spreadsheet, you can view all properties that are associated
with a constraint cell. This is unlike the constraint reference in that all descriptive and
programmatic information is displayed, and in a modeless dialog box from within CES. As you
activate different constraint cells, the Properties browser is updated to show the appropriate cell
information.
Procedure
1. From any page of the CES Spreadsheet, right-click a cell, and then click Properties.
Alternative: From the View menu, click to enable Properties.
2. From the Properties browser, you can now view all available cell properties
3. For properties that do not have a default image associated with them, you can optionally
add one from your available library of images, or remove one that you associated
previously. Please refer to the following short procedures:
To associate an image or change the associated image, in the Image row, click
Browse, and then from the Open File dialog box, browse to the location and
filename of an image file, and then click OK.
To remove an image or disassociate it, in the Image row, below the Browse button,
click Reset.
Related Topics
Viewing Design Statistics
CES Constraint Reference on page 237
Viewing Design Statistics
You can generate a detailed report of design statistics that includes object, connectivity, and
constraint information. It includes totals for each data point (e.g. total constraints) and top-level
information like snapshot, block, and EE software installation.
To View Statistics
1. From the Output menu, click Design Statistics.
2. To view the report that was created, click Yes.
Checking Constraints and Synchronization
You can check constraints to verify the data integrity of your local CES database. This is
especially useful when starting with a migrated design. Constraints checking provides
information and errors for multiple aspects of design object relation and net assignment. You
can also check synchronization between your CES database and that of the complimentary
design systems, front-end or back-end, respectively.
To Check Constraints Synchronization Between the Front-End and Back-
End
1. From the Output menu, click Check Constraints Synchronization.
2. To view the report that was created, click Yes.
In the event that synchronization checking fails, please ensure that you are properly connected
to appropriate client systems. You can also view the report for more information.
To Check Constraints
1. From the Tools menu, click CES Diagnostics.
2. To viewthe report that was created please refer to the Output window, CES Diagnostics
tab.
Result: The report shows the results of many diagnostics tests. Each test indicates
whether the CES data has passed or failed. In the event that a test has failed, and the
error is automatically fixable by CES, the report will showa link at the bottomthat gives
you the ability automatically fix all errors that fall into this category.
Optional: You can cross probe fromthe report to problematic design objects by clicking
a link on any available error rows.
Correcting CES Diagnostics Errors
After you check constraints integrity, the status bar of CES will display one of the following
types of exclamation points when your CES database has integrity problems:
Red exclamation point Please contact customer support to get help with fixing these
problems. You will need their assistance.
Yellow exclamation point Please attempt to fix these problems yourself by using CES
documentation to make changes based on the reported errors.
When your CES database does not have any integrity problems, the status bar does not display
an indicator. It only displays an indicator in the event that there is problematic data. It is
important to understand that CES will display some errors that are not fixable through CES.
Instead, you would have to do so through your schematic capture program, or another piece of
software. In these cases, the error report tries to make it clear that the error must be fixed outside
of CES.
To Fix All Automatically Fixable Errors
In the event that you have errors that can be fixed automatically by CES, you can click a link at
the bottom of error report to do so.
Note
After you have CES fix errors, it will reload when necessary. This is to ensure that CES
shows the correct constraint data based on changes that occurred during the process of
making automatic fixes.
To Fix Errors That Must be Fixed Manually
In the event that you have CES errors that can only be fixed manually in CES, you should use
CES documentation to make the appropriate fixes. In some cases, the error will provide a link to
the exact documentation that you must use to fix the error.
Listing of CES Diagnostics Tests
Each of the diagnostics tests that CES performs is described in the table below. This
information is in the tooltip that CES displays when you hover the mouse over a specific test in
the report.
Table 3-2. CES Diagnostics Tests
Test Purpose
CES database initialization Checks if CES database is correctly initialized.
Constraint class name
unique
Checks if constraint class name is unique on given level of
hierarchy.
Clearance rule in all
schemes
Checks if clearance rule exists in all schemes.
Layer numbering Checks if layers have continuous numbers starting from 1.
Layer in all z-axis clearance
rules
Checks if layer exists in all z-axis clearance rules.
Victims and aggressors
valid
Checks if victims and aggressors in noise rules exist.
Component valid Checks if all components are valid in terms of references
to pins.
Pin in net and component Checks if pin belonging to net also belongs to component.
Pin sets consistency Checks if pins in pin sets belong to physical net.
Physical net unique Checks if physical net name is unique.
Pin reference to net valid Checks if pin has a proper reference to physical net.
Electrical net unique Checks if electrical net name is unique.
Electrical net consistency Checks if all electrical nets contain correct physical nets.
Analog nets consistency Checks if each analog electrical net consists of only one
physical net.
All used constraint classes
valid
Checks if all constraint classes used by electrical nets and
differential pairs exist in the design.
All used net classes valid Checks if all net classes used by electrical nets and
differential pairs exist in the design.
Differential pair with two
electrical nets
Checks if all differential pairs have two existing and
different electrical nets.
Electrical nets belonging to
differential pair assigned to
the same net class
Checks if electrical nets belonging to differential pair have
the same net class.
Unique pin pairs in
electrical net
Checks if pin pairs in electrical net are unique.
Connection pin pairs in
electrical net
Checks if valid connection pin pairs exist in electrical nets
that contain multiple physical nets.
Power net topology Checks if power net has the proper topology.
Unique fromtos in physical
net
Checks if all fromtos in physical net are unique.
Table 3-2. CES Diagnostics Tests (cont.)
Test Purpose
Validating Constraints Against PCB Actuals
You can validate CES constraint data against actual PCB data to determine whether specific
constraint values need to be modified to better promote signal integrity and routing
requirements. Actuals displayed in CES are provided through one of two mechanisms:
AutoActive Calculates all actuals except for simulation actuals, which are calculated
by ICX Pro Verify.
ICX Pro Verify Calculates simulation actuals (e.g. Crosstalk Sim Actual, Simulated
Delay Actual Range). Simulation actuals usually include a button in the actual field.
Note
The CES actuals menu selections referenced in this section are only available in CES
sessions launched from a back-end design system (i.e. PCB layout application).
Common Tasks
Updating Actuals Displayed in CES on page 110
Clearing Actuals From the CES Spreadsheet on page 110
Highlighting Constraint Differences on page 110
Sharing PCB Actuals With Front-End CES Sessions on page 111
Fromto in only one net Checks if pin referenced by fromto belongs to the same
physical net as the fromto.
Constraints consistency Checks consistency of constraints.
Default objects Checks if standard and default objects exist for schemes,
clearance rules and net classes.
Mapping of schematic and
physical nets
Checks if all schematic nets and physical nets are mapped
correctly.
Reference designator vs.
component name
Checks if attribute 'Ref Designator' is the same as CES
component name.
Via span valid Checks if the via span is valid.
Unique virtual pin names
Checks if virtual pin names are unique in the design.
Schemes in all class to class
clearance rules
Checks if all schemes exist for class to class clearance
rules.
Unique template names
Checks if template names are unique in the design.
Table 3-2. CES Diagnostics Tests (cont.)
Test Purpose
To Validate Constraints
From the Data menu, click Connect to Board Station RE/Expedition.
Note: Typically, when you launch CES it is automatically connected to Board Station XE/RE or
Expedition PCB. This menu option is not present when you are already connected.
When constraint validation is available, you can easily see which constraints are resulting in
actuals that are approaching or exceeding a constraint threshold, or moving out of a minimum
and maximum constraint range. To make such distinctions clear, CES backlights actual
spreadsheet fields with one of two colors, which respectively indicate whether an actual is out
of range, or close to being out of range. During the process of setting up CES, you can specify
the backlight colors that CES uses.
Figure 3-6. CES Color-Codes Actuals to Indicate Violations
Rule: In order to perform this type of validation, you must update routing results from a
supported router (e.g. Board Station XE or Expedition PCB).
Viewing All Constraint Violations
Aside fromlocating constraint violations within specific pages of the CES Spreadsheet, you can
quickly generate a list of all actuals that are producing constraint violations. The Constraint
Violations dialog box is modeless, so you can conveniently keep it on screen for prolonged
periods of time. To update its display, click Refresh.
To View All Constraint Violations
1. From the Data menu, click Constraint Violations.
2. From the list of Constraint cautions and violations, refer to the Constraint and Object
columns to determine problematic constraints.
3. Optionally, do any of the following:
To display just violations, click to enable the Show only violations check box.
To hide any revised constraint rows, click to enable the Show only unrevised check
box.
To mark a constraint as revised, click to enable its Revised check box.
Alternative: To do this fromthe CES Spreadsheet, right-click a constraint cell, click
Mark As, and then click Revised.
To cross probe to the CES Spreadsheet rowto which a constraint caution or violation
refers, click a list row.
Alternative: To move up or down one row in the violations list while cross probing,
click or .
Updating Actuals Displayed in CES
When engineering efforts are being performed simultaneously in both CES and the router to
which CES is connected, you may want to periodically update/refresh the actuals that are in
CES to reflect changes to actuals produced by the router.
To Update All Net Actuals
From the Data menu, click Actuals, and then click Update All.
To Update Selected Net Actuals
1. On a CES Spreadsheet page, click, Ctrl-click, or Shift-click to select one or more nets.
Rule: In order to update net actuals, cross probing must be enabled. To do so, from the
Setup menu, click to enabling Cross Probing.
2. From the Data menu, click Actuals, and then click Update Selected.
Clearing Actuals From the CES Spreadsheet
In some cases, you may want to clear the actual values displayed on one or more CES
Spreadsheet pages. Please use the following procedures to clear actual data from the
spreadsheet.
To Clear Actuals From All Spreadsheet Pages
From the Data menu, click Actuals, and then click Clear All Pages.
To Clear Actuals From the Current Spreadsheet Page
From the Data menu, click Actuals, and then click Clear This Page.
Highlighting Constraint Differences
By having CES highlight all constraint differences, you can more-easily see which constraint
values are exceeded by actual values. When in this mode of operation, CES also highlights
hierarchical constraint differences. For example, a physical net comprised of two electrical nets
has three separate constraint values for # Vias Max. Based on net hierarchy, the sum of the two
electrical net values equals the physical net value. This is an accepted hierarchical constraint
difference that is easier to verify in this mode. In the example illustration below, each electrical
net has a # Vias Max value of 2. The higher-level physical net value for # Vias Max is 4, which
is the correct value based on constraint hierarchy (i.e. sum of the two electrical net # Vias Max
values).
Figure 3-7. Hierarchical Constraint Differences
To Highlight Constraint Differences
From the View menu, click Update Differences.
To Clear Highlighted Differences
From the View menu, click Clear Differences.
Sharing PCB Actuals With Front-End CES Sessions
Although PCB actuals are generated as part of back-end constraint calculations, you can also
share those values with front-end CES sessions. This is especially useful when the logic
engineers on your design teamare interested in the actual values that are being generated on the
back end. This is also useful for promoting general cohesion between design-team members.
The team member who performs which of the actions in the below procedure will vary
depending on your design process. For a small design team, a single person might perform the
above procedure in its entirety. For large design teams working on very complex designs, a
schematic designer would typically make a call or send an email to request that a PCB layout
engineer perform step 1 to export actuals. An alternative to that approach would be to adopt a
process where actuals are exported at multiple, scheduled times each day.
Prerequisites
Actuals must have been generated by the back-end design systems and displayed in
CES. Fore more information, please refer to Updating Actuals Displayed in CES on
page 110
Updating Electrical Net Data and Results
Procedure
1. In a back-end invocation of CES, from the File menu, click Export, and then click
Actuals.
2. From the Output log window, verify that the actual values have been successfully
exported.
3. In a front-end invocation of CES, from the Data menu, click Actuals, and then click
Import Layout Actuals. To include thermal values, click Import Thermal Actuals as
a second selection.
Results
Actual values are displayed in the front-end invocation of CES in the appropriate actual cells of
CES Spreadsheet.
Updating Electrical Net Data and Results
After you assign IBIS models to parts, electrical nets are automatically updated to include
changes based on the technology information in your IBIS models. When a new IBIS model
requires two or more existing electrical nets to be joined, CES resolves existing constraint
values.
When you are using ICX Pro Verify as part of your constraint-driven design flow, you can
update CES to ensure that it includes the most recent simulation actuals produced by ICX Pro
Verify. Simulation actuals include simulated delay constraints and overshoot/ringback
constraints (e.g. Simulated Delay Max Range, Dynamic High Overshoot Max).
Note
In order to use these features, you must have an Electrical CES license.
To Update ICX Pro Verify Simulation Results
From the Data menu, click Update, and then click Simulation Results.
Resolving Existing Constraint Values
When two or more existing electrical nets are joined into a larger electrical net due to new IBIS
model assignments, CES resolves the unique constraint values in each constituent net based on
the following rules:
The minimum Simulated Delay Min constraint value is used; the maximum Simulated
Delay Max constraint value is applied.
Painting Rules to Reuse Constraints
The minimum Ringback Low Max constraint value is used; the maximum Ringback
High Max constraint value is applied.
The minimum Static Low Overshoot Max constraint value is used; the maximum Static
High Overshoot Max constraint value is applied.
Dynamic Low Overshoot Max and Dynamic High Overshoot Max constraint values are
removed from the new electrical net.
You can quickly copy all constraint values that you define in a spreadsheet row into the rows of
other design objects that will benefit from these values. When painting rules to copy constraint
values, it is important to remember that the design object from which you copy must be the
same as the design object to which you copy.
For example, when reusing the constraint values of a specific net row, make sure that you apply
them to another net row. It is the same type of design object.
To Copy Constraint Values of One Spreadsheet Row to Another Row
1. From the CES Spreadsheet, click a scheme, net class, constraint class, layer, or net row,
and then from the Main toolbar, click .
2. Click the spreadsheet row for which you want to apply the copied constraint values.
3. Continue clicking additional rows to paint these rules where appropriate.
4. To turn off the Rule Painter, from the Main toolbar, click .
Example of Copying Board Layer Constraint Values to Another Board Layer
1. Fromthe CES Spreadsheet Trace &Via Properties page, expand a scheme, a net class,
and then click the layer that holds the constraint values you want to duplicate.
2. From the Main toolbar, click .
3. From the CES Spreadsheet, click the row of the layer to which you want to apply the
duplicate constraint values.
4. To apply these values to another layer, click it. When you finish, click to disable rule
painting.
Rolling Back and Undoing Constraint Changes
You can revert constraint changes made at any time during your current CES session. This
includes all commands for which undo/redo is supported. For example, modifying constraint
Rolling Back and Undoing Constraint Changes
classes and net classes, adding clearance rules, and creating differential pairs. For a full listing
of supported actions, please refer to the table below.
Note
When rolling back constraint changes made in CES, the forward and back annotation
indicator lights for your design flow do not reflect these undo actions. For example, after
you make a single change in back-end CES and then rollback that change, your back-end
system will still indicate that you need to perform back annotation.
To Roll Back All Constraint Changes
1. From the File menu, click Rollback Changes.
2. From the Rollback Changes dialog box, click Rollback.
Note: The Status column displays Pending, In Progress, Conflict, or Restored
for each row. Each entry starts out as pending. When you successfully roll back a
change, the field displays restored. For undo actions that take longer to process you
will see in progress displayed before it is moved to a resolved state. When a change
cannot be undone due to change conflicts, the Status field indicates this condition.
In addition to rolling back all changes, CES also supports an enhanced interface for undoing or
redoing multiple changes, beginning with the most recent undo or redo action. For example,
after making 3 consecutive constraint changes, you can quickly use the standard CES GUI to
undo all 3 changes without pressing Ctrl-Z multiple times. This approach also gives you a visual
indication of the most recent changes that can be undone.
When undoing or redoing changes, all actions following the selected action are also reverted or
restored. For example, when you create 3 net classes, beginning with Net Class A and ending
with Net Class C, undoing the creation of Net Class B results in the deletion of Net Class A as
well.
To Undo One or More Changes
1. From the File toolbar, next to , click the dropdown button.
2. In the list of changes you can undo, hover over one or more changes, and then click.
To Redo One or More Changes
1. From the File toolbar, next to , click the dropdown button.
2. In the list of changes you can redo, hover over one or more changes, and then click.
Saving Constraint Changes
Supported Undo/Redo Actions
You can roll back, undo, and redo the following CES changes.,
After you make constraint changes through the CES Spreadsheet and other constraint-entry
mechanisms, they are saved automatically in your front-end or back-end CES database;
however, the changes do not persist unless you perform a save in the tool from which you
launched CES (e.g. Expedition PCB).
To Save Constraint Changes
You can do this in the following ways:
After you exit a CES session, from the invocation tool, save your design.
When working in a CES session launched from the back-end, at the bottom-right corner
of your PCB layout tool, click the rightmost status indicator to load the changes into the
back-end, and then save your design in the PCB layout software.
Table 3-3. Supported Undo/Redo Actions
Design Object Actions
Clearance rule Add, remove, and rename.
Constraint Add, change, propagate,
rule painter, copy, and
paste.
Constraint class Net assignment to class,
add, remove, and rename.
Differential pair Add, remove, and auto-
assign.
Net class Net assignment to class,
add, remove, and rename.
Noise rule Add and remove.
Pin pair Auto pin-pair, manual pin-
pair, and remove.
Rule-area scheme Add, remove, and rename.
Template Rename.
Z-axis clearance rule Add, remove and rename.
Note
Some design tools automatically save your design data (e.g. DxDesigner). Depending on
the tool from which you launched CES, you may not have to explicitly save. Please refer
to the documentation for your design tool for information about saving design changes in
your invocation tool.
Overwriting the Board Station RE Log File
When your constraint-driven design flow includes Board Station RE, you can configure CES to
overwrite the Ces_RE.txt log file each time CES saves its data. By default, CES appends new
log file information to Ces_RE.txt.
To Overwrite the Log File With Each Save
1. Using an ASCII text editor, open your <Install
directory>/7.xBSXE/SDD_HOME/standard/workbench.ini file, and then navigate to the
[CES] section.
2. Add the following line:
OverwriteReLog=True
3. Save your changes.
Note: In order to disable overwrite, set OverwriteReLog=False, or remove the line
entirely.
Chapter 4
Rule-Area Scheme Creation
This section covers rule-area scheme creation. Some of the topics included are trace and via rule
specification, clearance-rule set creation, and class-to-class clearance rule assignment. This
section also provides information about package type clearance rules, general clearance rules,
and how to reset clearance rules. Please refer to the table of contents for the full listing of topics
included in this section.
Creating Schemes to Represent PCB Rule Areas
You create rule area schemes to represent distinct rule areas on a PCB. After you create a
scheme, you can define trace and via rules and clearance rule sets to which only nets within that
board area must adhere. The (Master) scheme represents the majority of your board's clearances
and widths, which are used by all areas and layers that do not have a user-created rule area and
scheme assigned.
Typically, you create several or more rule-area schemes for a PCB. By doing so, you can
separate areas of a board, and then manage constraint requirements for each board area
independently instead of using global rules. Commonly, global rules can be heavily constrained
due to the requirements of relatively small collections of critical nets that cross through
concentrated board areas.
To Create a Rule-Area Scheme
1. From the Navigator, right-click Schemes, and then click New Scheme.
Alternative: With the CES Spreadsheet Trace & Via Properties page or the
Clearances page active, from the Main toolbar, click .
Rule: Clicking creates a new design object based on context. For example, when the
Clearances page is active and an existing clearance rule set is highlighted, clicking this
button creates a new clearance rule set.
2. Replace the default name <user>_New with a unique name for the scheme.
(Minimum) Scheme Clearances and Widths
The rules within the (Minimum) scheme reflect the minimum clearances and widths defined
across all net classes within each scheme. Because these rules are generated on the fly, you
cannot change them directly. Because each rule area can have a different net class scheme, and
because each net class scheme can have a full set of widths and clearances, it may be difficult to
tell if some of the rules have been set below the minimum acceptable rules for manufacturing.
Specifying Trace and Via Rules for Rule-Area Schemes
By using the minimum scheme, you can verify that you are not violating manufacturing
minimums within any of the schemes that you have created.
Note
Typically, you do not assign the minimum net class scheme to a rule area on the board;
however, when you have an area that requires the absolute minimum clearances that you
defined across all other net class schemes, you can assign this scheme to a rule area in
your design.
Due to the nature of the minimumscheme, it will not always include all class-to-class clearance
rules, but instead the clearance rule with the minimum constraint value among duplicates. For
example, when you have a clearance rule between class A and class B in the Master scheme,
and an additional scheme you created defines the same relationship between class a and class b,
the minimum scheme includes the clearance rule with the lowest constraint value.
Related Topics
Creating Clearance Rule Sets for Rule-Area Schemes on page 120
Copying, Renaming, and Deleting Rule-Area Schemes on page 135
Specifying Trace and Via Rules for Rule-Area
Schemes
After you create a scheme to represent a rule area on a PCB, you can specify the trace and via
rules to which nets within the rule area must adhere. You can simultaneously define trace and
via rules for all board layers for nets in a net class, or you can do so individually for each board
layer.
When specifying trace and via rules, you can define values such as minimal, typical, and
expansion trace widths, typical impedance, and differential pair spacing. You can also override
these values for from-tos that must be routed on specific board layers.
Note
When you change the value for typical trace width, the field solver uses the existing
board stackup to calculate typical impedance. When you change the value for typical
impedance, the field solver is used to calculate typical width.
Common Tasks
Defining Via Assignments on page 119
To Specify Trace and Via Rules for a Rule-Area Scheme
1. From the CES Spreadsheet Trace & Via Properties page, expand a scheme.
Specifying Trace and Via Rules for Rule-Area Schemes
Alternative: Fromthe Navigator, expand Schemes, expand a specific scheme, and then
click Trace & Via Properties.
2. Expand the Default physical net class, or a unique physical net class that you created
previously, and then define trace and via rules in one of the two following ways:
To simultaneously define trace and via rules for all board layers, in the physical net
name row (e.g. Default), specify Route, Trace Width, Typical Impedance, and Diff
Pair Spacing rules.
Example: To specify a MinimumTrace Width value of 0.008 for all board layers for
nets that are a part of the Default physical net class, enter 0.008 in the Minimum
field, and then press Enter. CES updates each board layer to include this Minimum
Trace Width value.
To individually define trace and via rules for each board layer, in the appropriate
board layer row (e.g. PHYSICAL_1), specify Route, Trace Width, Typical
Impedance, and Diff Pair Spacing rules.
Rule: When specifying layers to route, you must do so in a Master scheme net class.
When working on a net class in the Master scheme and you change a net class via to
(None), all user-defined schemes automatically change to (None) for that net class.
Example: To specify an Expansion Trace Width value of 0.01 for board layer 1 of
the Default physical net class, in the PHYSICAL_1 row, enter 0.01 in the Expansion
field, and then press Enter.
Defining Via Assignments
You can assign a specific via to a net class when the default via is not suitable. When defining
via assignments, you can choose from the default, none, or any available vias. For all via
assignments other than default, the CES Spreadsheet indicates the specification with "Custom"
in the Via Assignments field.
To Define Via Assignments
1. From the CES Spreadsheet Trace & Via Properties page, expand a scheme.
2. In the Via Assignments field of the net class for which you want to define or modify a
via assignment, click .
Alternative: Click a net class spreadsheet row, and then from the Edit menu, click Via
Assignments.
3. From the Via Assignments dialog box, in the Net Class Via column, click the pulldown
to specify a different via assignment, and then click OK.
Tip: When defining multiple via assignments simultaneously, to set all to the default
assignment, click Set to Default.
Note: Optionally, you can use the dropdown buttons to change the Scheme and Net
Class you want to modify
Related Topics
Creating Schemes to Represent PCB Rule Areas on page 117
Copying, Renaming, and Deleting Rule-Area Schemes on page 135
Overriding Trace Width Constraints for From-Tos on page 161
Creating Clearance Rule Sets for Rule-Area
Schemes
After you create a scheme to represent a rule area on a PCB, you can specify clearance rules to
which net objects within the rule area must adhere. You can define clearance rules such as Trace
to Pad, SMD Pad to Trace, Resistor to Via, and Via to Plane. Different net classes often require
unique design rules in order to maintain signal integrity during transmission. By creating
clearance rule sets, you can address these requirements. Because CES handles conflicts between
rule set constraints, when one does occur, the larger clearance value is used.
You can also define z-axis clearance rules like Trace to Trace and SMD Pad to Trace. Unlike
standard clearance rules, which control spacing between design objects on the same signal
layer, z-axis clearance rules control spacing between design objects on different signal layers.
Z-axis clearance rules are especially important for high-speed designs where net density is very
tight.
Note
The (Default Rule) and (Default Z-Axis Rule) clearance rule sets contain the default
clearances for a design. When assigning clearance rule sets between net classes, the
values in (Default Rule) are used by default; however, (Default Z-Axis Rule) values are
not used by default. You must explicitly assign them, or the rules of a different z-axis
clearance rule set, between net classes.
It is important to note that z-axis clearance rules are absolutes based on just clearance. No
exceptions are made as a result of layer-direction bias. For example, when dielectric thickness is
smaller than a z-axis clearance constraint, no applicable trace is allowed to run over or under
another trace. This is still the case if the traces cross at right angles. Currently, z-axis clearances
are not applied between segments of the same net.
Common Tasks
Defining Embedded Resistor Clearance Rules on page 123
Defining SMD Clearance Rules on page 125
To Create a Clearance Rule Set
1. Fromthe Navigator, expand Schemes, right-click a specific scheme, and then click New
Clearance Rule.
Alternatives:
From the CES Spreadsheet Clearances page, right-click a scheme, and then click
New Clearance Rule.
From the CES Spreadsheet Clearances page, expand a scheme, click an existing
clearance rule, and then from the Main toolbar, click .
2. Replace the default name <user>_New with a unique name for the clearance rule set.
Result: You can now edit the values of any scheme except for the (Minimum) scheme.
The (Minimum) scheme contains non-editable clearance rules that are the minimum
values across all schemes.
To Define Clearance Rules for a Rule Set
1. From the CES Spreadsheet Clearances page, expand the (Master) scheme, or a
previously defined scheme.
2. Expand the clearance rule set for which you want to define clearance rules, and then
make your definitions in one of two ways:
To simultaneously define clearance rules for all board layers, in the clearance rule
set name row (e.g. (Default Rule)), specify any appropriate clearance rules.
Example: When your distance unit is thousandths, to specify a Trace To Trace
separation of 15 for all board layers, in the (Default Rule) row, enter 15 into the
Trace field of the Trace To heading, and then press Enter. CES updates each board
layer to include this Trace to Trace value.
To individually define clearance rules for each board layer, in the appropriate board
layer row (e.g. PHYSICAL_2), specify any appropriate clearance rules.
Example: When your distance unit is centimeters, to specify a Pad To Trace
separation of 10 for board layer 1, in the (Default Rule) row, enter 10 into the Pad
field of the Pad To heading, and then press Enter.
Note
Clearance rules are not applied to your design until you create associations between
specific net classes. To do so, please refer to Assigning Class-To-Class Clearance
Rules on page 125.
To Create a Z-Axis Clearance Rule Set
1. From the CES Spreadsheet Z-Axis Clearances page, perform one of the following
tasks:
Right-click an existing z-axis clearance rule set, and then click New.
From the Main toolbar, click .
2. Replace the default name <user>_New with a unique name for the clearance rule set.
To Define Z-Axis Clearance Rules for a Rule Set
From the CES Spreadsheet Z-Axis Clearances page, expand the clearance rule set for which
you want to define clearance rules, and then make your definitions in one of two ways:
To simultaneously define clearance rules for all board layers, in the clearance rule set
name row (e.g. (Default Z-Axis Rule)), specify any appropriate clearance rules.
To individually define clearance rules for each board layer, in the appropriate board
layer row (e.g. PHYSICAL_2), specify any appropriate clearance rules.
Note
Z-axis clearance rules are not applied to your design until you create associations
between specific net classes. To do so, please refer to Assigning Z-Axis Class-To-Class
Clearance Rules on page 126.
Example of Defining Differential Pair Spacing Between Channels and Ports
In this example, you have two ports, each of which consist of 4 differential pairs (i.e. 8
channels). You want to define unique constraint values to control spacing between differential
pairs (a), spacing between differential-pair traces (b), and spacing between traces of each port
(c). The following illustration depicts these spacing requirements.
Figure 4-1. Three Trace-Spacing Requirements
To Define These Spacing Requirements
1. Fromthe CES Spreadsheet Nets page, define Differential Spacing as a in each constraint
class that includes one of these differential pair nets.
2. Create separate net classes for each port, and then place each set of respective
differential pairs into these new net classes (e.g. Port_1 and Port_2).
3. Depending on the PCB layout software you use in your constraint-driven design flow,
perform one of the following tasks:
Expedition PCB Create two clearances rule sets. One for nets within a port (b), and
one for nets between ports (c).
Board Station XE or RE Create one clearance rule set for nets between ports (c). In
these flows, a clearance rule set is automatically created for each net class (i.e. port).
4. From the CES Spreadsheet Clearances page, perform the following tasks:
For the nets within a port clearance rule set (e.g. Within_Port), define Trace to Trace
as b.
For the nets between ports clearance rule set (e.g. Across_Ports), define Trace to
Trace as c.
5. Assign the following class-to-class clearances rules:
Within_Port between net class Port_1 and net class Port_1.
Within_Port between net class Port_2 and net class Port_2.
Across_Ports between net class Port_1 and net class Port_2.
Defining Embedded Resistor Clearance Rules
When your design includes embedded resistive components like thick-film and thin-film
resistors, you can define spacing requirements between these parts and conductive board
elements (e.g. traces, pads, vias), and other resistors. Embedded resistors are located on internal
board layers. In the following illustration, each internal board layer has one embedded resistor.
Figure 4-2. Embedded Resistors on Each Internal Board Layer
The clearance area that you define with each Resistor to <object> and EP Mask to <object>
constraint is depicted in the illustration below. As you can see, thick-film resistor clearance is
based on resistor material adjacency. Clearance of thin-film resistors is based on production
mask adjacency.
Figure 4-3. Embedded Resistor Clearances Defined by These Constraints
Unlike embedded resistors, you do not need to define unique clearance rules for embedded
capacitive components. Standard pad clearance constraints (e.g. Trace to Pad, Pad to Pad, Pad
to Plane) handle their clearance requirements. Examples of embedded capacitive components
are mezzanine, screen-printed, and interdigitated capacitors.
To Define Thick-Film Resistor Clearance Rules
From the CES Spreadsheet Clearances page, define the following constraints for an entire
clearance rule set, or individually for each board layer of a rule set:
Embedded Resistor To Trace on page 264
Embedded Resistor To Pad on page 265
Embedded Resistor To Via on page 266
Embedded Resistor To Resistor on page 267
To Define Thin-Film Resistor Clearance Rules
EP Mask To Trace on page 268
EP Mask To Pad on page 269
EP Mask To Via on page 270
EP Mask To Resistor on page 271
Assigning Class-To-Class Clearance Rules
Note
Mask refers to the production mask of a thin-film resistor. It does not mean solder
mask.
Defining SMD Clearance Rules
When your design includes surface mount devices (SMD), you can define spacing requirements
between the pads of these devices and conductive board elements (e.g. traces, vias). SMDs are
also commonly referred to as surface mount technologies (SMT).
To Define SMD Clearance Rules
Trace To SMD Pad on page 256
Via To SMD Pad on page 262
To Define Z-Axis SMD Clearance Rules
From the CES Spreadsheet Z-Axis Clearances page, define the following constraints for an
entire clearance rule set, or individually for each board layer of a rule set:
Trace To SMD Pad on page 278
Related Topics
Specifying General Clearance Rules on page 133
Assigning Class-To-Class Clearance Rules
After you create clearance rule sets for a rule-area scheme, you can assign class-to-class
clearance rules that maintain special clearances between specific net classes. To define
additional net classes, please refer to Creating Net Classes on page 139. By doing so, you can
apply the rules you previously defined in a clearance rule set to one or more pairs of physical
net classes to maintain adjacency relationships between nets. When selecting net classes to
associate with a clearance rule, you can quickly specify all net classes by using the (All) row.
Note
Class-to-class clearance rules are obeyed between the top-level net classes to which they
are assigned. Any sub-level net classes in the top-level classes will not obey these rules.
Assigning Z-Axis Class-To-Class Clearance Rules
To Assign a Class-To-Class Clearance Rule
1. With the CES Spreadsheet Clearances page active, from the Clearances toolbar, click
.
Alternative: With the CES Spreadsheet Clearances page active, from the Edit menu,
click Clearances, and then click Class to Class Clearance Rule.
2. From the Class to Class Clearances dialog box, In the Net Class to Class Clearance
Rules for Scheme pulldown, select a scheme.
3. In the grid display under Source Net Class(es), click within an editable cell to select the
rule to use between two specific net classes.
Tip: To simultaneously assign the same rule to multiple cells, use Ctrl-click and Shift-
click to select a group of cells. After you have selected the last cell, you must continue
holding Ctrl or Shift while you make the rule selection.
4. Continue making rule assignments between net classes.
5. When you want to assign class-to-class clearance rules for a different scheme, return to
step 2.
Rule: Those that you do not explicitly define do not use (Default Rule).
To Delete a Class-To-Class Clearance Rule
.
2. From the Class to Class Clearances dialog box, In the Net Class to Class Clearance
Rules for Scheme pulldown, select a scheme.
3. Click the row of an existing class-to-class clearance rule assignment, and then click the
blank selection.
4. After you finish deleting assignments, click OK.
Related Topics
Assigning Z-Axis Class-To-Class Clearance
Rules
After you create z-axis clearance rule sets, you use the same spreadsheet page to assign class-to-
class clearance rules that maintain unique clearances between specific net classes. By doing so,
you can apply the rules you previously defined in a z-axis clearance rule set to one or more pairs
Assigning Z-Axis Class-To-Class Clearance Rules
of physical net classes to control adjacency relationships between nets. When selecting net
classes to associate with a clearance rule, you can quickly specify all net classes by using the
(All) row. To define additional net classes, please refer to Creating Net Classes on page 139.
Note
When you update your PCB board stackup after already having defined z-axis clearances
in CES, the clearance rules will become corrupted or lost. You must re-enter them and
assign them again.
When assigning these clearance rules between net classes, you can only create relationships for
the (Master) scheme; however, they are used for all rule areas (i.e. rule-area schemes). For
example, when your design includes 10 user-created rule-area schemes, assigning a z-axis
clearance rule set between net class A and net class B results in those 10 schemes and the
(Master) scheme using the assignment.
The following illustration shows z-axis trace to trace relationships for two net classes. Because
the net classes contain mostly high-speed nets, that by nature are driving fast edge rates, it is
important to specify adjacent layer clearances between their net objects.
Figure 4-4. Example Z-Axis Trace to Trace Minimums
Depending on the number of adjacent layers that separate two design objects, z-axis clearance
rules may not be necessary. For this purpose, you can disable these rules when the number of
layers between design objects exceeds a certain amount. For example, after applying a z-axis
clearance rule set named Fast_Clocks to net class A and net class B, you specify that the
maximum depth is 5 layers. As a result, Trace to Trace distances between nets in class A and B
will not be obeyed when validating z-axis distances between layers 1 and 7, 2 and 9, etc.
Note
Class-to-class clearance rules are obeyed between the top-level net classes to which they
are assigned. Any sub-level net classes in the top-level classes will not obey these rules.
Assigning Package Clearance Type Rules
To Assign a Z-Axis Class-To-Class Clearance Rule
1. With the CES Spreadsheet Z-Axis Clearances page active, fromthe Clearances toolbar,
click .
Alternative: With the CES Spreadsheet Z-Axis Clearances page active, from the Edit
menu, click Clearances, and then click Z-Axis Class to Class Clearance Rule.
2. In the grid display under Source Net Class(es), click within an editable cell to select the
rule to use between two specific net classes.
Tip: To simultaneously assign the same rule to multiple cells, use Ctrl-click and Shift-
click to select a group of cells. After you have selected the last cell, you must continue
holding Ctrl or Shift while you make the rule selection.
3. Optionally, to specify a maximum layer depth between design objects, in the cell you
just edited, click . From the Setup Z-Axis Clearance dialog box, click the Max layer
depth dropdown, select a maximum value, and then click OK.
Example: When specifying a maximum layer depth of 3, nets within classes governed
by the clearance rule are not required to obey it unless they are separated by no more
than 3 board layers.
4. Continue making rule assignments between net classes.
Rule: Those that you do not explicitly define do not use (Default Z-Axis Rule).
To Delete a Class-To-Class Clearance Rule
1. With the CES Spreadsheet Z-Axis Clearances page active, fromthe Clearances toolbar,
click .
2. Click the row of an existing class-to-class clearance rule assignment, and then click the
empty selection, which is the first in the list.
3. After you finish reverting assignments, click OK.
You can assign clearance rules to each package type to specify the required amount of clearance
distance between a package type and all other design components that come close to it on a
board layer. Each package type clearance rule you define can be followed when the component
is located on the top of a board layer, the bottom of a board layer, or both placements. For
example, you can define a package type clearance rule for integrated circuit flip chips that
requires a layer-bottom placement clearance of 200 th between this component type and all
other design objects.
Note
When using Expedition PCB as part of your design flow, unique package types you
create in the Cell Editor of that PCB layout tool will show up in CES as part of the drop-
down list of selectable package types. To create a unique package type in Expedition
PCB, you must use the Clearance Type field of the Cell Editor. For more information,
please refer to the documentation for Expedition PCB.
In addition to defining package clearance type rules, you can also define clearance-type-to-
clearance-type rules. These rules give you the ability to specify board layer and component
directional clearances between specific package types. The illustration below depicts the
difference between side-to-side, end-to-end, side-to-end, and end-to-side clearances between
package type clearance rules.
Figure 4-5. Clearance-Type-to-Clearance-Type Directional Clearances
You might be wondering why side-to-end and end-to-side are not the same. Although you can
define them as if they are, having the ability to define clearances based on which side and
which end give you greater flexibility. For example when the end of an IC-BGA is next to the
side of an IC-SIC, you might want more clearance than when the side of an IC-BGA is next to
the end of an IC-SIC. Commonly, a distinction like this is used to provide a greater or lesser
amount of room depending on adjacency of component pins. Some components have the same
number of pins on sides and ends, while others have pins on just sides or ends.
When defining end-to-side and side-to-end rules, it is important not to define redundant rules.
For each pairing of package types, they only need a single end-to-side rule and one side-to-end
rule for the purpose of defining all clearance requirements. For two example packages A and B,
you would define just one of each set of the following rules, but not both:
End A to side B, side A to end B
Side B to end A, end B to side A
Note
When you assign a clearance-type-to-clearance-type rule, the board-side clearances you
defined in each package clearance type rule are overridden by the clearances defined in
the package adjacency rule.
Other Common Tasks
Determining Package Side and End on page 132
Creating New PCB Layout Package Types in a Board Station Flow on page 132
To Assign Package Clearance Type Rules
.
click Clearances, and then click Assign Package Type Clearances.
2. From the Package Clearance Type Rules dialog box, to the right of Package clearance
type override rules, click .
Result: A new package type row is created.
3. In the Package Clearance Type cell, click .
4. From the Select Package Type dialog box, select a package type (e.g. IC - BGA), and
then click OK.
5. In the Side cell, click to specify board layer side of top, bottom, or both sides.
6. In the Clearance cell, specify the required clearance distance for this package type.
Rule: This clearance defines the required distance between this package type and all
other design objects.
To Assign Clearance-Type-to-Clearance-Type Rules
.
2. If you have not done so already, create two package clearance type rules to associate
before you continue to step 3.
3. Fromthe Package Clearance Type Rules dialog box, next to Clearance type to clearance
type clearance override rules, click .
Result: A new rule row is created.
4. In the Pkg Clr Type cell of the new row, click to select the first Package clearance type
override rule you created.
5. In the second Pkg Clr Type cell, click to select the second Package clearance type
override rule you created.
6. In the Side, Direction, and Clearance cells, specify the side, direction, and clearance
distance between package types, and then click OK.
Note: The direction types Side to End and End to Side are unique and therefore
must be defined separately.
To Delete a Package Clearance Type Rule
.
2. From the Package Clearance Type Rules dialog box, under Package clearance type
override rules, click a row, and then click .
Tip: To select multiple rules, use Ctrl-click.
To Delete a Clearance-Type-to-Clearance-Type Rule
.
2. From the Package Clearance Type Rules dialog box, under Clearance type to clearance
type clearance override rules, click a row, and then click .
Tip: To select multiple package type to package type clearance rules, use Ctrl-click.
Example of Assigning a Clearance-Type-to-Clearance-Type Rule for Both
Layer Sides and All Directions
In this example, you want to assign a clearance-type-to-clearance-type rule between Discrete -
Chip components and IC - Flip Chip parts. Each of these package types already has a package
clearance type rule that requires a clearance distance of 50 th between instances of these
components and all other board objects. However, when these components are in the same
vicinity of a board layer, you require a clearance distance of 500 th between them, and for all
directions.
To Assign a Clearance-Type-to-Clearance-Type Rule Between These
Components
.
2. Fromthe Package Clearance Type Rules dialog box, next to Clearance type to clearance
type clearance override rules, click .
3. In the first Pkg Clr Type cell of the new row, select Discrete - Chip.
4. In the second Pkg Clr Type cell, select IC - Flip Chip.
5. In the Side cell, select Both, and then in the Direction cell, select All.
6. In the Clearance cell, enter 500. After you finish, the bottom portion of the Package
Clearance Type Rule dialog box should look like the following illustration.
Figure 4-6. Discrete - Chip to IC - Flip Chip Clearance Rule
Determining Package Side and End
In order to define the appropriate clearance rules between packages, you need to know which
parallel sides of a package are defined in your layout system as the sides, and which are
defined as the ends. Although it is not always the case, the general practice is for users who
create layout packages to define the long, pin sides as sides, and the other, no-pin sides as
ends. For square packages, which nearly always have pins on all sides, sides and ends should
be treated the same and assigned duplicate rules.
When a user creates a package in the cell editor, at that point they define package sides and
ends. After creation, though, those attributes are not editable. They are also not viewable unless
the person who created the cell added a user layer that provides this info. Doing so is a best
practice in that it provides a record of these declarations, and one that your organization should
adopt if it has not done so already.
In cases where your design team does not follow a strict protocol with regard to side and end
definition, or mandatory creation of a user layer, you should talk to the person in your
organization who created the layout package. In cases where you can not determine this, you
should treat a rectangular package like a square package (i.e. pins on all sides) and use
duplicate clearance values on sides and ends.
Creating New PCB Layout Package Types in a Board
Station Flow
When you create a unique package type instead of selecting one fromthe list of those available,
in order to assign the new package type to a part in your Board Station XE or Board Station RE
PCB layout environment, you must edit the cell.hkp or layout.hkp file to include the new
package type. After you do so, the new package type will be associated with either a library part
or a part instance.
Specifying General Clearance Rules
To Update the Cell File or Layout File
1. Create the ASCII version of the cell or layout database, and then perform one of the
following tasks:
To add the newpackage type to the cell database, open the cell.hkp file, and then add
a new TEXT property under the appropriate .PACKAGE_CELL entry in the
following form: ..TEXT "CELL_CLR_TYPE" "<new package type>"
Example: To add a new package type called MyPkgType1, your TEXT property
would read as follows: ..TEXT "CELL_CLR_TYPE" "MyPkgType1"
To add the new package type to the layout database, open the layout.hkp file, and
then add a new TEXT property under the appropriate
.PACKAGE_CELL_FROM_LIB entry in the following form: ..TEXT
"CMP_CLR_TYPE" "<new package type>"
Example: To add a new package type called MyPkgType2, your TEXT property
would read as follows: ..TEXT "CMP_CLR_TYPE" "MyPkgType2"
2. On the line right below the new TEXT property, add the following: ...TEXT_TYPE
PROPERTY_PAIR
Example: In the cell.hkp content below, the new package type MyPkgType1 has been
added to the antswtch518 PACKAGE_CELL.
.PACKAGE_CELL "antswtch518"
..TEXT "CELL_CLR_TYPE" "MyPkgType1"
...TEXT_TYPE PROPERTY_PAIR
3. Reimport the updated cell.hkp or layout.hkp file into your PCB layout environment.
You can specify general clearance rules to define a default set of clearance rules that are used
initially by each net class you create. After you create a net class, you can modify clearance
rules per the specifications of that net class. Aside from providing net class defaults, general
clearances rules are also used to define clearances for a variety of PCB elements regardless of
net class. The minimum distance between testpoint centers, for example, is a general clearance
rule that is set globally and obeyed by all nets.
To Specify General Net Class Clearance Rules
.
click Clearances, and then click General Clearances.
2. From the General Clearance Rules dialog box, modify the rules that have an editable
value. Editable rule values are set against a white background. Please refer to the table
below for explanations of each general clearance rule.
Rule: A number of specific rules are read-only when you use them in conjunction with
Board Station RE. The rules are Contour & Mounting Hole to Mounting Hole, Trace to
Resistor, Pad to Resistor, and Testpoint Center to Testpoint Center.
3. After you finish modifying general clearance rule values, click OK.
Table 4-1. General Clearance Rules
Rule Purpose
Cavity Inside Edge to Parts Defines the minimum required distance between the
inside edge of a cavity and all parts.
Note: This general clearance rule is supported in just the
Expedition Enterprise (EE) flow.
Cavity Outside Edge to
Non-Plane Conductor
Defines the smallest required distance between the outside
edge of a cavity and all non-plane conductors.
Cavity Outside Edge to
Plane Conductor
Defines the minimum required distance between the
outside edge of a cavity and all plane conductors.
Cavity Edge to Cavity Edge Defines the smallest required distance between a cavity
edge and all other cavity edges.
Contour, Cavity &
Mounting Hole to Mounting
Hole
Defines the minimum required distance between a
mounting hole (including contour and cavity) and all other
mounting holes.
Contour & Mounting Hole
to Non-Plane Conductor
Defines the smallest required distance between a
mounting hole and all non-plane conductors.
Contour & Mounting Hole
to Plane Conductor
mounting hole (including contour) and all plane
conductors.
Copying, Renaming, and Deleting Rule-Area Schemes
Related Topics
Copying, Renaming, and Deleting Rule-Area
Schemes
You can copy, rename, and delete rule-area schemes to reuse and remove rule-area schemes.
For example, by copying a rule-area scheme for which you have defined trace and via rules and
clearance rule sets, you can rename the copy, and then make modifications to that rule-area
scheme to reuse the majority of its constraint definitions on another area of the board.
As you make changes to your schemes, you can also undo or rollback those changes to return
one or more schemes to a previous design state. For example, after deleting a specific rule-area
scheme, you can quickly re-add it without having to manually recreate it.
In addition to copying top-level schemes, you can copy specific clearance rule sets contained
within a scheme. This is useful when you want to duplicate only a subset of scheme, instead of
an entire PCB rule area.
Caution
When you rename a scheme, all rule areas within that scheme are automatically reset to
those in the (Master) scheme. You must go into the PCB systemand reset the rule areas to
use the new scheme created as a result of renaming the scheme.
Placement Outline to
Placement Outline
placement outline and all other placement outlines.
Placement Outline to
Placement Obstruct
placement outline and all placement obstructs.
Placement Outline to Board
Edge
placement outline and all board edges.
Trace to Resistor Defines the minimum required distance between a trace
segment and all resistors.
Pad to Resistor Defines the smallest required distance between a pad and
all resistors.
Testpoint Center to
Testpoint Center
Defines the minimum required distance between the
center of a testpoint and all other testpoint centers.
Table 4-1. General Clearance Rules
Rule Purpose
Resetting Clearance Rules to the Master Scheme
To Copy a Rule-Area Scheme
1. From the Navigator, expand Schemes.
Alternative: Locate a scheme using the CES Spreadsheet Trace &Via Properties page
or Clearances page.
2. Right-click a scheme name, and then click Clone.
Result: The scheme is copied and given the following default name:
<user>_<scheme>_clone
3. Rename the copy by hovering over it and then clicking once.
4. Modify the name of the scheme, and then press Enter.
To Rename a Rule-Area Scheme
2. Right-click a scheme name, and then click Rename.
Alternative: You can also modify the name of a scheme by hovering over it and then
clicking once.
3. Modify the name of the scheme, and then press Enter.
To Delete a Rule-Area Scheme
2. Right-click a scheme name, and then click Delete.
Alternative: Click a scheme, and then from the Main toolbar, click .
Rule: You cannot delete the (Master) and (Minimum) schemes.
For rule-area schemes that you created, you can reset trace and via properties and clearances to
match the (Master) scheme. The (Master) scheme, which is also known as the default rule set,
typically represents the majority of the clearance and width values for a board. These values are
used by default for board areas that do not have user-created schemes and rule areas assigned to
them.
Resetting all or a subset of the constraints stored in a scheme to the (Master) scheme is most
useful when you are sure that further modifications to a user-created scheme will not result in
appropriate constraint values. Starting over with the default rule set gives you the ability to
start fresh by modifying values of a user-created scheme with the default rules as the starting
point.
To Reset Clearance Rules to the (Master) Scheme
1. From the Navigator, expand Schemes, right-click a scheme, and then click Reset to
(Master).
Alternative: With a scheme highlighted, from the Main toolbar, click , or from the
Edit menu, click Clearances, and then click Reset to Master.
2. Verify that the Area Scheme field lists the appropriate scheme.
3. By default, all constraint types are preselected. Click to de-select constraint types that
you do not want to reset to the (Master) scheme, and then click OK.
Example: To exclude resetting MinimumWidths, click to de-select this set of constraint
values.
Example of Resetting Class-To-Class Clearances and Expansion Widths to
Those of the (Master) Scheme
In this example, you want to reset just the class-to-class clearance rules and expansion widths of
user-created scheme SchemeA to those of the (Master) scheme.
To Reset This Subset of Constraints
1. From the Navigator, expand Schemes, right-click SchemeA, and then click Reset to
(Master).
2. From the Reset to (Master) dialog box, click Unselect all, and then click to select the
following constraint types:
Class to Class clearances
Expansion Widths
3. Verify that the Area Scheme field lists the scheme that you want to reset to the constraint
values of the master scheme, and then click OK.
Chapter 5
Net Class Definition
This section covers net class definition. Some of the topics included are creation of net classes,
net addition, and determination of net class assignments. This section also provides information
about creating a net class from an existing net class, and deletion of net classes. Please refer to
the table of contents for the full listing of topics included in this section.
Creating Net Classes
You can create net classes to group specific types of nets and then define board-level
physical/manufacturing constraints for multiple nets. For example, you can group nets based on
their function, or level of importance within a design. When grouping nets based on function,
you might classify them to differentiate power and ground nets from signal nets. Net class
constraints are located on the CES Spreadsheet Trace & Via Properties page.
When grouping nets based on their level of design importance, you could classify them to
differentiate critical nets in a design from non-critical nets. For example, a critical net class
could contain data nets that serve as the connections between microprocessors and other critical
connections that require a high-degree of signal integrity.
Note
At first, all nets are automatically assigned to the (Default) net class.
Creating Net Class Hierarchy
After you create a net class, you can create classes that are hierarchically arranged below it. For
example, after creating a top-level class for all signal nets (e.g. Signal Nets) in a design, you
could add hierarchy to the net class by creating additional classes that sit below Signal Nets to
further group the collection of nets that comprise this net class. In the example below, the Signal
Nets class contains two additional classes, which are Critical Nets and Non-Critical Nets.
Creating Net Classes
Figure 5-1. Navigator Showing Signal Nets Class with Two Additional
Hierarchical Classes
When creating net class hierarchy, a common approach is to create additional levels of
hierarchy on an as-needed basis. For example, as you define common constraint values for a
class of nets, you may find that several of the nets benefit frommost of the constraint values, but
require unique values for a few constraints. In this case, you can create a subclass for these
more challenging nets, move those nets into this subclass, and then modify the constraint
values that need more work. You do not need to redefine the other, working constraints because
each subclass is created to include the constraint values of its parent class.
To Create a Net Class
1. From the Navigator, right-click Net Classes, and then click New Net Class.
Alternative: From the CES Spreadsheet Trace & Via Properties page, right-click a
scheme, and then click New Net Class.
2. Replace the default name <user>_New with a name for the net class.
Rule: Net class names can contain up to 128 characters but cannot include the / or !
characters.
Tip: Use a name that reflects the purpose of the class. For example, when creating a net
class that will contain only signal nets, replace New with Signal Nets.
To Create Hierarchy Under a Net Class
1. From the Navigator, expand Net Classes. Right-click a net class, and then click New.
Alternative: From the CES Spreadsheet Trace & Via Properties page, expand any
scheme, right-click a net class, and then click New.
2. Replace the default name <user>_New with a unique name for the hierarchical net
class.
Note: You can create multiple levels of hierarchy.
To Rename a Net Class
1. From the Navigator, expand Net Classes.
Adding Nets to a Net Class
2. Right-click a net class, click Rename, type a new name, and then press Enter.
Alternative: Click a net class to highlight it, and then click it again to make the name
available for editing.
After you create a net class, you can add nets to it to define the group of nets that comprise the
net class. By default, each net class that you create contains no nets or constraint definitions.
When you want to create a net class that includes the constraint definitions of an existing net
class, you do so by creating a net class from an existing class instead of creating a new net class.
When you want to add nets to a net class by using the Design Architect or Board Architect
schematic views, you can accomplish this through cross probing.
Note
Each net can belong to no more than one net class.
Other Common Tasks
Adding Power Nets to a Net Class on page 142
To Add Nets to a Net Class
1. With the CES Spreadsheet Trace &Via Properties page active, fromthe Main toolbar,
click .
Rule: Clicking brings up an appropriate dialog box based on context. For example,
when the Nets page is active, clicking this button displays the Assign Nets to Constraint
Class dialog box.
Alternatives:
From the Navigator, expand Net Classes, right-click a net class, and then click
Assign Nets.
From the Edit menu, click Assign Nets to Classes.
From the CES Spreadsheet Nets page, select one or more nets, right-click a selected
net, and then click Assign Net(s) to Net Class. From the Select Net Class dialog
box, select a net class, and then click OK.
2. Fromthe Assign Physical Nets to Net Class dialog box, specify the net class fromwhich
you want to select nets by clicking the Source Net Class dropdown, and then clicking a
net class.
Example: When you are adding nets to your first custom class you can select from all
nets in the design by specifying the Default class as the source.
3. Specify the net class to which you want to add nets by clicking the Target Net Class
dropdown, and then clicking a net class.
4. Under the nets in source net class listing, specify the nets that you want to add to the
target class.
Tip: To select multiple nets, you can use Ctrl-click, Shift-click, or click-drag. To select
nets by name, in the field below the list of source nets, enter a search string, and then
click . To sort the list of nets, click the Net Name label. You can also move nets
individually by double-clicking a specific source net.
5. Click , and then click Apply or OK.
Tip: Before clicking OK, make sure that the list of target nets is accurate. To remove
any nets from the list of target nets, click to select them, and then click .
Result: The target nets are added to the net class; these nets are no longer a part of the
source class from which they originated.
To Add a BA or DA Schematic Net to a Physical Net Class
1. Make sure that cross probing is on.
Tip: To turn on cross probing, from the Setup menu, click Cross Probing. When cross
probing is enabled, a check mark appears next to its menu command.
2. From the schematic, click the net you want to add to a net class.
3. From CES, verify that the cross-probed net is highlighted.
4. With the Trace & Via Properties page active, from the Main toolbar, click .
Example of Adding All Available Nets in a Source Class to a Target Class
1. From the Assign Physical Nets to Net Class dialog box, specify a source net class, and
then specify a target net class.
2. Click , and then click OK.
Example of Swapping All Nets in One Class With All Nets in Another Class
1. From the Assign Physical Nets to Net Class dialog box, specify a source net class, and
then specify a target net class.
Adding Power Nets to a Net Class
Because power nets are not displayed on the CES Spreadsheet Nets page by default, you must
use the Assign Physical Nets to Net Class dialog box to move them from the (Default) net class
Determining Net Class Assignments
to another net class for more specific board-layer constraint definitions. To do so, please use the
above procedure, To Add Nets to a Net Class on page 141.
Related Topics
Creating Net Classes on page 139
Creating a Net Class From an Existing Net Class on page 144
Deleting Net Classes on page 144
Determining Net Class Assignments
After you create net classes and add nets to classes, you can view the list of all nets that are
contained in a specific class. The Nets page method, which is detailed in the above alternative
method is useful for determining net class on a net-by-net basis. The method below gives you
the ability to determine net association from the perspective of a net class.
To View the List of All Nets That Comprise a Net Class
1. With the CES Spreadsheet Trace &Via Properties page active, fromthe Main toolbar,
click .
Alternative: From the CES Spreadsheet Nets page, refer to the Net Class constraint to
determine the net class to which one or more nets is assigned.
2. From the Assign Physical Nets to Net Class dialog box, use the Source Net Class
pulldown to select the contents of the net class that you want to view.
3. Refer to the Physical nets in source rule class list to determine all nets that are assigned
to this net class. In the following illustration, the 15MIL net class includes four nets.
Figure 5-2. 15MIL Net Class With Four Net Assignments
4. Optionally, you can sort the list of nets by ascending and descending order. To do so,
click the Net Name heading.
Creating a Net Class From an Existing Net Class
Related Topics
Deleting Net Classes on page 144
Creating a Net Class From an Existing Net Class
You can create a net class from an existing class to quickly create a net class that includes the
same constraint definitions as the existing net class. For example, after creating a net class that
includes constraint definitions for most signal nets in your design, you can duplicate it, and then
modify the constraint definitions in the duplication.
Tip: It is important to remember that creating a net class froman existing net class copies
constraints and not nets. After you create a copy, make sure you add the appropriate nets
to it.
To Create a Net Class From an Existing Net Class
1. From the Navigator, expand Net Classes, right-click a net class, and then click Clone.
2. Right-click the name of the clone/copy, click Rename, and then enter a different name.
Alternative: Click the name of the clone/copy, wait, click, and then modify the text in
the box to specify a different name.
3. Specify the group of nets that comprise the new class by adding nets to this net class,
and removing nets from it.
4. Modify the physical constraint values defined in this class such that they are appropriate
for the nets you added to this class in the previous step.
Related Topics
Deleting Net Classes
You can delete net classes that you no longer require. Prior to deleting a net class, make sure
that it is the appropriate class to delete. Before deletion of a net class, CES prompts you to
verify that you have selected the intended net class. After you delete a net class, you can re-add
it to the list of net classes using undo or rollback.
Note
Before you can delete a net class that includes nets, you must empty its contents by
moving nets to a different class, and removing any net-class hierarchy. You will also
want to delete references to the net class in any class-to-class clearance rules.
To Delete a Net Class
From the Navigator, expand Net Classes, right-click a net class, and then click Delete.
Alternative: Click a net class, and then press the Delete key.
Chapter 6
Constraint Class Definition
This section covers constraint class definition. Some of the topics included are creation of
constraint classes, net addition, and auto-creation of bus constraint classes. This section also
provides information about creating a constraint class from an existing constraint class, and
deletion of constraint classes. Please refer to the table of contents for the full listing of topics
included in this section.
Creating Constraint Classes
You can create constraint classes to group specific nets and then define electrical and signal
integrity constraints such as length or time-of-flight delay values and overshoot/ringback
voltages. Constraint class constraints are located on the CES Spreadsheet Nets and Noise Rules
pages. After you create a constraint class, you can create more constraint classes below it to
create hierarchy among nets within a constraint class. By doing so, you can apply general
constraints to all nets within the constraint class hierarchy, and then apply more specific
electrical, signal integrity, and high-speed signal integrity constraints to the nets that make up
the further groupings of constraint classes.
For example, after creating a constraint class that contains a dozen similar critical nets and
applying the same rules to each net in the constraint class, you find that two or three of the nets
in the constraint class do not promote signal integrity when they use a few of the rules
designated in the top-level constraint class. To assign slightly different rules to these nets that
require a higher-level of signal integrity, you can create a constraint class within the top-level
constraint class, move these critical nets into the hierarchical constraint class, and then modify
specific electrical rules.
Note
At first, all nets are automatically assigned to the (All) constraint class.
Creating Constraint Class Hierarchy
After you create a constraint class, you can create more constraint classes that are hierarchically
arranged below it. For example, after creating a top-level class for all bus nets (e.g. Bus Nets)
in a design that should share many of the same electrical rules, you could add hierarchy to the
constraint class by creating additional classes that sit below Bus Nets to further group the
collection of nets that comprise this constraint class. In the example below, the Bus Nets
constraint class contains two additional classes, which are 8-bit and 16-bit.
Creating Constraint Classes
Figure 6-1. Navigator Showing Bus Nets Constraint Class With Two Additional
Hierarchical Classes
To Create a Constraint Class
1. From the Navigator, right-click Constraint Classes, and then click New Constraint
Class.
Alternative: From the CES Spreadsheet Nets page, right-click a constraint class, and
then click New Top Level Class.
2. Replace the default name <user>_New with a name for the constraint class.
Rule: Constraint class names can contain up to 128 characters but cannot include the \
or ! characters.
Tip: Use a name that reflects the purpose of the constraint class. For example, when
creating a constraint class that will contain only signal nets, replace New with Signal
Nets.
To Create Hierarchy Under a Constraint Class
1. Fromthe Navigator, expand Constraint Classes. Right-click a constraint class, and then
click New.
Alternative: From the CES Spreadsheet Nets page, right-click a constraint class, and
then click New.
2. Replace the default name <user>_New with a unique name for the hierarchical
constraint class.
Note: You can create multiple levels of hierarchy.
To Rename a Constraint Class
1. From the Navigator, expand Constraint Classes.
Adding Nets to a Constraint Class
2. Right-click a constraint class, click Rename, type a new name, and then press Enter.
Alternative: Click a constraint class to highlight it, and then click it again to make the
name available for editing.
Adding Nets to a Constraint Class
After you create a constraint class, you can add nets to it to define the group of nets that
comprise the constraint class. By default, each constraint class that you create contains no nets
or constraint definitions. When you want to create a constraint class that includes the constraint
definitions of an existing constraint class, you do so by creating a constraint class from an
existing constraint class instead of creating a new constraint class.
Note
Each net can belong to no more than one constraint class.
To Add Nets to a Constraint Class
1. With the CES Spreadsheet Nets page active, from the Main toolbar, click .
Rule: Clicking brings up an appropriate dialog box based on context. For example,
when the Trace & Via Properties page is active, clicking this button displays the Assign
Physical Nets to Net Class dialog box.
Alternatives:
From the Navigator, expand Constraint Classes, right-click a constraint class, and
then click Assign Nets.
From the CES Spreadsheet Nets page, select one or more nets, right-click a selected
net, and then click Assign Net(s) to Constraint Class. From the Select Constraint
Class dialog box, select a constraint class, and then click OK.
2. From the Assign Nets to Constraint Class dialog box, specify the constraint class from
which you want to select nets by clicking the Source Constraint Class dropdown, and
then clicking a constraint class.
Example: When you are adding nets to your first custom constraint class you can select
from all nets in the design by specifying the (All) constraint class as the source.
3. Specify the constraint class to which you want to add nets by clicking the Target
Constraint Class dropdown, and then clicking a constraint class.
4. Optionally, limit the source and target net listings to just physical nets. To do so, click to
enable Use physical nets.
5. Under the nets in source constraint class listing, specify the nets that you want to add to
the target class.
Defining Bus Constraint Classes Automatically
Tip: To select multiple nets, you can use Ctrl-click, Shift-click, or click-drag. To select
nets by name, in the field below the list of source nets, enter a search string, and then
click . To sort the list of nets, click .
6. Click , and then click Apply or OK.
Tip: Before clicking OK, make sure that the list of target nets is accurate. To remove
any nets from the list of target nets, click to select them, and then click .
Result: The target nets are added to the constraint class; these nets are no longer a part
of the source class from which they originated.
Example of Adding All Available Nets in a Source Class to a Target Class
1. From the Assign Nets to Constraint Class dialog box, specify a source constraint class,
and then specify a target constraint class.
Example of Swapping All Nets in One Class With All Nets in Another Class
1. From the Assign Nets to Constraint Class dialog box, specify a source constraint class,
and then specify a target constraint class.
Note: When you create a new constraint class while the Assign Nets to Constraint Class
dialog box is displayed, the drop down lists are updated appropriately.
Related Topics
Creating Constraint Classes on page 147
Creating a Constraint Class From an Existing Constraint Class on page 153
Deleting Constraint Classes on page 153
You can automate the process of defining and adding nets to unique constraint classes to group
all nets that comprise a bus. Allowing CES to do this for you automatically saves time and
reduces the instance of error that can be involved when you perform this task manually. After
you give CES the approval to create each constraint class and move the appropriate nets into the
new classes, the Bus constraint for each resultant constraint class is enabled.
Note
The Bus constraint is used to indicate that your PCB layout software should enable bus
planning and routing capabilities for a specific constraint class.
Depending on your constraint-entry process, you will automatically define bus classes before or
after manually creating constraint classes. Regardless of the process you use, CES makes it easy
to keep track of the previous constraint class to which you assigned a net by creating a bus class
as a sub-class of the original class. For example, when you automatically create bus classes for
nets that originate from the default constraint class, (All), each new constraint class is a sub-
class of the (All) class.
Note
After nets are assigned to newly created bus constraint classes, each net in the class is
assigned to a single net class.
Determining Nets That Comprise a Bus
Depending on the option you choose, CES uses one of three methods to determine which nets it
should suggest for grouping as a new constraint class:
Digit suffix CES suggests constraint classes using nets that include numeric characters
at the end of a net name (e.g. MicroNet0 and MicroNet1). The resultant constraint class
name is the common part of the net name (e.g. MicroNet).
Default: The default match type is Digit suffix.
Bus nets CES suggests constraint classes using nets that include typical bus-net
characters (e.g. ~ and _) within a net name. The name of the resultant constraint class
includes a digit range at the end that indicates the number of nets in this class. For
example, Primary_Bus[3:0] means that this bus constraint class will includes 4 nets: net
0, net 1, net 2, and net 3.
Custom net match string Enter a custom search string using letters, numbers and
wildcard characters like * and ?. This method is especially useful when one of the
above methods cannot be used due to an uncommon naming convention for design nets.
To Define Bus Constraint Classes Automatically
1. With the CES Spreadsheet Nets page active, from the Edit menu, click Auto Bus.
2. From the Auto Assign Bus dialog box, in the Electrical Net Match String pulldown,
specify the match type you want to use, and then click .
Result: Under Proposed busses, CES creates a row for each suggested bus. The
Suggested Bus Name cell indicates the new constraint class name that appropriate nets
will be moved into.
3. Optionally, to have CES group bus nets into constraint classes that contain no fewer than
a specific number of nets, activate the Minimum Bus Width checkbox, and then modify
the numerical value in the field to the right to reflect your requirement.
4. You should now verify or adjust the suggested nets for each proposed bus constraint
class. To do so, next to the Suggested Bus Name, click .
5. From the Assign Nets to New Bus Constraint Class dialog box, under Nets in new bus
constraint class, verify that the list of nets is appropriate (or make adjustments), and then
click OK. You can perform the following tasks with this dialog box:
To move a suggested net out of the list, keeping it in its present constraint class, click
.
To move a net froman existing constraint class into the list of nets that will comprise
the new bus constraint class, use the Existing Constraint Classes pulldown and the
Nets in existing constraint class list to select the appropriate nets, and then click .
6. From the Auto Assign Bus dialog box, select the proposed bus constraint classes that
you want to create by placing a checkmark beside each appropriate Suggested Bus
Name.
Note: By default, all proposed bus constraint classes are marked for creation. To quickly
de-select all rows, click . To quickly select all rows, click .
Rule: The Net Classes cell for each proposed bus constraint class lists all net classes that
the proposed list of nets are currently assigned to. After a bus constraint class is created,
each net is moved into the first net class listed in the Net Classes cell.
7. For the proposed constraint classes you select, resolve any naming errors, which are
indicated by shading the background color of a Suggested Bus Name cell. In the
following example, the backslash character needs to be removed from the Suggested
Bus Name to satisfy syntax requirements.
Figure 6-2. Suggested Bus Name With a Syntax Problem (Backslash Character)
8. After you select the proposed bus constraint classes to create, and resolve any naming
errors, click OK.
Result: CES creates a new constraint class for each proposed bus that you selected and
moves the appropriate nets into the new constraint classes.
Related Constraints
Bus on page 282
Creating a Constraint Class From an Existing Constraint Class
Creating a Constraint Class From an Existing
Constraint Class
You can create a constraint class from an existing constraint class to quickly create a constraint
class that includes the same electrical and signal integrity rules as the starting point for a new
constraint class. For example, after creating a constraint class that defines many rules for a large
number of signal nets, you can duplicate it, add specific nets to it, and then modify the rules that
were copied over from the original constraint class to make them appropriate for another group
of nets.
Note
When you create a constraint class from an existing constraint class, the nets in the
existing constraint class remain in that constraint class.
To Create a Constraint Class From an Existing Constraint Class
1. From the Navigator, expand Constraint Classes, right-click a constraint class, and then
click Clone.
2. Right-click the name of the clone/copy, click Rename, and then enter a different name.
Alternative: Click the name of the clone/copy, wait, click, and then modify the text in
the box to specify a different name.
3. Specify the group of nets that comprise the new class by adding nets to this constraint
class.
4. Modify the constraint values defined in this class such that they are appropriate for the
nets you added to this class in the previous step.
Related Topics
Adding Nets to a Constraint Class on page 149
Deleting Constraint Classes
You can delete constraint classes that you no longer require. After you delete a constraint class,
any nets that were contained in it are returned to the (All) constraint class. Before deleting a
constraint class, make sure that it is the appropriate class to delete. Before deletion of a
constraint class, CES prompts you to verify that you have selected the appropriate constraint
class. After you delete a constraint class, you can re-add it to the list of constraint classes using
undo or rollback.
Deleting Constraint Classes
Tip: Although it is not required, before you delete a constraint class you may want to
empty its contents by moving nets to a different class, removing any constraint class
hierarchy, and deleting design-object references to the constraint class. By default, CES
reassigns nets of a constraint class to the (All) constraint class after deletion.
To Delete a Constraint Class
From the Navigator, expand Constraint Classes, right-click a constraint class, and then click
Delete.
Alternative: Click a constraint class, and then press the Delete key.
Chapter 7
Net Constraint Definition
This section covers net constraint definition. Some of the topics included are specification of
general constraints, topologies, and delay rules. This section also provides information about
definition of formulas, overshoot and ringback constraints, and I/O Designer FPGA constraints.
Please refer to the table of contents for the full listing of topics included in this section.
Specifying General Net Constraints
You can use CES to specify general net properties such as topology type and the maximum
number of vias that can be applied to a net. You can specify general net properties individually
for each net, or simultaneously by assigning a property value to a constraint class. When
specifying a single property value for multiple nets through a constraint class assignment, each
net in the constraint class is updated to include the single property value.
Tip: To viewall constraints instead of those that are of a specific type (e.g. net properties,
delays and lengths, overshoot/ringback), from the Group pulldown, select All.
To Specify General Properties for Nets
1. With the CES Spreadsheet Nets page active, from the Group pulldown, click Net
Properties.
Note: These constraints are also displayed as part of the All group, but you may find
it easier to work with general net constraints when the CES Spreadsheet Nets page
displays only them.
2. You can specify these properties in one of two ways:
To simultaneously define a property for all nets in a constraint class, in the constraint
class name row, enter a value into a property field (e.g. # Vias Max), and then press
Enter.
Result: Each net in the constraint class is updated with this value.
To individually define a property of a specific net, in the net row, enter a value into a
property field.
Related Constraints
Analog on page 281
Specifying Topologies for Nets and Constraint Classes
Bus on page 282
Stub Length Max on page 289
Single Ended Characteristic Impedance Value on page 320
Single Ended Characteristic Impedance Tol on page 321
Specifying Topologies for Nets and Constraint
Classes
You can assign pre-defined and custom topology types to specific nets and constraint classes.
When you assign a topology type to a constraint class, all nets within the class take on the
topology type designation. The available pre-defined topology types are MST , Chained ,
TShape , Star , and HTree . When a pre-defined topology type is not appropriate for a
specific net, you can manually define netline ordering.
When you assign a topology type to a net or constraint class, or manually create a unique
topology ordering, you are defining the order in which the router etches transmission lines and
other physical mechanisms that aid in the propagation of electrical signals. CES provides router
instruction in the formof from-tos, each of which is composed of two design or component pins
that respectively designate the router to etch from one pin to another pin.
Note
MST topology type disregards the Stub Length Max constraint. You do not need to define
this constraint when the topology type is MST.
Other Common Tasks
Creating Pin Sets to Construct Advanced Topologies on page 158
From-Tos, Pin Pairs, or Both?
Often times, from-to relationships, and their concept, can be confused with pin pair
relationships, and the design purpose that they serve. To ensure that you have an accurate
understanding of these separate design attributes, refer to the following definitions:
Net line ordering/from-tos Physical pairings of component pins that instruct the router
where to etch from and to when creating physical transmission lines (i.e. traces).
Pin pairs Electrical pairings of component pins that are created for the purpose of
defining electrical relationships between component pins.
Handling Multiple Loads
When there are at least two loads, a virtual pin is created to join all of the sources. The loads are
then balanced from the joining virtual pin. This procedure is followed for TShape, Star, and
HTree topology types.
To Specify Topology Type for a Net or Constraint Class
1. With the CES Spreadsheet Nets page active, from the Group pulldown, click Net
Properties.
Warning: When you change a topology type fromCustomor Complex to a pre-defined
topology type, all pin pairs, from-tos, and virtual pins are deleted.
it easier to work with topology constraints when the CES Spreadsheet Nets page
displays only them.
2. In the spreadsheet row of the net or constraint class to which you want to assign a
topology type, click the Topology Type field, and then select a pre-defined topology
type (MST, Chained, TShape, HTree, or Star), Custom, or Complex.
Alternative: From the Topology toolbar, click a topology type button to specify a pre-
defined topology type ( , , , , or ), or a custom topology ( ).
Tip: To simultaneously specify a pre-defined topology type for multiple nets, use Ctrl-
click, and then from the Topology toolbar, click a topology type button.
Rule: After you choose Customor Complex, the next step is to performnetline ordering
to define the custom topology type. When you include pin sets with a Custom topology,
it is automatically changed to Complex to indicate the usage of pin sets.
To Manually Define Netline Ordering (From-Tos) for a Specific Net
1. From the CES Spreadsheet Nets page, click the row of the net for which you want to
manually define netline ordering, and then from the Topology toolbar, click .
Alternative: After you click a net row, from the Edit menu, click Netline Order.
Rule: Before you can define netline ordering for a net, you must set the topology type
constraint to Custom or Complex.
2. From the list of available pins, click a row to select the From pin.
Pin sets: When defining from-tos between pin sets, select pin sets instead of pins in both
the From and To fields. Also, you can select both types of objects.
3. From the list of available pins, click a row to select the To pin.
4. Verify the From pin and To pin fields, and then click .
Note: When the From pin and To pin fields do not contain the correct pins, click to
clear the designation.
5. Repeat steps 2 through 4 for each from-to you want to create. After you finish, click
OK.
Tip: To automatically create pin pairs from each from-to, enable the Automatically
create pin pairs from from-tos checkbox.
To Delete a Manually Defined Netline Order From-To
From the list of defined netline order from-tos, click a row, and then click .
Tip: To delete all defined netline order from-tos, click .
Creating Pin Sets to Construct Advanced Topologies
When a net contains a large number of pins, sometimes the best approach to constructing an
advanced topology is to group pins into subsets called pin sets. For example, a 16-pin net that
requires characteristics of both T-shape and chained topology types is a good candidate for pin
sets. This would result in 3 pin sets, consisting of two 3-pin T-shape topologies and one 10-pin
chained topology. After you create pin sets, you can define from-to relationships between pin
sets, and pin sets and pins. You can also create higher-level pin sets by grouping existing pin
sets into new pin sets.
To Create a Pin Set
1. From the CES Spreadsheet Nets page, click the row of the net for which you want to
create a pin set, and then from the Topology toolbar, click .
2. From the Netline Order dialog box, click one of the following topology types:
T-shape, which automatically balances load branches, though the trunk branch
may not match. T-shape is used exclusively for constructs that include 3 objects (i.e.
pins or pin sets).
Chained, which chains all selected pins between the first and last pins you
select. No virtual pins are created for this type of pin set.
Minimum spanning tree, which connects selected pins in the best way possible
based on physical location. No virtual pins are created for this type of pin set.
Balanced, which requires the distance between the virtual pin and all pins in the
pin set to be equal.
Unbalanced, which performs no automatic balancing. This is especially useful
when you want to specify unequal constraints on branches of the pin set.
3. From the available pins / pin sets listing, click each pin that should comprise the pin set;
then click Finish.
Rule: When defining a T-shape pin set, you can select no more than 3 pins. For chained
pin sets, make sure that you click the start pin first and the end pin last.
Result: The pin set is added to the listing of Available pins / pin sets. The Pin/Set and
Type columns indicate that a row is a pin set by including the topology type in their text
(e.g. CH 1, Chained). Also, the Set Contents column includes a button.
To Change the Order of Pin-Set Pins
1. From the Netline Order dialog box, in the row of a pin set, click .
2. From the Pin Set Order dialog box, click a pin to move, and then click or .
3. Repeat step 2 for each pin for which you want to change its order; then click Apply.
To Delete Pin Sets
From the Netline Order dialog box, you can do this in one of the following ways:
Click the row of an individual pin set, and then click .
To delete all pin sets, click .
Example of a Complex Net Topology
In the following example, a complex net topology is constructed for a net that has 9 pins. This
net topology is considered complex because it uses both pin sets and from-tos. This complex net
topology includes a T-shaped pin set, a chained pin set, and an MST pin set. It connects each of
the 3 pin sets, all of which include just 3 pins, with 2 from-tos.
First, here is a visual of the complex net topology that we are going to create. It is important to
note that the standard pins are shown as blue. The virtual pins created for the T-shaped pin set
are shown as green to distinguish them from the preexisting, or standard pins.
Figure 7-1. Visual of Complex Net Topology
Next, here is what the Netline Ordering dialog box would look like for the purpose of defining
this complex net topology. The steps you would use to create it are listed after the picture of the
dialog box.
Figure 7-2. Netline Ordering of a Complex Net Topology
To create the above netline ordering, or one that is similar, you would have to use the following
steps:
1. Create a T-shaped pin set (T_1) using pins R3-2, RT1-2, and U1-14.
2. Create a chained pin set (CH_1) using pins U2-14, U3-14, and U4-20.
3. Create an MST pin set (MST_1) using pins U5-14, U6-1, and U7-8.
4. Connect pin sets T_1 and CH_1 by creating a from-to between pins RT1-2 and U2-14.
5. Connect pin sets T_1 and MST_1 by creating a from-to between pins U1-14 and U5-14.
Defining Pin Pairs for Nets
Overriding Trace Width Constraints for From-Tos
After you define the constraint From To Constraints Layer to select a specific board layer for a
from-to to route on, you can optionally override the trace width constraints (e.g. Trace Width
Typical, Trace Width Minimum) defined for the net as part of its trace and via rules.
Note
The net's Topology Type must be Custom, and Filters > Levels > FromTos must be
enabled in order to view CES Spreadsheet rows for from-tos.
To Override Trace Width Constraints for a Specific From-To
From the CES Spreadsheet Nets page, in the From To Constraints Trace Width cell, enter the
override value.
Result: Based on the trace width override you entered, the FromTo Constraints Z0 constraint is
updated to display the calculated impedance.
You can define pin pairs for nets manually, semi-automatically, and automatically. When
automating the pin pair definition process for one or more nets, you should verify the accuracy
of the pin pair definitions that CES produces. When a specific pin pair definition is not
appropriate, you can manually define that pin pair. You use pin pairs to define constraints for
specific nets that result fromthe linking of two pins. Although pin pairing can be thought of as a
physical coupling, a pin pair only defines a relationship that governs an electrical net property.
For example, you can define a pin pair between an output pin of a microprocessor and an input
pin of another microprocessor that are part of the same net and then constrain the signal delay
between these pins such that it stays within a specific threshold, or minimum and maximum.
Note
You can define pin pairs for nets that are of topology type TShape , HTree , Star ,
Custom , or Complex. You cannot define pin pairs for nets that are of topology type
Chained or MST .
Tip: After you define specific pairs of pins, the CES Spreadsheet column referring to a
pin pair designation is preceded with a icon. Be careful not to confuse this icon with
the resultant icon of non-graphical netline ordering ( ), which you use to create from-to
relationships.
To Define Pin Pairs Manually
1. From the CES Spreadsheet Nets page, click a net row. From the Edit menu, click Pin
Pairs, and then click Add Pin Pairs.
2. From the Define Pin Pairs dialog box, click to create a new pin pair relationship.
Optional: To make any internal EBD pins available for pin-pair definition, click .
3. Click the Start Pin field, and then select a pin.
4. Click the End Pin field, and then select a pin.
Tip: To automatically create a pin pair, click instead of selecting the End Pin.
5. Repeat steps 2 through 4for each pin pair you want to manually define.
6. After you finish defining pin pairs, click OK.
To Define Pin Pairs Semi-Automatically
2. From the Define Pin Pairs dialog box, click to create a new pin pair relationship.
3. Click the Start Pin field, and then select a pin.
4. Click .
Result: CES fills the End Pin field.
5. Repeat steps 2 through 4 for each pin pair you want to semi-automatically define.
6. After you finish defining pin pairs, click OK.
To Define All Pin Pairs Automatically
Fromthe CES Spreadsheet Nets page, click a net row, and then fromthe Pairs toolbar, click .
Alternative: After you click a net row, from the Edit menu, click Pin Pairs, and then click
Auto Pin Pair Generation.
To Define Only Simulation Pin Pairs Automatically
From the CES Spreadsheet Nets page, right-click a net row, and then click Auto Simulation
Pin Pair Generation.
Alternative: After you click a net row, from the Edit menu, click Pin Pairs, and then click
Auto Simulation Pin Pair Generation.
Note
Simulation pin pairs are only pairings of load pins and source pins. No other pin
combination is a valid simulation pin pairing.
To Delete One or More Pin Pairs
2. From the Add Pin Pairs dialog box, click to select one or more pin pairs, and then click
.
3. After you finish deleting pin pairs, click OK.
Including Internal Component-Pin Delay
When you want to constrain signal delay such that it includes internal component-pin delays,
you can construct pin pairs using internal EBD pins. When using EBD pins, both pins of the pin
pair must be of this pin type. Depending on your design methodology, you might begin the
constraint process for some pin pairs by including EBD pins at the start, or instead, later change
some standard pin pairs to EBD pin pairs to solve design challenges.
Note
In order to assign EBD pin pairs, you must have an Electrical CES license.
The following illustration depicts the physical difference between an external (i.e. standard) pin
pair and an internal EBD pin pair.
Figure 7-3. Standard and EBD Pin Pairs
As you can see, the physical length of the connection between pin pairs is longer for EBD pin
pairs because internal component connections are included in addition to the trace segment
between external pins. After you create an EBD pin pair, you can specify delay and simulated
delay (i.e. signal edge rate) constraints.
Specifying Delay Rules for Nets
Defining Discrete Component Pin Pairs
When your design includes complex discrete components like resistor packs, you can define pin
pairs for such components. You can define discrete pin pairs manually, or automatically based
on single-inline and dual-inline pin pairing.
Note
Before you can define discrete pin pairs, you must add the reference designator prefix
your design uses for resistor packs (e.g. RP). To do so, from the Setup menu, click
Settings. From the Settings dialog box, under Design Preferences, click Discrete
Component Prefixes, and then in the Resistor cell, add your reference designator. For
example, when RP is your reference designator, and R is the one used for resistors, this
cell will now contain both (e.g. R, RP).
To Define Discrete Pin Pairs
1. From the CES Spreadsheet Parts page, right-click a top-level discrete part that begins
with the reference designator prefix you added above (e.g. RP), and then click Create
Pin Pairs.
2. From the Define Discrete Pin Pairs dialog box, perform one of the following tasks:
To define pin pairs manually, click , and then click within the Start Pin and End
Pin cells to select each pin-pair pin. Repeat this step for each pin pair you want to
create.
Tip: To delete a pin pair, click its row, and then click .
To define pin pairs automatically, click or to create dual-inline or single-inline
pin pairings.
3. After you finish defining discrete pin pairs, click OK.
You can specify delay rules for nets, differential pairs, and pin pairs. When specifying delay
rules, you can do so based on physical or electrical properties. For example, to specify delay
from an electrical perspective, use time of flight instead of length. Time of flight is an electrical
observance that is defined by the duration of time for signal propagation between two points
(e.g. pins). Conversely, to specify delay from a physical perspective, use length instead of time
of flight. Length delay is a physical rule that defines the minimum and maximum trace distance
between pins. When a delay rule of this type is put in place, the router uses these minimum and
maximum values to determine an acceptable trace distance between the minimum and
maximum range.
Note
When specifying delay rules, you can use both types of delay rules within CES; however,
depending on your design requirements, you might use a single delay type exclusively.
Common Tasks
Matching Delay Rules Among Nets on page 167
To Specify Delay Rules for Nets
1. With the CES Spreadsheet Nets page active, fromthe Group pulldown, click Delays
and Lengths.
it easier to work with delay constraints when the CES Spreadsheet Nets page displays
only them.
2. In the row of the net for which you want to specify delay rules, use the available
constraint fields to define delay based on length or time of flight.
Note: When you want to include the length or time of flight of vias that are part of a net,
you can express those inclusions by entering larger values that approximate the
appropriate increases to the overall length or time.
Defining a Routing Tolerance for All Nets Within a
Constraint Class
Aside from defining general minimum and maximum delay constraints for nets within a
constraint class, you can also assign a tolerance to an entire constraint class through use of the
Length or TOF Delay Tol constraint. Doing so gives the router greater room to increase or
decrease the length of trace connections during routing operations. It is important to understand
that the tolerance is only displayed at the constraint-class level, but it is by default used by all
lower-level objects (e.g. sub-level constraint classes and electrical nets).
Child-level constraint classes within a parent constraint class use the defined tolerance of the
parent constraint class by default; however, you can define a tighter tolerance at the child-class
level. In the event that you want to specify a tighter tolerance at the net level, you can do so by
defining a match relationship and then specifying a tolerance for the matched group of nets. To
do so, please refer to Matching Delay Rules Among Nets on page 167.
Specifying Maximum Length as a Percentage Above
Manhattan Length
You can use a net's Manhattan length plus a fixed percentage to specify the value used for the
maximumlength constraint (Length or TOF Delay Max). Manhattan length is calculated in your
associated PCB layout tool. You can specify a length of Manhattan plus 1%or greater (e.g. 1%,
200%, 400%, or larger).
Note
Manhattan length values used in CES are not validated.
To Specify Maximum Length as Manhattan Length
In the Length or TOF Delay Max field, enter a value of 1 or more, and follow it with a
percentage symbol (%).
Example: To use a length that is 120%of the Manhattan length, enter 20%. To use a length that
is 500% of Manhattan length, enter 400%. To specify a length as close as possible to the
Manhattan length, enter 1%.
Net Delay Calculations
When you define a time of flight or length delay constraint for an entire net instead of a pin pair,
delay is calculated by combining the trace segment lengths between each pin in the net. When
the delay method is time of flight, each trace segment length is converted into corresponding
delay values based on trace length and the propagation velocity associated with the board layer
on which a trace segment is located. When the calculated length or time of flight delay is less
than the minimum constraint for the net, one of the trace segments is increased to satisfy the
specified minimum delay.
Note
For electrical nets, the physical length of any devices that join physical nets is included in
the length calculation when available.
In order for delay to be calculated, the following net requirements must be met:
Ground planes exist.
Trace is not touching or intersecting the plane or another trace.
Trace is not floating over the dielectric (i.e. trace doesn't touch dielectric).
Trace has width and height greater than 0.
Trace isn't very wide or very narrow.
Trace or trace/plane separations are exceedingly smaller.
Tip: To define maximum length as Manhattan length plus a fixed percentage, in the
Length or TOF Delay Max field, enter a value between 1 and 100, and follow it with a
percentage symbol (%). For example, entering 20%defines maximum length as 120%of
the Manhattan length.
Delay Value Default
When one or more of the above requirements is not met, a delay value based on the default
propagation velocity is used. This default value is 170 ps/inch (2.04 ns/ft).
Example of Specifying a Length Delay Rule for a Net Pin Pair
1. In the Type field of the pin pair for which you want to specify a length delay rule, click,
and then select Length.
2. In the Min field, enter a value for the minimum acceptable trace length between pins.
3. In the Max field, enter a value for the maximum acceptable trace length between pins.
Example: In the illustration below, the user chose a minimum value of 1000 th, and a
maximum value of 1500 th. Notice that this pin pair delay rule is a single instance that
does not have a match relationship or match tolerance associated with it.
Figure 7-4. Net Pin Pair With a Length Delay Rule
Matching Delay Rules Among Nets
By creating match groups, you can use the delay rules you define for a single net or pin pair as
the delay rule for multiple nets and/or pin pairs. You can also create match groups that do not
include minimum or maximum delay rules, but instead are matched only within a range. You
accomplish delay matching by setting up a match relationship, and optionally, a match
tolerance. The match feature of CES delay rule specification is especially useful when you want
to use the same time-of-flight or length delay range for bus nets, and similar design components
that lend themselves to rule reuse. When using match groups, all nets or pin pairs with the same
group identifier will be routed to the same length or delay within the tolerance.
Rules
Match group identifiers that include multiple characters must begin with an alphabetical
character. After which, you can use any combination of alphabetical and numerical
characters, and underscores.
A single match group can contain any combination of electrical nets, physical nets, and
pin pairs.
When you do not set a tolerance for the matched group, the default formula tolerance is
used.
To Define a Match Relationship
1. In the Match field of an electrical net, physical net, or pin pair row, enter a match
identifier (e.g. 1, a2, b_3).
2. Optionally, in the Tol field, specify a tolerance (i.e. delay range that design objects must
be within).
Example: To specify a tolerance of 100 th, type 100, and then press Enter. All design
objects that use this match relationship must be within 100 th of each other.
3. For each net for which you want to match this delay rule, in the Match field of each row,
type the match identifier (e.g. 1, a2, b_3) you specified in step 1, and then press Enter.
Example of Specifying a Matched Time of Flight Delay for Several Pin Pairs
1. In the Type field of the pin pair for which you want to specify a time of flight delay rule,
click, and then select TOF.
2. In the Min field, enter a value for the minimum acceptable time of flight between pins.
3. In the Max field, enter a value for the maximum acceptable time of flight between pins.
4. In the Match field, enter an alphanumeric identifier for this time of flight delay rule.
Optional: Enter a tolerance value.
5. In the Match field of the net pin pairs for which you want to use this time of flight delay
rule, type the match identifier you chose in step 4.
Example: In the illustration below, the user chose a minimumacceptable value of 40 ns,
and a maximumacceptable value of 80 ns. The match identifier is '1' and has a tolerance
value of 5 ns. The user assigned this time of flight delay rule to the three net pin pairs
below it by entering '1' in each Match field. This match relationship means that each of
the four pin pairs must have a time of flight between 40 ns and 80 ns, and their
respective values must be within 5 ns of each other (e.g. 60 ns, 61 ns, 63 ns, 64 ns).
Figure 7-5. Net Pin Pair With a Time-Of-Flight Delay Rule
Example of Matching Length Delay Only by Tolerance
In this example, you are not concerned with the minimumand maximumlength values to which
several nets will be matched, just the tolerance of the match group. As you can see in the
illustration below, the length of each net must be within 50 th of each other.
Figure 7-6. Matching by Just Tolerance
Related Topics
Defining Pin Pairs for Nets on page 161
Matching Delay Tolerance at the Constraint Class Level
In addition to matching delay rules among nets, you can also match delay tolerance based on
constraint classes and their hierarchy. Doing so gives you the ability to easily ensure that all nets
within a constraint class end up with delay values that do not exceed a specific tolerance.
Furthermore, when you have parent constraint classes that include child constraint classes, or
even more extensive hierarchy, you can define a tolerance at each level. For example, at the
parent constraint class level, you might define a tolerance of 50 th, while at a child constraint
class level a tolerance of 25 th.
Defining Formulas to Create Net Relationships
Prerequisites
You must have one or more constraint classes and nets assigned to constraint classes.
Procedure
1. From the CES Spreadsheet Nets page, in the Length or TOF Delay Tol cell of the
constraint class of interest, enter a tolerance value.
Note: Length or TOF Delay Tol cells are always editable for constraint classes. Unlike
net rows, you do not need to define a value in a Match cell in order to make a Tol cell
accessible.
2. Optionally, when there are sub-level/child constraint classes for which you want to
define tighter tolerances, enter a value in the associated Length or TOF Delay Tol cell.
The tolerance value for a child constraint class must be smaller than that of the parent or
child constraint class above it.
Results
The tolerance values will now be used during routing.
You can define formulas to create relationships between nets, pin pairs, or differential pairs. By
doing so, you can set up delay relationships among similar design objects that would benefit
from such associations. For example, you can set one pin pair delay to equal the delay of
another (=), specify that the delay of one net must be greater than or less than the delay of
another (> or <), add or subtract the delay of one pin pair to or from the delay of another. You
can also include constants and variables to define net and pin pair delay with even more detail.
Common Tasks
Including Tolerance on page 171
Entering Multiple Formulas on page 171
Solving Formulas to Check for Errors on page 172
To Define a Formula
1. From the CES Spreadsheet Nets page, in the Formulas Formula cell of the net, pin pair,
or differential pair net for which you want to define a formula, construct a formula using
available constants, variables, and accepted operators (=, >, <, +, -). Refer to the
following examples, which show common formula applications:
A+3 Delay equals constant A plus 3 units
B-2 Delay equals constant B minus 2 units
> Delay must be greater than another delay value
< Delay must be less than another delay value
= Delay must be equal to another delay value
Rule: Formulas assume ns unit of measure. When you are working with a different unit
of measure (e.g. th), you must include it after the hardcoded value (e.g. 1000th).
2. After you enter an operator that requires a reference object (=, >, <), click the name cell
of the electrical net, physical net, differential-pair net, or other object that you want to
use as the reference. You can also type the object name, but clicking is recommended
because it is far more accurate and efficient when you have the option to do so.
Rule: The reference object must be same type as the object for which you are defining
the formula. For example, when you define a formula for a net, the reference object must
also be a net.
Note: CES distinguishes between electrical and physical nets that you include in
formulas by encasing them with bracket symbols or pipe symbols (e.g. {\<electrical net
name\} or |\<physical net name>\|).
Note: When including virtual pins, they must appear in the form \VP#\-\VP#\. For
example, to include virtual pin number 12, enter the following: \VP12\-\VP12\
Including Tolerance
You can include tolerance in your formulas to introduce a range around a formula value. For
example, when you require length delay for several nets to be larger than 3000 th, but a
tolerance of 100 th is acceptable (i.e. minimum value can be 2900 th), you can include the
tolerance in your formula.
To Include a Tolerance
At the end of the formula, enter +/-, the tolerance, and then the unit of measure.
Example: =2000th+/-100th specifies that the length delay can be between 1900th and 2100th.
Entering Multiple Formulas
When you want to define two or more formulas for a net or pin pair, you must separate formulas
with the # character and include the net, pin pair, or differential pair name in each formula that
appears after the initial formula. For example, when you want to set the delay constraint of a pin
pair (e.g. \U1\-\3\@\U2\-\3\) to be equal to a pre-defined constant (e.g. A) and less then a
specific value (e.g. 800 th), the correct cell notation is =A#\U1\-\3\@\U2\-\3\<800th where the
# symbol defines an AND relationship between formula one (i.e. =A) and formula two (i.e.
\U1\-\3\@\U2\-\3\<800th).
Note
When entering multiple formulas, the net, pin pair, or differential pair name must
immediately follow the # symbol. When you type the # symbol, CES automatically adds
the name. In the event that it does not, to quickly and accurately add an object name to a
formula, click its name cell.
Solving Formulas to Check for Errors
After you define formulas, you can check themfor errors by solving all formulas in your design.
When you do so, CES attempts to compute net and pin pair delay values based upon the
formulas that you have entered. After it is finished, you are notified of any formulas that contain
syntactic or semantic errors through the log file. In addition, cells that contain erroneous
formulas are also highlighted to make them easier to find.
To Solve Formulas
With CES Spreadsheet Nets page active, from the Pairs toolbar, click .
Alternative: With the CES Spreadsheet Nets page active, from the Data menu, click Solve All
Formulas.
Example of Matching Length Delay Within a Bus and Between Busses
In this example, you want to match the length delay for 8 pin pairs that comprise a bus with a
tolerance of +/- 1.27 mm. In addition, you want to match the length delay of this bus between
specific external bus pin pairs with a tolerance of +/- 12.7 mm.
To Construct This Formula
1. Create two variables. One for within bus (e.g. withinbus) matching and the other for
between bus (e.g. betweenbusses) matching.
2. In the Formulas Formula cell of the first pin pair, enter =withinbus+/-1.27mm#<pin pair
name>=betweenbusses+/-12.7mm
Rule: CES automatically adds the pin pair name after you press #.
Example: When the pair name is C1\-\1\@\C1\-\5\, the formula would be =withinbus+/-
1.27mm#C1\-\1\@\C1\-\5\=betweenbusses+/-12.7mm
3. For the seven remaining pin pairs, enter this formula in the Formulas Formula cell.
4. For each external pin pair that you want to match between the pin pairs of this bus,
include =betweenbusses+/-12.7mm in the Formulas Formula cell.
Example: When a pin pair already includes its own length formula (e.g. >50mm),
append it to the end (i.e. >50mm#<pin pair name>=betweenbusses+/-12.7mm). This
formula requires that the pin pair length delay be greater than 50 millimeters AND
Creating Constants and Variables for Delay Rules and Formulas
match the betweenbusses value calculated during routing. The tolerance of the final
value can be +/- 12.7 millimeters.
Creating Constants and Variables for Delay
Rules and Formulas
You can create constants and variables to use when defining length and delay formulas within
the CES Spreadsheet in the Formulas Formula field. Creation and application of constants and
variables is a way to provide delay rule consistency across multiple nets or pin pairs within a
design. After you create constants or variables, you can delete specific entries that you no longer
need. You can also find variable references to view net or pin pair formulas that include
variables.
Using Free Variables to Constrain Delay by Group Only
Unlike constants, you never associate a pre-defined value with a variable, nor do you set a
variable to a specific value within the Formulas Formula cell of a net, pin pair, or differential
pair row. Variables, also known as free variables, give you the ability to constrain delay of
several objects by group, with no regard for the delay value that is produced automatically, or
manually during routing. For example, when you want the length delay of 16 nets that comprise
a bus to route to the same length, but you do not care what the length is, you can set each net
equal to this free variable (e.g. =samelength) and allow the router to determine the length to
which to match each net.
To Create Constants and Variables
1. With the CES Spreadsheet Nets page active, from the Edit menu, click Variables, and
then click Edit.
2. From the Variable List dialog box, make sure that the tab that corresponds to the data
type you want to create is selected (i.e. Constants or Variables), and then click .
3. In the Name field, enter a name for the new constant or variable.
Rule: Constant and variable names can contain alphabetic characters (a - z) and
numerals (0 - 9). They cannot contain only numerical characters.
4. When defining a constant, in the Value field, enter a value for the new constant.
5. After you finish creating constants and variables, click OK.
To Delete Specific Constants or Variables
then click Edit.
Specifying Simulated Delay Rules for Nets
2. Fromthe Variable List dialog box, use the tabs at the bottomto view available constants
or variables.
3. Click the constant or variable row you want to delete, and then click .
Tip: To select multiple constants or variables, use Ctrl-Click.
4. After you finish deleting constants and variables, click OK.
To Find Variable References
then click Find Variables References.
2. From the Variables Reference dialog box, perform one of the following tasks:
To expand or collapse the listing of nets or pin pairs for a variable, click the +/-
button
To select a net or pin pair within the CES Spreadsheet, double-click a specific net or
pin pair
Related Topics
Defining Formulas to Create Net Relationships on page 170
You can specify simulated delay rules to constrain the edge rates of individual electrical nets or
constraint classes by time. When using ICX Pro Verify in conjunction with CES, you can
accurately simulate actual values for these constraints to determine how closely they match.
ICX Pro Verify gives you the ability to test these constraints with multiple simulators, and
simulation settings, which makes it easy to verify sets of unique electrical requirements, corner
cases, and extreme corner cases.
Note
In order to use these constraints, you must have an Electrical CES license. In order to
calculate actual values for these constraints, you must be using ICX Pro Verify within
your design flow.
Common Tasks
Matching Simulated Delay Rules Among Nets or Constraint Classes on page 176
When constraining delay through simulation, you can choose to constrain one or more signal-
edge properties with unique or identical minimum and maximum delay values. You can also
specify the maximum acceptable range between the actual values produced by simulation of
these minimums and maximums. When you are constraining based on range, but not actual
values, use Simulated Delay Max Range without defining minimum and maximum simulated
delay values to design source-synchronous busses where the absolute delay is not important, but
limiting the skew between bus nets is critical.
Unlike the constraints in the Delays and Lengths group of the CES Spreadsheet Nets page,
which you use to define the total delay for a net, simulated delay constraints control the
switching times between signal states. These states are formally referred to as the edge rates of a
signal, which are the following types:
Rising edge The amount of time it takes the signal to switch between low and high
signal states (i.e. off to on).
Falling edge The amount of time it takes the signal to switch between high and low
signal states (i.e. on to off).
Signal Edge Rates and Crosstalk
Constraining edge rates is a crucial component of signal integrity. It is directly related to
crosstalk. The speed of transition as a signal switches between its low and high states causes a
spike in interference energy from the switching net (i.e. aggressor) to others net in its vicinity
(i.e. victims). The faster a signal switches, the more interference energy it produces. Although
you can space parallel trace segments to account for strong EMI fields generated by fast edge
rates, slowing down edge rates is the best solution when adding extra trace length is not an
option.
To Specify Simulated Delay Rules for Nets
1. With the CES Spreadsheet Nets page active, from the Group pulldown, click
Simulated Delays.
it easier to work with simulated delay constraints when the CES Spreadsheet Nets page
displays only them.
2. In the row of the net or constraint class for which you want to specify simulated delay
rules, click within the Simulation Settings cell, click the dropdown, and then select a
simulation template.
3. In the Simulation Stimulus cell, click the dropdown, and then select a simulation
stimulus.
4. Click within the Simulated Delay Edge cell to select the signal edge to constrain.
5. In the Simulated Delay Min and Simulated Delay Max cells, enter the target minimum
and maximum delays.
Rule: When the Simulated Delay Edge is set to Rise:Fall, enter unique minimum and
maximum delays by separating them with a colon (:).
6. Optionally, to specify a maximum range between the actual values produced for
Simulated Delay Min and Simulated Delay Max, in the Simulated Delay Max Range
cell, enter a value.
Note: Specify unique Rise:Fall values with a colon (e.g. 20:30).
Matching Simulated Delay Rules Among Nets or
Constraint Classes
You can match the simulated delay constraints of a net or constraint class to use the same values
for another net or constraint class. When matching simulated delay values between a constraint
class and a net, the mean of the delay range for nets in the constraint class is used as the
matching simulated delay.
When matching simulated delay rules, the electrical net or constraint class to which you are
matching does not need to include defined constraints for Simulated Delay Min, Simulated
Delay Max, or Simulated Delay Max Range. By keeping these constraints undefined you can
specify edge rate commonality between multiple nets without constraining the common edge
rate to a specific value.
To Match Simulated Delay Among Nets
1. Fromthe CES Spreadsheet Nets page, in the row of the net, differential pair, pin pair, or
constraint class for which you want to match simulated delay values, in its Simulated
Delay Match To cell, click to select the hierarchical level to which to match.
2. In the Simulated Delay Match cell, click .
3. From the Simulated Delay Match dialog box, click an appropriate hierarchical object,
and then click OK.
Result: The Simulated Delay Match cell now displays this design object, and the
Simulated Delay Offset and Tol constraints are accessible.
4. Optionally, specify an offset and/or tolerance.
Example: When matching Simulated Minimum Delay of 200 ns, entering an offset of -
50 and a tolerance of 10 means that Simulated Delay Actual Match Min must be
between 140 ns and 160 ns (i.e. 200 ns -50 ns = 150 ns +/-10).
Example of Matching Simulated Delay Between Two Nets Without Defining
Specific Delay Values
In this example, you want to match both the rising and falling edges of two electrical nets, but
you are not interested in specifying appropriate minimum and maximum delay values, or the
maximumrange between these values. Your concern is that the signal edges of these nets match
within a certain tolerance. The specific delay values are not of concern.
Defining Overshoot and Ringback Constraints
To Set Up This Simulated Delay Match Relationship
1. Fromthe CES Spreadsheet Nets page, in the row of the electrical net you want the other
net to match, click within the Simulated Delay Edge cell, and then click Both.
2. Make sure that the Simulated Delay Min, Max, and Max Range cells are empty.
3. In the row of the electrical net you want to match to another net, in the Simulated Delay
Match To cell, click to select Net.
4. In the Simulated Delay Match cell, click .
5. From the Simulated Delay Match dialog box, click the electrical net you used in step 1,
and then click OK.
6. In the Simulated Delay Tol cell that is now accessible, enter a tolerance.
Example: In the illustration below, electrical nets DATA1 and DATA2 are matched.
DATA2 includes a tolerance of +/-10 for all actual values that are produced during ICX
Pro Verify simulation.
Figure 7-7. Simulated Delay Matching Between DATA1 and DATA2
You can define overshoot and ringback constraints to specify voltage requirements that
maintain component operability and signal integrity. The four overshoot constraints define the
high point, low point, extreme high point, and extreme low point voltage thresholds that the
specific logic components (e.g. microprocessors) of a net can handle. Unlike logic thresholds,
which dictate the voltage levels needed to switch a component between logic states, voltage
thresholds are maximums and minimums that must be adhered in order to maintain operability.
Because of the small size and delicate nature of electronic components, too little or too much
voltage can cause irreversible damage, rendering them useless. In the illustration below, you
can see that logic thresholds are between the overshoot thresholds, with dynamic thresholds
encapsulating both logic and static thresholds.
Figure 7-8. Static and Dynamic Overshoot in Relation to Logic Thresholds
Ringback constraints, which are not depicted in the above illustration, give you the ability to
define the amount of ringback voltage a net can sustain while in its logic high or logic low state.
Too much ringback, also called feedback, can cause a component to haphazardly switch
between logic states. This is why it is important to define the maximum acceptable amount of
ringback energy individually for each logic state.
Note
Overshoot constraints must be rail-relative (rr) where rr = VLmin abs for low and rr =
abs VHmax for high.
Other Common Tasks
Understanding Static and Dynamic Overshoot on page 179
Note
In order to use these constraints, you must have an Electrical CES license. In order to
calculate actual values for these constraints, you must be using ICX Pro Verify within
your design flow.
To Define Overshoot and Ringback Constraints
1. With the CES Spreadsheet Nets page active, from the Group pulldown, click
Overshoot/Ringback.
it easier to work with simulated delay constraints when the CES Spreadsheet Nets page
displays only them.
2. In the row of the net or constraint class for which you want to specify overshoot and
ringback constraints, click within the Simulation Settings cell, click the dropdown, and
then select a simulation template.
3. In the Simulation Stimulus cell, click the dropdown, and then select a simulation
stimulus.
4. In the Static Low Overshoot Max and Static High Overshoot Max cells, enter minimum
and maximum operating voltages.
5. Optionally, in the Dynamic Low Overshoot Max and Dynamic High Overshoot Max
cells, enter a lower minimum and higher maximum operating voltage, followed by a :
character and the duration of time each voltage can be sustained before CES should
report an error.
Example: To define a Dynamic High Overshoot Max constraint of 6 volts for 3
nanoseconds, enter 6:3.
6. In the Ringback High Max and Ringback Low Max cells, enter the maximumamount of
ringback voltage that is acceptable for high and low signal states.
7. In the Monotonic Edge cell, use the dropdown to specify whether transitions between
signal states must be monotonic for the rising edge, falling edge, or both edges.
Understanding Static and Dynamic Overshoot
Static and dynamic overshoot are two distinct types of overshoot that are often times confused
with each other. Static overshoot is unidimensional. The high and low values you use will
maintain component operability for an infinite duration. Dynamic overshoot is bidimensional.
Each extended high or low value is accompanied by a precise duration. Specification of this
duration is what makes dynamic overshoot possible. Although these durations are usually
extremely short, sometimes they are the key to solving design problems.
Tip: To learn more about each overshoot constraint, please refer to the CES Constraint
Reference (appendix chapter A).
Example of Defining Dynamic Overshoot Constraints With a 5 ns Limit
In this example, you have already assigned static overshoot constraints to a net. Static Low
Overshoot Max is set to .5, and Static High Overshoot Max is set to 5. Now, you want to define
the net's dynamic overshoot constraints and apply a duration of 5 nanoseconds to both Dynamic
Low Overshoot Max and Dynamic High Overshoot Max. The 5 ns value means that CES will
not report an error as long as the overshoot value is not met or exceeded for a continuous time-
period greater than 5 ns. The dynamic overshoot constraints you will define here are 1 and 5.5.
To Define These Overshoot Constraints
1. In the Dynamic Low Overshoot Max cell, enter 1:5, and then press Enter.
2. In the Dynamic High Overshoot Max cell, enter 5.5:5, and then press Enter.
Result: The net now has a fully-defined set of static and dynamic overshoot constraints.
In the illustration below, you can see that both dynamic overshoot constraints are
applicable for a duration of no more than 5 ns.
Modifying I/O Designer FPGA Constraints
Figure 7-9. Dynamic Overshoots With a 5 ns Duration Limit
Modifying I/O Designer FPGA Constraints
You can modify I/O Designer field-programmable gate array (FPGA) constraints to define
technology standards, and control timing between components of FPGA signal nets. Within I/O
Designer, these FPGA constraints are accessible from the Timings list tabs. For example, I/O
Designer Setup/Hold Timing corresponds to the Pad to Setup Constraints tab.
Because FPGA constraints are synchronized between front-end CES and I/O Designer,
modifications in either tool will result in an update across your schematic-capture design flow.
When you want to update these constraints across your entire design flow, you can do so with
standard forward-annotation processes. For more information about these constraints, please
refer to the following constraint reference topics:
I/O Designer I/O Standard on page 342
Note
To Modify I/O Designer FPGA Constraints
1. With the CES Spreadsheet Nets page active, from the Group pulldown, click I/O
Designer.
Note: Because most I/O Designer constraints are defined by pin or pin pairs, make sure
that Filters > Levels > Pins and Pin Pairs are enabled.
2. In the row of the net, constraint class, pin, or pin pair for which you want to modify an
I/O Designer constraint, enter a value.
Updating FPGA Constraints Between Tools
After you make constraint changes in front-end CES or I/O Designer, you must update
constraint values between these tools in order to synchronize the changes and make themappear
in both environments.
Defining Constraints for Single-Pin Nets
To Update I/O Designer With CES Changes
1. Close CES.
2. In the invocation of the front-end application from which you launched CES, save your
design changes.
3. From the I/O Designer Generate menu, click Synchronize.
4. From the Synchronization wizard, locate the row for which the Name field lists the
proper .ucf file and the Description field lists Constraints file.
5. Click within the Action column, select , and then click Next.
See also: To learn more about using I/O Designer, please refer to the I/O Designer
User's Manual. It is accessible through the Help > Contents menu selection of I/O
Designer.
To Update CES With I/O Designer Changes
From the I/O Designer Generate menu, click Save Changes to CES Database.
To Update I/O Designer Constraints Between Schematic Capture and PCB
Layout
After you synchronize front-end CES and I/O Designer using one of the above procedures, run
forward annotation to update these constraints in your PCB-layout environment, which includes
back-end CES.
You can define a subset of constraint values for single-pin nets, which are also commonly
referred to as Net0 nets. The constraints you can define are located on the CES Spreadsheets
Nets page. Constraints cell that you can not define are grayed out and not editable. In addition to
defining constraint values for Net0 nets, you can also assign this grouping of nets to a constraint
class and net class. Including them in a specific net class gives you the ability to define
clearances.
Within CES, all single-pin nets have one entry. Therefore, you define rules for all Net0 nets as a
group. Incidentally, all single-pin nets will be part of the same constraint class and net class.
Whether you have two hundred single-pin nets, or just 2, CES refers to them as (Net0)-1:X.
Prerequisites
Your design must contain at least 1 single-pin net.
Procedure
1. From the CES Spreadsheet Nets page, locate the following net row: (Net0)-1:X
2. Modify the subset of constraint cells that are available to (Net0)-1:X for definition.
Available constraints are modifiable, and not displayed as blank or read-only.
Results
The constraint changes you have made to (Net0)-1:X now apply to the entire grouping of single-
pin nets.
Chapter 8
Parallelism and Crosstalk Rule Creation
This section covers parallelism and crosstalk rule creation. Some of the topics include
determining when to use parallelism and crosstalk rules, defining parallelism rules for stack-up
layers, and assigning parallelism rules to nets and constraint classes. This section also provides
information about definition of crosstalk rules for nets and constraint classes. Please refer to the
table of contents for the full listing of topics included in this section.
Determining When to Use Parallelism or
Crosstalk Rules
Before you define crosstalk rules for nets or constraint classes, or parallelism rules for stack-up
layers and then assign them to nets or constraint classes, you should have an understanding of
how parallelism and crosstalk rules differ to determine which rule type you want to use with
your design:
Crosstalk rules give you the ability to specify the maximum amount of acceptable
interference energy (mV) for specific nets and constraint classes. Accordingly, the
hazard system displays violations that it encounters. Each crosstalk rule that you create
consists of two nets or constraint classes. The first object is the victim, and the second
object is the aggressor.
Parallelism rules give you the ability to define pairings of net properties that specify
acceptable distances and parallelism run lengths between specific nets and net classes.
When Hazards identifies a distance/length pairing that has been breached, it resolves
such violations. In addition, for same layer parallelism rules, the router uses these rules
to avoid creating violations altogether.
Other Common Tasks
Choosing Between Noise Rule Types for AutoActive on page 184
Rule Precedence
Although you can assign both parallelism and crosstalk rules to the same nets or constraint
classes, parallelism rules take precedence. When both are used, the router ignores the crosstalk
rules during Tune Xtalk routing passes. Hazards will show both crosstalk and parallelism
hazard information.
Defining Parallelism Rules for Stack-Up Layers
Parallelism Rules Hierarchy
When you assign multiple parallelism rules between nets, CES uses the rule with the lowest
level of hierarchy. For example, you assign parallelismrule PR1 to Net A and Net B. These nets
are grouped into separate constraint classes. When you assign a different parallelism rule (e.g.
PR2) between these two constraint classes, Net A and Net B will use the net-to-net parallelism
rule instead of the class-to-class rule.
The hierarchy CES uses to determine parallelism-rule usage obeys the following order:
1. Class to (All Classes)
2. Class to class
3. Net to (All Nets)
4. Net to net
Choosing Between Noise Rule Types for AutoActive
When you define a parallelism rule and a crosstalk rule for a net-to-net or class-to-class
relationship, you can specify which noise rule type is used during auto routing.
To Select a Noise Rule Type
From the CES Spreadsheet Noise Rules page, click the Crosstalk Auto Route Usage cell, and
then select Crosstalk or Parallelism.
Related Constraints
Crosstalk Auto Route Usage on page 372
Related Topics
Assigning Parallelism Rules to Nets and Constraint Classes on page 186
Defining Crosstalk Rules for Nets and Constraint Classes on page 188
You can create rules that define parallelismfor net segments that are on the same layer, adjacent
layers, or both. When you do so, you specify a combination of edge-to-edge spacing between
segments and the maximum length that segments can run in parallel without violation. By
defining parallelism rules, you can help control the amount of crosstalk by restricting excessive
segment parallelism. Before defining parallelism rules, you should have an understanding of
when to use parallelism and crosstalk rules.
When defining parallelism rules, you can create as many edge-to-edge and maximum length
combinations as you require. For example, a parallelismrule that contains two edge-to-edge and
maximum length combinations for net segments on the same layer might specify that segments
with an edge-to-edge spacing of 10 th can run parallel for no more than 2000 th, while those
with an edge-to-edge spacing of 8 th can run parallel for no more than 1500 th.
Parallelism Rule Definition Methodologies
Depending on your design practices, you may define parallelism rules all at once, individually,
or as a mixture of these two methodologies as you work with the nets in a design. When
defining multiple rules, the method of parallelismrule creation explained in this topic gives you
the ability to quickly define multiple rules, making it best suited for this purpose. When defining
or refining individual rules, you can use the CES Spreadsheet Noise Rules page.
To Define Parallelism Rules
1. With the CES Spreadsheet Noise Rules page active, from the Pairs toolbar, click .
Alternative: From the Edit menu, click Parallelism Rules, and then click Define
Parallelism Rules.
2. Fromthe ParallelismRules tab, next to the Parallelismrules heading, click , and then
change the default name of the new rule (New) to a meaningful title.
3. Define an edge-to-edge spacing and maximum length combination for each same layer
or adjacent layer segment rule you want this parallelism rule set to include by
performing one of the following tasks:
To define a same layer segment rule, next to the Same layer segments heading, click
, and then enter an Edge / Edge value and a Max Parallel Len value.
To define an adjacent layer segment rule, next to the Adjacent layer segments
heading, click , and then enter an Edge / Edge value and a Max Parallel Len value.
4. After you finish entering edge-to-edge and maximum length combinations, click Apply.
Rule: The maximum length value associated with an edge-to-edge value cannot be
greater than the maximum length value associated with a larger edge-to-edge value. For
example, after you define an edge-to-edge and maximum length combination of 10 th
and 1200 th, an edge-to-edge value of 8 th must be accompanied by a maximum length
value that is less than the maximum length value of the previous set (i.e. 1200 th).
Note: When you enter incorrect values, the cell background is changed to red and the
data in the cell is not saved until you correct the value.
Related Topics
Determining When to Use Parallelism or Crosstalk Rules on page 183
Assigning Parallelism Rules to Nets and Constraint Classes
Assigning Parallelism Rules to Nets and
Constraint Classes
After you define parallelism rules, you can apply them to specific pairs of nets and constraint
classes by creating net-to-net or class-to-class parallelism rule assignments. Each parallelism
rule assignment includes two specific nets or constraint classes, and the parallelism rule to
which they must adhere. In addition, you can also apply all parallelism rules that you have
created to the nets or constraint classes that comprise a parallelism rule assignment.
Tip: It is important not to confuse constraint classes and net classes for the purpose of
parallelism rule assignments. Net classes are used to create board layer and
physical/manufacturing rules. You use constraint classes to define net constraints and
relationships between nets.
Common Tasks
Navigating to Assigned Parallelism Rules From the Nets Page on page 188
To Assign Parallelism Rules to Nets or Constraint Classes
Alternative: From the CES Spreadsheet Noise Rules page, click , and then modify
the Noise Type, Constraint Class or Electrical Net Name Victim and Aggressor, and
Parallelism Rule fields using the appropriate field selector. For example, because Class-
Class is the default parallelism type, when assigning a net-to-net parallelism rule, click
to change this field to Net-Net. When assigning parallelism rules using the Assign
Parallelism Rules dialog box, you can access it from the Edit menu by clicking
Parallelism Rules, and then clicking Assign Parallelism Rules.
2. Fromthe Assign ParallelismRules dialog box, In the Noise rule type field, specify a net-
to-net or class-to-class assignment.
3. Fromthe list of available electrical nets or constraint classes, select the nets or constraint
classes that will comprise the first half of the pairing (i.e. reference nets or classes), and
then next to the Victim constraint class(es) or Victim electrical net(s) box, click .
Tip: To select multiple nets or constraint classes, you can use Ctrl-click, Shift-click, or
click-drag. To select nets or constraint classes by name, in the field below the list of
source nets or net classes, enter a search string, and then click .
4. From the list of nets or constraint classes, select the nets or constraint classes that will
comprise the second half of the pairing (i.e. apply rules to nets or constraint classes), and
then next to the Aggressor constraint class(es) or Aggressor electrical net(s) box, click .
Note: When assigning a parallelism rule to constraint classes, you can quickly set the
Aggressor constraint class(es) to include all constraint classes or all other constraint
Assigning Parallelism Rules to Nets and Constraint Classes
classes (excluding those nets in Victim constraint class(es)). To select all constraint
classes, click the (All) row. To select all other constraint classes, click the (All Classes)
row.
Tip: When you want to check for same net or same constraint class parallelism, select
the nets or constraint classes you chose in step 3.
5. In the Parallelism rule box, select a specific parallelism rule, and then click Apply.
Crosstalk: You can also define a maximum crosstalk value for these pairings of
electrical nets or constraint classes. To do so, in the Max crosstalk box, enter the
maximumamount of crosstalk that the victimnets or constraint classes can receive from
the aggressor nets or constraint classes.
Tip: Before clicking Apply, make sure that the lists of nets or constraint classes is
accurate. To remove any nets or constraint classes from either list, click to select them,
and then click the corresponding .
To View Detailed Parallelism Rule Information During Assignment
2. From the Assign Parallelism Rules dialog box, to the right of the Parallelism rule
dropdown, click .
Result: The Parallelism Rules tab is displayed.
Example of Assigning a Parallelism Rule Between a Single Constraint Class
and All Other Constraint Classes
In this example, you want to assign a parallelism rule between nets in a single constraint class
with nets in all other constraint classes. The parallelism rules includes both same-layer and
adjacent-layer segment edge-to-edge and maximum parallelism rule lengths. The nets in the
single constraint class are critical nets with strict net parallelism requirements.
To Assign a Parallelism Rule Between a Single Constraint Class and All
Other Constraint Classes
1. From the Assign Parallelism Rules dialog box, in the Noise rule type field, make sure
Class to Class is selected.
2. From the list of Available constraint class(es), select the single constraint class to
associate with all other constraint classes, and then next to the Victim constraint
class(es) list, click .
3. Fromthe list of Available constraint class(es), select the (All Classes) row, and then next
to the Aggressor constraint class(es) list, click .
4. In the Parallelism rule box, click the dropdown, and then select the parallelism rule to
assign between the single constraint class and all other constraint classes, and then click
Defining Crosstalk Rules for Nets and Constraint Classes
OK. In the illustration below the Noise Rules spreadsheet shows that parallelism rule
G10L100/G15L150 is assigned between constraint class HT_CONN_IN and all other
constraint classes.
Figure 8-1. Single Constraint Class and All Other Constraint Classes
Parallelism Rule Assignment
Navigating to Assigned Parallelism Rules From the Nets
Page
As you work with the CES Spreadsheet Nets page to define constraints for individual nets and
constraint classes, you can quickly navigate to the parallelism rules assigned to a net or
constraint class. By doing so, you can easily and accurately determine any parallelism-rule
assignments for a design object.
To Navigate to Assigned Parallelism Rules
From the CES Spreadsheet Nets page, right-click a net or constraint class, and then click
Navigate to Parallelism Rule.
Result: The Noise Rules page becomes active, and any parallelism rules assigned to the design
object are highlighted.
Related Topics
Defining Parallelism Rules for Stack-Up Layers on page 184
Defining Crosstalk Rules for Nets and Constraint
Classes
You can define crosstalk rules for pairs of nets and constraint classes to specify the maximum
crosstalk value for nets and constraint classes as part of an aggressor-victimrelationship. Before
applying crosstalk rules to specific nets or constraint classes, you should have an understanding
of when to use parallelism and crosstalk rules.
When you define a maximum crosstalk value, you can also specify the victim net's signal state
(e.g. Low, High) that is most susceptible to crosstalk. Because crosstalk is a complicated matter
that presents unique challenges based upon signal state, you can define multiple crosstalk rules
to specify constraints for aggressor-victimnet and constraint class pairs. For example, when Net
B is in a low state, you can restrict the maximum crosstalk from Net A to 10 mV. However,
when Net B is in a high state, you can require that the maximum crosstalk from Net A is no
more than 5 mV.
Note
Although you can assign both parallelism and crosstalk rules to the same nets or
constraint classes, parallelism rules take precedence. When both are used, the router
ignores the crosstalk rules during Tune Xtalk routing passes. Hazards will show both
crosstalk and parallelism hazard information.
To Define Crosstalk Rules for a Net or Constraint Class
1. With the CES Spreadsheet Noise Rules page active, from the Main toolbar, click .
2. In the Noise Type cell, click to specify whether the aggressor-victim relationship is Net-
to-Net or Class-to-Class (i.e. constraint class).
3. In the Constraint Class Or Electrical Net Name Victim field, click the browse button,
select the victim net or constraint class, and then click OK.
4. In the Constraint Class or Electrical Net Name Aggressor field, click the browse button,
select the aggressor net or constraint class, and then click OK.
5. In the Crosstalk Max cell, enter the maximum amount of crosstalk the victim net or
constraint class can receive from the aggressor.
6. Optionally, in the Crosstalk Level cell, click to select the signal state or states of the
victim net or constraint class using the following guidelines:
High The victimnet is on (i.e. in its high state). The voltage level is at or above the
high threshold (e.g. 5.1 V).
Low The victim net is off (i.e. in its low state). The voltage level is at or below the
low threshold (e.g. 0.9 V).
Tristate The victim net is off, but a small voltage still flows from the receiver to
ground (e.g. 0.5 V).
Result: The Crosstalk Max value is now the constraint for a specific net-to-net
relationship, or for all victimnets in a constraint class when receiving crosstalk fromthe
aggressor nets in another constraint class.
Example of Defining Two Nets as Both Aggressors and Victims
In this example, you want to define two net-to-net crosstalk relationships to specify how Net A
and Net B should be constrained when each net is an aggressor or victim of the other. In this
case when Net A is the aggressor of victim Net B, the maximum crosstalk value Net B can
receive from Net A is 5 mV. Conversely, when Net B is the aggressor of victim Net A, the
maximum crosstalk value Net A can receive from Net B is 10 mV. In addition, both victim nets
must meet this constraint during all signal states.
To Define Two Nets As Both Aggressors and Victims
1. From the CES Spreadsheet Noise Rules page, click , and then in the Noise Type cell,
click Net-to-Net.
2. In the Constraint Class Or Electrical Net Name Victim field, click the browse button,
select Net A, and then click OK.
3. In the Constraint Class or Electrical Net Name Aggressor field, click the browse button,
select Net B, and then click OK.
4. In the Crosstalk Max cell, enter 10. In the Level cell, click to select All.
5. Repeat steps 1 through 4, and this time specify Net B as the victim net, Net A as the
aggressor net, and a Crosstalk Max value of 5.
Example: In the following illustration, net MICROAD4 can be susceptible to 10 mV of
crosstalk from net 50M_CLK. Conversely, when the aggressor-victim role is reversed,
net 50M_CLK can receive no more than 5 mV of crosstalk from net MICROAD4.
Figure 8-2. MICROAD4 and 50M_CLK Are Defined As Both Aggressor and
Victim Nets
Related Topics
Determining When to Use Parallelism or Crosstalk Rules on page 183
Chapter 9
Differential-Pair Net and Rule Definition
This section covers differential-pair net and rule definition. Some of the topics included are
manual definition of differential pairs, and automatic definition of differential pairs. This
section also provides information about assigning rules to differential pairs. Please refer to the
Note
When any previously defined differential pairs now include a push pin next to them,
please refer to Differential Pairs Conversion on page 49.
Defining Differential Pairs Manually
You can manually define differential pair nets by selecting the two electrical nets ( ) to define
as the differential pair. After you define a differential pair net, the CES Spreadsheet Nets page is
updated to include the designation.
When you can match differential pair nets by net name, you should consider creating
differential pair nets automatically. By doing so, you can create differential pair nets more
efficiently.
Note
Nets that you define as differential pairs must be part of the same net class and the nets
must also be electrical nets.
To Define Differential Pairs Manually
1. From the CES Spreadsheet Nets page, use Ctrl-click to select two electrical nets ( ),
and then from the Pairs toolbar, click .
Alternative: After you select two electrical nets, right-click either net, and then click
Create Diff Pair; or, from the Edit menu, click Diff Pairs, and then click Diff Pair
from Selected Nets.
2. Optionally, to give the differential pair a unique name instead of its system-defined
name, right-click the differential-pair cell, and then click Rename. Now that the cell is
editable, type a new name, and then press Enter.
Defining Differential Pairs Automatically
To Delete a Differential-Pair Net Designation
Fromthe CES Spreadsheet Nets page, click a differential pair row ( ), and then fromthe Main
toolbar, click . To select multiple rows for simultaneous deletion, use Ctrl-click and Shift-
click.
Example of Defining a Differential-Pair Net Manually
1. Fromthe CES Spreadsheet Nets page, use Ctrl-click to select the two electrical nets ( )
that will comprise the differential pair.
Rule: The two electrical nets you select can be part of the same constraint class or part
of a different constraint class; however, each electrical net must be part of the same net
class. If you have not defined net classes and assigned appropriate nets to each class,
each net is currently part of the (Default) net class and will not violate differential-pair
net creation requirements.
2. From the Pairs toolbar, click .
Result: The differential-pair net is created. The Nets page is updated to include the
differential pair net. A differential pair icon is placed next to the shortened name of the
first net you selected in the net-pair relationship. In the illustration below, nets
/I$1930/I$205/N$9 and /I$1930/I$205/N$11 are now a differential pair, labeled N$9.
Figure 9-1. Differential Pair N$9
Related Topics
Assigning Rules to Differential Pairs on page 194
You can automatically define differential-pair nets to quickly construct differential pair
relationships for specific nets. After CES automatically constructs differential pairs based on a
net name criterion or IBIS model information, you can select from the proposed list of
differential pairs to choose those that you want to apply to CES. After you apply specific
differential-pair nets, the CES Spreadsheet Nets page is updated to include those differential
pair nets.
Note
In order to automatically define differential pairs based on IBIS models, you must have
an Electrical CES license. Also, differential-pair nets must be part of the same net class;
however, they can belong to different constraint classes.
To Automatically Define Differential Pairs
1. With the CES Spreadsheet Nets page active, from the Pairs toolbar, click .
Alternative: With the CES Spreadsheet Nets page active, from the Edit menu, click
Diff Pairs, and then click Auto Assign Diff Pairs.
2. Fromthe Auto Assign Differential Pairs dialog box, In the Assign by field, select one of
the following assignment methods:
Net Name Group nets into differential pairs based on net naming conventions.
IBIS Models Group nets into differential pairs based on differential pin definitions
in available IBIS models.
Note: After selecting this method, click , and then proceed to step 5.
3. In the Net name field, enter a search criterion.
4. In the Pair net name field, enter an appropriate search criterion with regard to the Net
name search criteria, and then click .
Example: To create differential pair nets for nets beginning with N, enter a Net name
search criterion of N?+ and a Pair net name search criterion of N?-.
5. In the list of proposed differential pairs, click to select the differential pairs that you
want to use, and then click Apply.
Tip: To select all proposed differential pair nets, click . To unselect all differential
pair nets, click .
Result: Differential pairs that you define automatically are indicated on the spreadsheet
in the same manner as differential pairs that you define manually.
6. Optionally, to give one or more differential pairs unique names instead of their system-
defined names, from the CES Spreadsheet, right-click a differential-pair cell, and then
click Rename. Now that the cell is editable, type a new name, and then press Enter.
To Delete a Differential-Pair Net
Fromthe CES Spreadsheet Nets page, click a differential-pair row ( ), and then fromthe Main
toolbar, click .
Assigning Rules to Differential Pairs
IBIS Model [Diff_Pin] Section Declarations
Nets that are connected to a receiver or bidirectional pin in the [Diff_Pin] section of an IBIS
model are always simulated as differential pair nets. This is true regardless of whether you
define the nets as differential pairs within CES. However, the router you use with CES will only
enable differential pair routing/constraints when you have defined a pairing in CES.
Related Topics
After you manually or automatically define differential-net pairings, you can assign rules (i.e.
constraint values) to each differential pair. Unlike many CES constraints, you cannot assign the
same rules to multiple differential pairs by grouping them into constraint or net classes. You
must define rules individually for each net pair.
Differential-Pair Rules
You can assign the following differential-pair rules/constraints:
Pair Tol Max on page 335 Length or delay tolerance of the pair. For example, when
you need a set of differential pairs routed to a matched length or time of flight delay, you
can use this rule to define a very tight pair tolerance, but also define a more loose
matched group tolerance.
Convergence Tolerance Max on page 336 Maximum allowed difference in trace
length distance from a pad to the point where the traces start routing differentially at
Differential Spacing.
Distance to Convergence Max on page 337 Maximumallowed trace distance froma
pad to the point where the traces start routing differentially at Differential Spacing.
Separation Distance Max on page 338 Maximum allowed distance that differential
traces are allowed to be routed at a spacing greater or less than Differential Spacing.
Differential Spacing on page 339 Spacing at which differential pair traces must be
routed. Differential spacing is defined per layer. This is a reference field (i.e. read only)
when accessed from the Differential Pair tab. To modify this value, use the Trace & Via
Properties page, Diff Pair Spacing constraint.
Differential Impedance Target on page 340 Defines the target differential
impedance. When this constraint cannot be met, Differential Spacing is used.
Differential Impedance Tolerance on page 341 Introduces a tolerance around
Differential Impedance Target. You can define this constraint for each differential pair,
or individually for each net that comprises a differential pair.
See also: For more information about a specific differential-pair constraint, click its name to
open the CES Constraint Reference topic for the constraint.
To Assign Differential-Pair Rules
1. From the CES Spreadsheet Nets page, click the row of the differential-pair net ( ) to
which you want to assign differential-pair rules.
Tip: To limit the Nets spreadsheet to a subset of constraints that includes only
differential pair constraints, from the Group dropdown, click Diff Pair.
2. Click in a specific differential-pair rule field (e.g. Pair Tol Max, Distance to
Convergence Max, and Differential Spacing), and then enter an appropriate value.
3. Repeat step 2 to define more differential pair rules.
Example of Defining a Matched Group Tolerance and Pair Tolerance
By defining both a matched group tolerance and differential pair tolerance, you can specify
length or delay tolerances for differential pair nets at the individual net and pair level. For
example, for 3 differential pair nets consisting of 6 total nets, you first define a matched group
tolerance of 100 th to give the router the ability to route each of these nets such that the
difference between the longest and shortest net is less than or equal to 100 th. Because these 6
nets comprise 3 differential pairs, you are also concerned about the difference in length between
each pair of nets that makes up a differential pair. To account for this, you define a pair
tolerance of 20 th to ensure that the maximum difference between net lengths at the differential
pair level is no greater than 20 th.
To Define a Matched Group Tolerance and Pair Tolerance
1. From the CES Spreadsheet Nets page, specify a Match and Tol for one net of the
intended matched group.
2. For the nets that will use this matched group tolerance, enter the match number you
choose in step 1 into the Match field of each appropriate net row.
Example: In the example above, you would specify the match and tolerance in the
spreadsheet row of one of the 6 nets, and then enter the match number into the Match
field of the remaining 5 nets.
3. From the CES Spreadsheet Nets page, specify an acceptable Pair Tol for each
differential pair that is comprised of the nets for which you defined a matched group
tolerance in step 2.
Example: In the example above, you would define a pair tolerance of 20 th for the 3
differential pairs that are based upon the nets for which you defined a matched group
tolerance.
Related Topics
Defining Differential Pairs Automatically on page 192
Chapter 10
Constraint Template Definition and Reuse
This section covers constraint template definition and reuse. Some of the topics included are
definition of constraint templates, and application of constraint templates. This section also
provides information about constraint-template reuse in external designs. Please refer to the
Defining Constraint Templates to Capture Net
Constraints
You can define constraint templates to capture net constraints for reuse on similar nets within
your current design and external designs. Defining a constraint template for a single bus net is a
common application that could promote both design-internal and external constraint template
reuse. For example, after specifying the constraints that promote signal integrity for one bus net
within a 64-bit bus (i.e. 64 total bus nets), you can quickly define a constraint template based
upon that net, and then apply the template to the other sixty-three bus nets that comprise the bus.
By exporting this constraint template, you can then import it into designs that have a common
bus structure, and reuse the constraint template to duplicate characteristics that promote signal
integrity for similar nets.
Note
When you modify constraint values from the CES Spreadsheet Constraint Templates
page, just the values in the template are changed. The originating values, which come
from other spreadsheet pages, are not modified.
To Define a Constraint Template
1. From the CES Spreadsheet Nets page, right-click an electrical net ( ), and then click
Create Constraint Template.
2. In the name field and optional description field, enter suitable identifiers for this
constraint template, and then click OK.
Tip: Enter a name and description that promotes the highest potential for proper reuse
among other designers and yourself.
Result: The constraint template is created and now available from the CES Spreadsheet
Constraint Templates page.
Defining Constraint Templates to Capture Net Constraints
To Rename a Constraint Template
1. From the CES Spreadsheet Constraint Templates page, right-click the name of the
constraint template, and then click Rename.
2. Type a new name, and then press Enter.
To Delete a Constraint Template
From the CES Spreadsheet Constraint Templates page, click the name of the constraint
template you want to delete, and then from the Main toolbar, click .
Developing Libraries of Constraint Templates
Because constraint templates capture all constraints defined for a specific net, constraint
templates are an extremely powerful and efficient way to reuse constraint specifications that
have resulted in or will result in faster progression fromdesign concept to market placement. At
any time during or after the design creation process, you can export constraint templates to a
common directory to build a library of reusable design constraint sets that will streamline the
design creation process for future designs that contain many of the same connection
requirements between parts.
Tip: When developing a library of constraint templates, you should consider making it
accessible to all designers within your group when appropriate. By doing so, you can
leverage common design constraints and promote consistency.
Constraints and Values Stored With Each Template
When you create a constraint template, it combines net values and constraints to produce the
template. It does so by using internal CES database information, constraint definitions you have
made on the CES Spreadsheet Nets, Parts, and Noise Rules pages, and appropriate selections
from specific CES dialog boxes.
Please refer to the following table, which includes a description of each template cell that does
not originate from another spreadsheet page. For all other cells (e.g. Formulas Formula), please
refer to Quick Reference - CES Constraint Spreadsheet on page 27 or CES Constraint
Reference on page 237.
Table 10-1. General Template Values
Template Value Description
Template Name Name of the constraint template.
Description Description of constraint template, if provided.
Device Orig Name Name of the source object.
Applying Constraint Templates to Nets
After you define a constraint template to capture net constraints, you can apply it to one or more
nets. When you apply a constraint template to a net, you should make sure that the net to which
you are applying it is an appropriate candidate for the constraint set defined in the template.
During the application process, which includes the process of elaboration, CES performs an
analysis to determine whether the target net is suitable for the constraint template. Depending
on the required level of similarity you defined while setting up CES, the potential for net
application will vary. By modifying the CES setting that dictates this similarity requirement,
you can specify how similar candidate nets must be to the net from which the constraint
template originated.
Note
To modify the similarity requirement between constraint templates and net candidates,
from the Setup menu, click Settings, click General Options, and then change the
Topology match threshold. For example, to specify a lesser similarity requirement, enter
a smaller percentage value.
Other Common Tasks
Applying Constraint Templates From the Nets Page on page 201
Modifying Pin Matching for an Applied Constraint Template on page 201
Updating a Net With Constraint Template Changes on page 202
Device Type Part number of the source component.
Device Model IBIS model of the source object.
Device Value Discrete value of the source object, when available.
Pin Type Pin type of the source pin.
Pin Number Pin number of the source pin.
Pin Net Template net for the pin.
Pin Model Pin model of the source object.
Pin Set Type Type of pin set (e.g. balanced, unbalanced).
Pin Set Pins Pins included in pin set.
Net Constraint Class Constraint class to which the originating net belongs.
Table 10-1. General Template Values (cont.)
Template Value Description
To Apply a Constraint Template to One or More Nets
1. With the CES Spreadsheet Nets page active, from the Edit menu, click Apply
Constraint Template.
Alternative: From the CES Spreadsheet Nets page, select one or more electrical nets
( ), right-click and then click Apply Constraint Template. Fromthe Select Constraint
Template dialog box, click a constraint template, and then click OK.
2. Fromthe Select Nets for Constraint Template Application dialog box, enter a Net Name
Filter to select the appropriate nets to which to apply the constraint template, and then
click .
3. In the Constraint Template field, use the pull down to select a constraint template.
4. Under the list of Proposed nets, use the checkbox next to each net to uncheck the nets to
which you do not want to apply the constraint template. While you are working with the
list of proposed nets, you can perform any of the following tasks:
To determine the level of compatibility between checked nets and the constraint
template, click Test.
To apply the constraint template to all checked nets without exiting this dialog box,
to the right of the Proposed nets heading, click .
To select all Proposed nets, click .
To deselect all Proposed nets, click .
To clear the list of Proposed nets and start over, click .
5. After you have tested and selected the nets to which you want to apply the constraint
template, click OK.
Optional: After you finish, the Constraint Template Matching dialog box is displayed,
which lets you modify pin matching. For more information, please refer to Modifying
Pin Matching for an Applied Constraint Template on page 201.
To Apply A Constraint Template from the Constraint Templates Page
1. With the CES Spreadsheet Constraint Templates page active, right-click a template
name row, and then click Assign nets.
2. From the Assign nets to template dialog box, use click and Ctrl-click to select one or
more nets.
Alternative: Use the search box, and optionally wildcard characters, to quickly select a
group of nets that match a name criteria.
3. After you finish highlighting the appropriate nets, click OK.
Applying Constraint Templates From the Nets Page
CES provides multiple methods of applying constraint templates to nets. The methods described
in the above procedures are generally more suitable for working with large numbers of nets. The
method described in the procedure below is useful when you want to work with a finite number
of nets by selecting individual nets on the CES Spreadsheet Nets page.
To Apply Constraint Templates From the Nets Page
1. Right-click an electrical net ( ), and then click Apply Constraint Template.
Tip: To select multiple nets, use Ctrl-click or Shift-click.
2. From the Select Constraint Template dialog box, select the constraint template to apply
to one or more nets.
3. When applying constraint templates to nets, specify whether the nets should be moved
into the constraint (electrical and signal integrity) and/or net (physical) classes defined
in the template. To make these specifications, click the check boxes associated with
Apply Constraint Class and Apply Net Class, and then click OK.
Example: To move nets into just the net class defined in the constraint template, make
sure that only Apply Net Class is checked.
Result: The Constraint Template Application Report dialog box shows the
compatibility between a constraint template and nets. It also applies the constraint
template to the selected nets when you begin this procedure with the right-click, Apply
Constraint Template command.
Modifying Pin Matching for an Applied Constraint
Template
You can modify pin matching for each net that is associated with a constraint template. After
you apply a constraint template to a net, the Constraint Template Matching dialog box is
automatically displayed. You can also display this dialog box when you need to update pin
matching.
The Constraint Template Matching display uses both color coding and numbering to show how
well a constraint template matches the net to which it is applied. The following are very
important fields of the dialog box:
Pins Template Displays the number of pins in the template.
Pins Net Displays the number of pins in the net.
Pins Matched Displays the number of net pins that have been matched to template
pins.
When matching constraint templates to nets, good matches are indicated with green color
coding of the Pins Net and Pins Matched fields. Red color coding indicates that there isnt
sufficient matching. Yellow is used to show that the matching isnt good, but it may be suitable.
In the following example illustration, green color coding is used to indicate that all 4 of the pins
in the constraint template have been matched.
Figure 10-1. Example of Pin Matching Between Template and Net
To Modify Pin Matching
1. Fromthe CES Spreadsheet Nets page, right-click the row of a net that is associated with
a constraint template, and then click Update Pin Matching.
2. From the Constraint Template Matching dialog box, in the table at the bottom, click the
right column of a pin row to change the net pin associated with one of the available
template pins.
Rule: Each template pin can only be associated with a single net pin.
3. After you finish making changes, click OK or Apply.
Updating a Net With Constraint Template Changes
After you modify the constraint definitions in a constraint template, nets associated with the
constraint template are not automatically updated to include the template changes. They reflect
the constraint values that were stored in the template at the time the constraint template was
applied to the net. You must update one more nets associated with the constraint template to
include the current constraint values with each net.
Tip: To make it easier to determine when changes have occurred and a net does not
reflect the current constraint values stored in the associated template, please refer to the
CES Spreadsheet Nets page, Template Status constraint.
Reusing Constraint Templates in External Designs
To Update a Net With Modified Template Values
From the CES Spreadsheet Nets page, right-click the row of a net that is associated with a
constraint template, and then click Reapply Constraint Template.
Related Topics
Defining Constraint Templates to Capture Net Constraints on page 197
Reusing Constraint Templates in External
Designs
After you create one or more constraint templates, you can reuse them by exporting them to a
file, and then importing that file into the external design you intend for reuse. Each .cts file
(encrypted XML format) you export includes all constraint template definitions associated with
a CES database.
For example, after defining the physical, electrical, and signal integrity constraints for a net that
serves as the critical connection between two common components for a product line, you can
make the constraint template available for reuse by storing it in a common or collaborative
network directory. You and the other designers in your group now have the ability to reuse this
constraint template in similar designs by applying it to specific design nets that benefit fromthe
constraint set.
To Reuse a Constraint Template in an External Design
1. Export CES constraint templates (File > Export > Constraint Templates) to a .cts file.
See also: For more information about importing or exporting CES constraints, please
refer to the related topics below.
2. Launch CES on the design for which you want to reuse these constraint templates.
3. Import your template file using one of the following methods:
When your templates are stored in a .cts file, use File > Import > Constraints to
specify the file to which you exported constraint templates in step 1.
When your templates are stored in a .ctm file, use File> Import > Constraint
Template to specify a file that you exported from the CTE.
4. You can now apply the imported templates as needed. For more information, please
refer to the related topic below.
Related Topics
Exporting CES Constraints on page 205
Importing CES Constraints on page 205
Reusing Constraint Templates in External Designs
Applying Constraint Templates to Nets on page 199
Chapter 11
CES Constraints Import and Export
This section covers the import and export of CES constraints. It includes two topics, each of
which provides one of the procedures you use to accomplish these tasks.
Importing CES Constraints
You can import CES constraints and templates that you previously exported during an earlier
CES session. During constraint exportation, CES writes constraint information to a file. By
importing CES constraints that are stored in a data file, you can easily work with constraint data
that you, or another engineer saved at a previous time. For example, when you are having
trouble developing the constraints for a specific net, you can export your best-guess CES
constraint data to a file, send it to another engineer (e.g. a signal integrity expert), and then that
person can import your constraints in their CES environment to help devise the appropriate
constraint solution.
Note
When name changes have occurred after you export constraints, constraint values may
not be properly imported.
To Import CES Constraints
1. From the File menu, click Import > Constraints.
2. Fromthe Import Constraints dialog box, select the constraint file (.cts) you want to load,
and then click Open.
3. Optionally, set the display units for the constraint set. For more information, please refer
to Setting Units for the CES Spreadsheet on page 62.
Exporting CES Constraints
You can export CES constraints to capture constraints to a data file for the purpose of importing
them into CES at a later time. When you export constraints, all constraint templates associated
with the CES session are included in the data file. You can export CES constraints in the
proprietary encrypted XML format (.cts), and ASCII format (.csv). Exported constraints use the
native concurrent unit type. After you reimport, you can set the unit type associated with the
constraint set if the native setting is not ideal. You can only import .cts date files.
When exporting constraints, you can either start with the entire constraint set and then reduce
the total amount of constraint data, or select just the spreadsheet rows you want to export.
Depending on the amount of data you want to capture, one of the two procedures below is more
appropriate for your purpose.
To Export CES Constraints
1. From the File menu, click Export > Constraints or Constraints to ASCII.
Note: When you are exporting constraints to ASCII format, now skip to step 3.
2. Fromthe CES - Export Constraints dialog box, specify the following, and then after you
finish, click Export:
Data scope as all data or just specific pages. To select the pages to export, click to
activate the Selected pages radio button, and then click to highlight 1 or more
spreadsheet pages.
Note: When exporting just specific pages, referenced objects between the Nets page
and the Constraint Templates page are not included unless both pages are selected,
or you enable the Include referenced objects check box.
Whether you want to include Default Constraints, User constraints, Objects
hierarchy, and Attributes.
In the Description field, optionally, modify the textual description for the exported
data set. To do so, click to activate the Edit description check box, and then modify
the description.
3. Fromthe resultant Export Constraints dialog box, specify a filename and location for the
constraint data file you want to export, and then click Save.
To Export Only Selected Nets or Spreadsheet Rows
1. Fromthe CES Spreadsheet, use click or Ctrl-click to select the rows or rows you want to
export.
2. After you finish making your selections, right-click, and then click Export Selection.
3. From the Export Selected Constraints dialog box, specify the following options, and
then after you finish, click Export:
When applicable, referenced objects between the Nets page and the Constraint
Templates page.
Whether you want to include Default Constraints, User constraints, Objects
hierarchy, and Attributes.
In the Description field, optionally, modify the textual description for the exported
data set. To do so, click to activate the Edit description check box, and then modify
the description.
4. Fromthe resultant Export Constraints dialog box, specify a filename and location for the
constraint data file you want to export, and then click Save.
Related Topics
Importing CES Constraints on page 205
Reusing Constraint Templates in External Designs on page 203
Chapter 12
Stackup Property Display
This section covers stackup property display. It includes a single topic, viewing or modifying
stackup properties.
Viewing or Modifying Stackup Properties
You can view or modify the properties of the stackup associated with a CES design. By doing
so, you can verify existing stackup characteristics or modify specific attributes to augment the
stackup to account for design changes that result from the creation and verification of CES
constraints.
Note
When using CES as part of the Board Station XE design flow, the CES Stackup Editor is
read-only. You must make stackup changes through Board Station XE. In an Expedition
PCB flow, however, you can performsuch operations, but do so cautiously because there
may be severe consequences when the board has already gone through partial or full
routing.
Note
When using CES as part of the BSXE or BSRE design flow, when the Er for a conductive
layer is "0", the Er of the adjacent dielectric layer is passed on to the CES Stackup Editor.
To View or Modify Stackup Properties:
From File toolbar, click , or, from the Edit menu, click Stackup.
See also: To learn more about using the Stackup Editor, please refer to the Stackup Editor Help.
This help system is accessible through the dialog box Help buttons and Help > Contents menu
selection of the Stackup Editor.
Correlating Layer Names Among Design Tools
The CES Spreadsheet, CES Stackup Editor, and your PCB layout system use slightly different
nomenclature when referring to unique board-layer types. Please refer to the following table for
an understanding of howthese names correlate among design tools. PCB layout systems include
Expedition PCB, Board Station XE, and Board Station RE.
Stackup Property Display
Viewing or Modifying Stackup Properties
Note
Because CES deals with just signal-layer nets, dielectric layers displayed in the CES
Stackup Editor do not apply. This includes solder mask and substrate layer types.
Table 12-1. Board-Layer Name Correlation
CES Spreadsheet CES Stackup Editor PCB Layout System
Signal Signal Signal
Flooded Signal Flooded Signal Flooded
Mixed Split/Mixed Plane
Chapter 13
Part-Model Assignment Verification
This section covers part-model assignment verification. Some of the topics included are
verification of default part-model assignments, and specification of available part models. This
section also provides information about assigning models to parts. Please refer to the table of
contents for the full listing of topics included in this section.
Verifying Default Part-Model Assignments
The first time you launch CES on a design, it automatically assigns models to parts by matching
design components with part models located in the subfolders of your design folder. In order to
ensure that its designations are correct, you should verify these default assignments using the
content generated by the Model Audit Report. When one or more assignments is incorrect or
unavailable, you must manually specify available part models, and then assign these models to
specific parts located on the CES Spreadsheet Parts page.
Note
In order to use this feature, you must have an Electrical CES license.
To Verify Default Part Model Assignments
1. From the Output menu, click Model Audit Report.
2. Fromthe Model Audit Report that CES produced, scroll its content to locate instances of
ERROR and WARNING lines.
3. For each instance, locate its row on the CES Spreadsheet Parts page, and then do one of
the following things:
Assign the correct model to the part.
Specify additional available part models, and then assign the correct model to the
part.
Automatic Assignment of IBIS Models
IBIS models you selected from within in your schematic capture or PCB layout design tool will
automatically be assigned in CES when the following conditions are met:
The model matches the pinout of the part.
The model parses without error.
Verifying Default Part-Model Assignments
Because IBIS models are loaded based on the PART_NO property, this property value
must be the IBIS Component name in an (.ibs) file that resides in one of the SI Library
search paths. For more information, please refer to Specifying Available Part Models
on page 213.
Hierarchical Assignment Process
CES uses the following assignment hierarchy to set the default IBIS Component Name value for
each part:
1. When you provide the IBIS component attribute on a symbol that is contained in a part
instance, it is used as the default IBIS component name. If this attribute is set on more
than one symbol that maps to a particular part instance, CES decides which wins based
on its established rules.
2. User provided IBIS component name for the entry in the PDB corresponding to the part
instance.
3. CES searches the IBIS library for a component with the same name as the PCB part
name. When it finds a case insensitive match, it uses this value.
4. CES searches the IBIS library for a component with the same name as the symbol name
for the part instance in the PDB. When it finds a case insensitive match, it uses this
value.
5. When the part instance has a Technology value, CES searches for an IBIS component
that matches the technology. When it finds a match, it uses this value.
6. When the part instance is a simple passive component that is included in the list below,
the IBIS component name is set to one of the following values:
R_by_value (resistor)
C_by_value (capacitor)
L_by_value (inductor)
RC_by_value (RC terminator)
RThev_by_value (thevenin terminator)
7. When the part instance is not a simple passive component, diode, or connector, the
default IBIS component name is set to generic. The IBIS library provided with the
release always contains a supporting IBIS component named generic to support this
type of assignment.
Note
The only case where CES sets IBIS Component Name to reference a component that does
not exist is when you explicitly set a name in the schematic or PDB, and it does not exist.
Specifying Available Part Models
Related Topics
Assigning Models to Parts on page 215
You can specify the group of models that is available within CES for part assignment. When
making part models available to CES, you can update the group to include all model files stored
in a local or network directory, or just a single model file. CES supports IBIS (I/O Buffer
Information Specification) component models. In addition to the standard IBIS model file
format (.ibs), you can also use IBIS EBD (electrical board definition) model files (.ebd).
Note
IBIS Models Delivered With CES
CES comes with a set of IBIS models that you can use to model an array of component
technologies. This collection of over ten thousand model files is available within your
installation tree at the following location:
Board Station XE: <Install location>\7.xBSXE\mgc_ibis_lib
Expedition Enterprise: <Install location>\7.xEE\mgc_ibis_lib
In addition, there are other IBIS models available at the following location:
Board Station XE: <Install location>\7.xBSXE\SDD_HOME\hssd\models\ibis\tech
Expedition Enterprise: <Install location>\7.xEE\SDD_HOME\hssd\models\ibis\tech
You can also search your Mentor Graphics software installation for other .ibs files.
Other Common Tasks
Specifying Individual Model Files on page 214
Understanding Relative Paths on page 215
Specifying Model File Directories
You can add directories, remove existing directory entries, and change the order of directories
searched and displayed within the IBIS Model Browser.
Note
When adding an IBIS EBD model file to the group of available component models, make
sure to include any standard IBIS model files that are referenced within the IBIS EBD
model.
To Add a Directory to the Model Search Path
1. From the Edit menu, click Simulation, and then click SI Library Search Paths.
another page active to enable this menu option.
Alternative: To access this dialog box from the IBIS Model Browser, at its top right,
click .
2. From the SI Library Search Paths dialog box, click .
3. In the newrowthat appears in the IBIS Libraries listing, enter the directory path, or click
the browse button to navigate to the path and select it.
To Remove a Directory From the Model Search Path
2. From the SI Library Search Paths dialog box, in the listing of IBIS Libraries, click the
directory you want to remove, and then click .
To Change the Search/Display Order of Model Directories
2. From the SI Library Search Paths dialog box, in the listing of IBIS Libraries, click the
directory for which you want you to change its order, and then click or to move the
directory up or down within the list.
Result: The IBIS Model Browser Directories / Components list is updated to reflect the
new order.
Specifying Individual Model Files
When you want to make one or more single model files available to CES, you can add
individual IBIS and EBD files to the group of available models. You can use both methods of
model specification interchangeably. For example, after specifying several or more model file
directories, you can add a dozen individual model files to complete the specification of
available models.
Assigning Models to Parts
To Add an Individual Model File
1. With the CES Spreadsheet Parts page active, in any IBIS Component Name or
Technology cell, click .
2. From the IBIS Model Browser, click .
3. From the Open dialog box, browse to the model file (.ibs or .ebd), select it, and then
click Open.
Result: All models included in the model file are now available within CES.
Understanding Relative Paths
When you enter a relative path, an attempt is made to fully resolve the path. On Windows, this
includes pre-pending the current drive letter from which CES was launched. When the path
does not exist, you are prompted with a dialog box asking whether you want to keep the path as
it is, or reject it. When you keep it, the unresolved path will be used.
You can assign models to parts to specify the component technology used during ICX Pro
Verify design verification. In most cases, each part will already include a model assignment.
When an assignment is incorrect, you can change the model associated with a part. Because pin
information is stored in each part model, these designations are also used by CES to construct
accurate electrical nets.
Note
Common Tasks
Updating Part Model Constraints on page 216
Reloading Model Directories and Individual Models on page 216
To Assign a Model to a Component
1. From the CES Spreadsheet Parts page, in the row of the component to which you want
to assign a model, in its IBIS Component Name or Technology cells, click .
2. From the IBIS Model Browser, under Directories / Components, click a specific
directory, or click All to display models in all directories that are available to CES.
Tip: To select multiple directories but not all directories, use Ctrl-click and Shift-click.
To search for a directory, in the Search directory field, enter a search string, and then
click .
3. In the Component list, click the model you want to assign to the component.
Tip: To search for a model when the Component list includes a large number of models,
in the Search component field, enter a search string, and then click .
4. In the Pin Model Types field, click the dropdown, and then click a specific pin type (e.g.
Output) or All.
5. In the table below the Pin Model Types field, click a pin/model row, and then click OK.
Tip: To change the display of this table, use the Select by Pin and Select by Model radio
buttons.
To Edit a Model File
From the IBIS Model Browser, select a model file from the Component list, and then do one of
the following things based on the editor you want to use:
To use the ICX Pro Visual IBIS Editor, click .
To use the Quick Model Wizard, click .
IBIS Models or Technology Models?
Although you can assign an IBIS model and a technology model to a single part, when both are
present, the IBIS Component Name model is used. IBIS models provide greater detail than
technology models, which model pins based on pin type. IBIS models include dedicated pin
models for each component pin. For example, an IBIS model for a sixteen pin component will
include sixteen individual pin models. A technology model used for the same component may
include 3 or 4 pin models (i.e. one for each type of pin for the sixteen pin set).
Updating Part Model Constraints
You can update the IBIS Pin Type part model constraint to reflect accurate pin designations.
Doing so also updates default values.
To Update IBIS Pin Types
With the CES Spreadsheet Parts page active, fromthe Data menu, click Update, and then click
IBIS Pin Type & Defaults.
Reloading Model Directories and Individual Models
When one or more of your model directories or models are located in a network folder, it is best
practice to occasionally reload those model directories or individual models. By doing so, you
can make sure that the model data available to CES is the most current. You should also reload
Overriding IBIS Values
model information when you make changes to any model directories or individual models on
your local machine.
Note
Reloading a model directory refreshes all individual models contained within it.
To Reload Model Directories
1. With the CES Spreadsheet Parts page active, in any IBIS Component Name or
Technology cell, click .
2. From the IBIS Model Browser, under Directories / Components, select one or more
model directories:
Select all model directories by clicking the All row.
Select two or more model directories by using Ctrl-click and Shift-click to highlight
the appropriate rows.
Select just a single model directory by clicking it.
3. Click .
To Reload an Individual Model
From the IBIS Model Browser, in the list of available models, click a row, and then next to the
Search component field search button, click .
Tip: To adjust the list of available models, use the directory selections under Directories /
Components. For example, to list all available models, click All.
Related Topics
Specifying Available Part Models on page 213
Updating Electrical Net Data and Results on page 112
For discrete components, Thevenin terminators, and AC terminators that reference IBIS
models, you can override the discrete values stored in them by entering values directly into
CES. For example, although the IBIS model for a resistor specifies resistance as 50 ohms, you
want to temporarily change the value to 60 ohms.
To Override a Value
1. From the CES Spreadsheet Parts page, in an appropriate IBIS Component Name cell,
enter one of the following override types:
C_by_value Capacitance by value.
L_by_value Inductance by value.
R_by_value Resistance by value.
RC_by_value AC terminator by value.
RThev_by_value Thevenin terminator by value.
2. In the Value cell, enter one or more override values based on the following guidelines:
For C_by_value, L_by_value, and R_by_value, enter a single override value.
For RC_by_value, enter a resistance and a capacitance value, and separate themwith
a colon (e.g. 75:5).
For RThev_by_value, enter two resistance values, and separate them with a colon
(e.g. 75:75).
Example: In the following illustration, a resistor model has been changed to a Thevenin
terminator with resistance values of 75 ohms and 50 ohms.
Figure 13-1. Thevenin Terminator by Value
Chapter 14
Signal Integrity Exploration
This section cover signal integrity exploration and enhancement with HyperLynx
LineSim
and ICX Pro Explorer. Some of the topics included are sending nets out for signal integrity
analysis, and creating constraint templates to capture enhancements. This section also provides
information about updating CES with constraint enhancements. Please refer to the table of
contents for the full listing of topics included in this section.
Sending Nets to HyperLynx LineSim
You can export an electrical net from the Nets page of the CES Spreadsheet to a LineSim free-
form schematic. In LineSim, you can run what if experiments to find physical and electrical
net properties that satisfy signal integrity and other performance requirements. When you send a
net from CES to HyperLynx LineSim, the board stackup for the design is included to ensure
simulation accuracy.
From LineSim, you can export a constraint template file that can be imported back into CES. It
is important to note that some information can be lost when transitioning your net data from a
free-form schematic to a constraint template file. For instructions regarding exporting a
constraint template file from LineSim, please refer to HyperLynx LineSim documentation or
search the InfoHub to locate this information.
Figure 14-1. CES-HyperLynx LineSim Design Flow
Prerequisites
HyperLynx 8.0 or newer must be installed on the same computer as CES.
HyperLynx must use or include the same IBIS search paths as CES.
Limitations
Resistor and capacitor packages can be modeled with IBIS models in CES, however
HyperLynx does not support IBIS package models. On the other hand, HyperLynx
supports series elements described in IBIS/EBD files for IC components. This means
that resistors and capacitors with three or more pins, and assigned IBIS/EBDmodels, are
Sending Nets to ICX Pro Explorer
exported to the free-formschematic as IC components with assigned models. Only those
signal pins of passive network packages that are connected inside it (that is, belonging to
the same electrical net) are exported.
Unconnected pins on the net have no topology information. These pins will be
connected in a chained routing topology that you can verify and edit in the free-form
schematic.
Exported connectors are modeled in the free-form schematic as ICs with no model
assignment.
To Send a Net to HyperLynx LineSim
From the CES Spreadsheet Nets page, right-click an electrical net ( ), click Display Net in,
and then click HyperLynx LineSim.
Result: When HyperLynx 8.0 or newer is installed on the same computer, LineSim
automatically opens and displays the net in the free-form schematic editor. The exported free-
form schematic (FFS) and HyperLynx project (PJH) files are written to
\<projects_folder>\<project_name>\HighSpeed\HyperLynx\<net_name>. For example,
C:\mentor_projects\test_project\HighSpeed\HyperLynx\data1.ffs.
Related Topics
Updating CES With Constraint Enhancements on page 224
You can send nets from CES to ICX Pro Explorer to explore constraint enhancements for nets
that produce a large number of hazardous actuals in CES. By working with these nets in ICX
Pro Explorer, you can determine net and constraint changes that produce sufficient signal
integrity results. After you enhance a trace model schematic (net topology) in ICXPro Explorer,
you can run simulation on just this topology, and analyze the results to determine which net and
constraint changes increase the integrity of the signal propagated by the net. This work flow is
captured in the following illustration.
Figure 14-2. CES-ICX Pro Explorer Design Flow
As the above flow diagram indicates, you can send a CES net directly to ICX Pro Explorer for
signal integrity exploration and enhancement work. Typically, you use CES constraint actuals
and hazard information displayed in your PCB system to determine which nets need ICX Pro
Explorer exploration.
Note
In order to use this signal integrity exploration and enhancement tool, you must have a
license.
After you send a net fromCES, any modifications you make to it fromwithin ICX Pro Explorer
are not reflected in CES until after you complete the update process. In addition, actual values
generated in the ICX Pro Explorer Simulation Results Spreadsheet are not displayed in CES.
To Send a Net to ICX Pro Explorer
From the CES Spreadsheet Nets page, right-click an electrical net ( ), click Display Net in,
and then click ICX Pro Explorer.
When sending a net, the following unit values from CES are included as necessary: Linear,
Ohms, Time, and Voltage. Based on your constraint definitions, some or all of these unit values
are accurately displayed in the SRS and CTE.
Related Topics
Updating CES With Constraint Enhancements on page 224
Creating Constraint Templates to Capture Enhancements
After you enhance the signal integrity of a net topology, you can create a constraint template to
capture those enhancements for later application in CES. Although a constraint template you
create for a net will include any net topology enhancements that you made while refining
component and transmission line symbol properties of the TMS, you can also make additional
net topology changes using the fields displayed by the Constraint Template Editor. For
example, you can modify high-speed constraints like overshoot, ringback, and simulated delay
(i.e. signal edge-rate delay).
Note
A TMS is ICX Pro Explorers unique way of displaying and working with both
schematic-entry and PCB-layout elements of design nets. These combined
representations of front-end and back-end net components are called trace model
schematics. By combining both properties in one environment, you can easily explore the
effects of trace and part changes on overall net signal integrity without confining your
view to the schematic or PCB representations, each of which focus move heavily on the
perspective of one type of electronic design engineer. Whenever you send a net fromCES
to ICX Pro Explorer, a TMS is created to represent the nets combined logical and
physical characteristics.
Because multiple constraint templates can be displayed at the same time, you can also paint
rules to quickly reuse suitable constraints that you defined in one constraint template, without
having to hand-enter the rules into additional constraint templates.
Other Common Tasks
Reducing the Display of CTE Constraints on page 223
Importing Constraint Templates on page 224
Deleting Constraint-Template Objects on page 224
To Create a Constraint Template
Fromthe ICX Pro Explorer trace model schematic, right-click a driver or receiver symbol, click
Constraints, and then click Create Template (Selected).
Alternatives:
After you click a driver or receiver symbol, fromthe File menu, click Create Template
(All).
Right-click any driver or receiver symbol, click Constraints, and then click Create
Template (All).
To Save a Constraint Template
1. From the Constraint Template Editor (CTE) Main toolbar, click .
Alternative: From the File menu, click Save Template.
2. Fromthe Export Constraint Template dialog box, specify a location and filename (.ctm),
and then click Save.
Rule: By default, constraint templates are saved in your top-level design folder.
Result: All constraint templates ( ) currently displayed in the CTE are saved to the .ctm
file you specified.
Updating a Net Topology With CTE Changes
When you make changes to the constraint values available fromthe Constraint Template Editor,
you must update the net topology if you want to re-simulate it using the updated constraint
values.
To Update a Net Topology for Simulation
From the CTE, click the top-level row of a constraint template, or a sub-level differential net
row, and then from the Main toolbar, click .
Example: In the following illustration, the positive net of a differential pair is selected for
update.
Figure 14-3. Sub-Level Net Selected for Update
You can quickly copy all constraint values that you define in a spreadsheet row into the rows of
other design objects that will benefit from these values. When painting rules to copy constraint
values, it is important to remember that the design object from which you copy must be the
same as the design object to which you copy.
To Copy Constraint Values Between Rows
1. Click a CTE spreadsheet row, and then from the Main toolbar, click .
2. Click the CTE spreadsheet row for which you want to apply the copied constraint
values.
3. Continue clicking additional rows to paint these rules where appropriate.
4. To turn off the Rule Painter, from the Main toolbar, click .
Reducing the Display of CTE Constraints
When you want to work with just a subset of CTE constraints, you can select from pre-defined
and user-created constraint groups to limit the types of constraints that are displayed.
To Display Only Specific Constraint Types in the CTE
From the Main toolbar, click the Group dropdown, and then select a constraint type.
Example: To display only Overshoot/Ringback constraints, click the Group dropdown, and
then click Template Overshoot/Ringback.
To Display All Constraint Types
From the Group dropdown, click All.
Updating CES With Constraint Enhancements
Importing Constraint Templates
You can import constraint templates into your ICX Pro Explorer environment for the purpose of
applying themto trace model schematics, viewing/editing themto verify their constraint values,
or painting rules from one constraint template to another. When your goal is application, the
Template Name associated with an imported constraint template must match the net name to
which you want to apply it.
To Import a Constraint Template
1. From the Main toolbar, click .
Alternative: From the File menu, click Open Template.
2. From the Import Constraint Template dialog box, browse to the appropriate constraint
template file (.ctm), and then click Open.
Deleting Constraint-Template Objects
As you work with constraint templates, you may want to delete a design-object row (e.g. a
specific from-to or pin pair), or an entire constraint template.
To Delete a Constraint-Template Object
From the CTE, click a unique design-object row, or a top-level constraint-template row, and
then from the Main toolbar, click .
Rule: When you select a row that you cannot delete, the delete icon will not become active.
Related Topics
Sending Nets to ICX Pro Explorer on page 220
After you create a constraint template to capture net topology enhancements, you can apply it
one or more nets in CES. By doing so, you will complete the signal integrity and enhancement
process by updating CES with the work that you performed in HyperLynx LineSim or ICX Pro
Explorer.
Note
You must make a constraint template file (.ctm) available to CES before you can apply a
constraint template stored within it to a net.
To Update a CES Net With Constraint Enhancements
1. From the CES File menu, click Import, and then click Constraint Template.
2. From the CES Import Constraint Template dialog box, select the path and filename of
the constraint template file (.ctm) that includes your net topology enhancements, and
then click Open.
3. From the CES Spreadsheet Nets page, select one or more electrical nets ( ) to update,
right-click, and then click Apply Constraint Template.
4. From the Select Constraint Template dialog box, click the constraint template of the net
you enhanced in HyperLynx LineSim or ICX Pro Explorer, and then click OK.
Result: Your net enhancements are applied to one or more CES nets.
Example of Updating Net DiffPairA
In this example, you have used ICX Pro Explorer to enhance the signal integrity of a CES net,
DiffPairA. After saving the ICX Pro Explorer version of this net to a constraint template
(DiffPairNets.ctm), you are ready to update CES with the changes stored in the template.
To Update Net DiffPairA
1. Fromthe CES Import Constraint Template dialog box, select DiffPairNets.ctm, and then
click Open.
2. From the CES Spreadsheet Nets page, right-click net DiffPairA, and then click Apply
Constraint Template.
3. From the Select Constraint Template dialog box, click the DiffPairA template, and then
click OK.
Result: CES net DiffPairA is updated to include the constraint enhancements of the
DiffPairA template, which was stored in the DiffPairNets.ctm template file.
Related Topics
Sending Nets to HyperLynx LineSim on page 219
Sending Nets to ICX Pro Explorer on page 220
Creating Constraint Templates to Capture Enhancements on page 221
Chapter 15
Design Tool Update
This section covers design tool update. Some of the topics included are management of design
changes between tools, synchronization of constraint data between schematics and CES, and
sending schematic data to layout. This section also provides information about synchronization
of constraint data between CES and layout, and sending layout data to schematics. Please refer
to the table of contents for the full listing of topics included in this section.
Managing Design Changes Between Tools
After you exit CES, constraint changes you make while working within CES are automatically
synchronized with the schematic entry or PCB layout tool from which you launched CES. For
example, after launching CES from DxDesigner, changes that you make to constraints that
correspond to schematic design properties are updated within DxDesigner after you exit CES.
Froma back-end perspective, Expedition PCB, for example, is updated with changes fromCES
in the same manner; however, you can explicitly send pending CES changes to layout during
the active CES session as well.
When you want to update changes between the front-end and back-end tools that comprise your
flow, you can perform forward annotation by sending schematic data to layout, or back
annotation by updating schematic designs with changes from layout. During these processes,
constraint synchronization occurs, resulting in full updates of both the front-end and back-end
constraint sets. For more information, please refer to CES Synchronization of Constraint
Databases on page 228.
Communicating Design Changes Between Schematic and
Layout
CES provides several constraint-driven design flows that bring together front-end design
systems (schematic) like Design Architect, Board Architect, Design Capture, DesignView, and
DxDesigner with back-end design systems (layout) like Expedition PCB, Board Station XE, and
Board Station RE. Depending on the design systems that make up your design flow, you
communicate design changes between schematic and layout using the forward and back-
annotation commands provided by your design systems.
Constraint-Driven Design-Flow Manuals
For proper usage of these design annotation commands within the CES constraint-driven design
flow that you use, please refer to the following design-flow manuals:
Design Tool Update
Constraint Editor System (CES) User's Manual for Board Station XE and RE Flows
(da_bs.pdf)
Constraint Editor System (CES) User's Manual for Expedition Enterprise Flow: Design
Capture (dc_exp.pdf)
Constraint Editor System (CES) User's Manual for Expedition Enterprise Flow:
DxDesigner (dx_exp.pdf)
You can find these PDFs within InfoHubs, on SupportNet, or in your Mentor software
installation directory.
CES Synchronization of Constraint Databases
The most important thing to understand about constraint synchronization is that both the front-
end and back-end constraint databases are fully updated as a result of this process. Regardless of
whether you are forward annotating or back annotating, both CES databases will have the
latest/synchronized constraint data. For this reason, the synchronization process is unlike
standard design annotation, which usually results in the front-end communicating its changes to
the back-end, or vice versa, but not both at the same time. The following illustration provides an
overview of this process.
Figure 15-1. CES Synchronization Updates Both CES Databases During Design
Annotation
Design Tool Update
Caution
Because you set the winner separately for forward annotation and back annotation, the
CES database value that is propagated depends on these settings. In some cases, you may
always want the front-end to win when there is a conflict (whether forward annotating or
back annotating). In other cases, you may want the back-end to win only when you are
back annotating design changes. To specify the winner for each type of design
annotation, please refer to Resolving Constraint Conflicts Between Front-End and Back-
End Designs on page 232.
CES synchronization works in this manner to provide more opportunities for constraint
alignment in all of its flows. Because both forward annotation and back annotation result in full
constraint synchronization, overall design state is less of an issue for update purposes. For
example, when your Design Architect/Board Architect data is changing less frequently as you
move toward manufacturing start, forward annotating to Board Station XE gives you more
opportunities to acquire constraint changes made in XE-CES. Due to the large volume of design
changes that can occur in Board Station XE at the end of the PCB creation cycle, forward
annotating to get back-end constraint changes saves time because there are few or no schematic
changes to communicate to your layout design.
XtremePCB
XtremePCB gives multiple designers the ability to simultaneously work on a single layout
project. Because of this, CES synchronization is also used as a back-end only process to manage
changes to layer and net constraints within your PCB design. The result is that all constraint
work performed by multiple designers is accurately stored in the back-end CES database.
During forward annotation and back annotation, the front-end and back-end CES databases are
synchronized as explained above.
Note
When you run XDS Save from XtremePCB, it back annotates when necessary. As
expected, this back-annotation process includes full CES synchronization between back-
end and front-end constraint databases.
TeamPCB
TeamPCB gives you the ability to partition your layout design, but it does not incorporate
constraint changes made to a partition. For this reason, you should use TeamPCB to perform
layout operations to partitionsnot constraint modifications. After a partition is rejoined to the
main layout design, you can modify constraints in CES.
Design Tool Update
Example Synchronization Scenarios
Please refer to the following example scenarios, which are the five synchronization cases. Each
scenario also includes the results to expect based on whether you are forward annotating or back
annotating. The winner setting in the .prj file is also reflected in these examples when
appropriate.
Scenario 1
In this scenario, just the front-end constraint database has been modified. There have been no
changes in the back-end constraint database since the last synchronization occurred.
Forward-Annotation Result
The back-end CES database is updated with front-end constraint changes during forward
annotation.
Back-Annotation Result
The back-end CES database is updated with front-end constraint changes during back
annotation.
Scenario 2
In this scenario, just the back-end constraint database has been modified. There have been no
changes in the front-end constraint database since the last synchronization occurred.
Forward-Annotation Result
The front-end CES database is updated with back-end constraint changes during forward
annotation.
Back-Annotation Result
The front-end CES database is updated with back-end constraint changes during back
annotation.
Scenario 3
In this scenario, both the front-end and back-end constraint databases have been modified since
the last synchronization occurred. Although changes have occurred on both sides, none of the
same constraint values have been changed.
Forward-Annotation Results
The front-end CES database is updated with back-end constraint changes during forward
annotation.
Design Tool Update
The back-end CES database is updated with front-end constraint changes during forward
annotation.
Back-Annotation Results
The front-end CES database is updated with back-end constraint changes during back
annotation.
The back-end CES database is updated with front-end constraint changes during back
annotation.
Scenario 4
the last synchronization occurred. Roughly half of the changes on both sides are changes to the
same constraint values.
The front-end CES database is updated will all non-conflicting back-end constraint
changes during forward annotation.
The back-end CES database is updated with all non-conflicting front-end constraint
changes during forward annotation.
Based on the SchematicConflict key in the .prj file:
o If it specifies that the front-end should win during forward annotation (Default),
conflicting back-end values are updated with the front-end changes.
o If it specifies that the back-end should win during forward annotation (BE),
conflicting front-end values are updated with the back-end changes.
The front-end CES database is updated with all non-conflicting back-end constraint
changes during back annotation.
The back-end CES database is updated with all non-conflicting front-end constraint
changes during back annotation.
o If it specifies that the back-end should win during back annotation (Default),
conflicting front-end values are updated with the back-end changes.
o If it specifies that the front-end should win during back annotation (FE),
conflicting back-end values are updated with the front-end changes.
Design Tool Update
Scenario 5
the last synchronization occurred. All of the changes on both sides are changes to the same
constraint values.
If it specifies that the front-end should win during forward annotation (Default), back-
end values are updated with the front-end changes.
If it specifies that the back-end should win during forward annotation (BE), front-end
values are updated with the back-end changes.
If it specifies that the back-end should win during back annotation (Default), front-end
values are updated with the back-end changes.
If it specifies that the front-end should win during back annotation (FE), back-end
values are updated with the front-end changes.
Resolving Constraint Conflicts Between Front-End and
Back-End Designs
During the forward annotation and back annotation processes, you can use your .prj file to
designate which design constraints should be used when there is a conflict between front-end
and back-end design constraints. The key you use to do this is called SchematicConflict. By
default, this key value in your .prj file is set to Default. This means that the front-end wins
during forward annotation, and the back-end during back annotation. You can set this key to
specify that the opposite occurs. For example, Expedition PCB constraint values win when there
is a conflict during forward annotation.
To Set This KEY
In your .prj file, locate the KEY SchematicConflict line, and then modify its value such that it
is one of the following entries:
Default When any conflicts occur, schematic constraints win during forward
annotation. Layout constraints win during back annotation.
FE Schematic constraints win when any annotation conflicts occur.
BE Layout constraints win when any annotation conflicts occur.
Design Tool Update
Resolving Constraint Conflicts Manually
Related Topics
Sending Schematic Data to Layout on page 235
Sending Layout Data to Schematics on page 236
Using the Constraint Resolution Manager (CRM) mode of CES, you can manually determine
which of 2 or more constraint values should be used when conflicts arise. Because CRM is a
real-time mode tool, you can also select fromvalues that are actively being entered concurrently
by other users connected to the design.
Currently, CRM only supports conflict resolution between schematic sheet or blocks that you
copy from a source schematic design to a target schematic design. Providing manual constraint
resolution during this type of copy gives you the ability to specify the aspects of net design
reuse you want to apply, while keeping important constraint values that are unique to your
design. In some cases, you might want to use most of the constraint values in the source sheet or
block, and keep only a few of the values in the target design. In other cases, you might specify
that more constraint values in the target sheet or block be used than those in the source design.
Prerequisites
You must have copied a schematic sheet or block from a source design to a target
design.
Optionally, you can set up your schematic tool to launch CRM automatically. Please
refer to your schematic documentation to determine how to set up the application to
launch the Constraint Resolution Manager automatically for conflict resolution when
copying a sheet or block between designs.
Procedure
1. When CRMis not automatically displayed, fromthe CES Tools menu, click Constraint
Resolution Manager.
2. CES is now in CRM mode. It has the appearance of CES, but provides a limited subset
of functions related to manual resolution of constraint conflicts. At any time, to switch
from CRM mode back to CES, from the CRMTools menu, click Constraint Editor
System.
3. When there are conflicting constraint values between source and target objects, the CES
Spreadsheet Nets page and/or Trace &Via Properties page will highlight each net and/or
layer row that has conflicting constraint values. Cells that do not conflict will remain
white.
4. For each conflicting cell, you can do the following:
Design Tool Update
To view the list of availabe values from which you can choose, click the dropdown
button. S refers to the source value, T refers to the target value, and C refers to
a concurrent value that is being entered in real time.
To change the default conflict resolution by choosing a different constraint value,
right-click a cell, and then click the appropriate Restore to selection. For example,
to use the value already in a sheet or block to which you are pasting, click Restore to
Target.
5. Change appropriate constraint values as often as you like until the correct set of source,
target, and concurrent values are present.
6. After you have finished, close the CRM, or switch to CES mode. To do so, from the
CRMTools menu, click Constraint Editor System.
Results
The set of appropriate constraint values is chosen. There are no longer any conflicting
constraints in the target sheet or block.
Related Topics
Viewing Constraint Resolution Statistics
While you are using the Constraint Resolution Manager, you may find it helpful to get a top-
level view of the source, target, or concurrent selections that you have made to resolve each set
of conflicting values. Doing so is especially helpful when you want to quickly verify that the
selections you have made are correct. The alternative is to scroll through each affected page of
the CES Spreadsheet. In comparison, using that method can be error-prone and time-
consuming.
Prerequisites
CES must be in CRM mode.
Procedure
1. From the CRMData menu, click Constraint Resolution.
2. From the Constraint Resolution dialog box, review the table of Source and target wins,
and the summary of win statistics located at the top of the dialog box.
3. Optionally, you can do any of the following:
To display just target wins, click to enable the Show only target wins check box.
Viewing Constraint Resolution Statistics on
page 234
Design Tool Update
Synchronizing Constraint Data Between Schematics and CES
To display only source wins, click to enable the Show only source wins check box.
To update the table to show the latest wins after you make changes within the CRM,
click Refresh.
To cross probe to the CES Spreadsheet row to which a win refers, click a list row.
Alternative: To move up or down one row in the wins list while cross probing, click
or .
4. After you finish reviewing statistics, click Close.
Results
The dialog box is no longer displayed on screen, leaving the CRMat the forefront of the screen.
Related Topics
Synchronizing Constraint Data Between
Schematics and CES
You synchronize constraint data between schematics and CES whenever CES saves your
constraint modifications. During this process, the front-end tool from which you launched CES
is updated with any applicable constraint changes or assignments.
Sending Schematic Data to Layout
After you synchronize constraint data between schematics and CES, you can send schematic
data to layout to update layout with any applicable changes. The process of sending schematic
data to layout is called forward annotation.
To Send Schematic Data to Layout
From your front-end design tool, or in some cases your back-end design tool, forward annotate.
Note: For specific forward-annotation commands, please refer to the CES constraint-driven
design-flow manual for your flow, or your schematic-capture software documentation.
Sending DxDesigner Schematic Data to Expedition PCB
When sending constraint changes you made in DxDesigner to Expedition PCB, you must first
create a front-end CES database by launching CES from DxDesigner. You must only do this
once in order for the database to be created. For example, after using only the DxDesigner
Resolving Constraint Conflicts Manually on
page 233
Design Tool Update
Synchronizing Constraint Data Between CES and Layout
Attributes add-in to enter or modify Expedition PCB style constraints, you do not yet have a
front-end CES database. To create it, from the DxDesigner Tools menu, click Setup
Constraints.
Synchronizing Constraint Data Between CES and
Layout
You synchronize constraint data between layout and CES whenever you exit CES or explicitly
updating layout with pending CES changes. During either of these processes, the back-end tool
from which you launched CES is updated with any applicable constraint changes or
assignments.
Note
When Expedition PCB, Board Station XE, or Board Station RE is your layout system,
you must save your layout database after you exit CES. This is true regardless of whether
you have made design changes to your layout database prior to launching CES.
Sending Layout Data to Schematics
After you synchronize constraint data between layout and CES, you can update schematic
designs with changes fromlayout to update your schematic design with any applicable changes.
The process of updating schematic designs with changes from layout is called back annotation.
To Send Layout Data to Schematics
From your back-end design tool, back annotate.
Note: For specific back-annotation commands, please refer to the CES constraint-driven
design-flow manual for your flow, or your layout/routing software documentation.
Related Topics
Synchronizing Constraint Data Between CES and Layout on page 236
Appendix A
CES Constraint Reference
This section provides a full constraint reference for each constraint available in CES. This
reference is organized and ordered to reflect the display of constraints on each CES Spreadsheet
page.
Using This Constraint Reference
The CES Constraint Reference includes information about each design constraint that appears
on the Trace & Via Properties, Clearances, Nets, Parts, and Noise Rules pages of the CES
Spreadsheet. Constraints in each category are listed by their default arrangement on a
spreadsheet page. By default, each constraint is available from the CES session launched from
any design tool unless otherwise specified.
Click within section CES Constraint Reference of the table of contents to view the
reference topic associated with a constraint. In the illustration below, the graphic available in
the overshoot constraint topic Dynamic Low Overshoot Max is shown.
Figure A-1. CES Constraint Reference Example Illustration
Note
For illustrative purposes, components and other board elements may appear
disproportionately large relative to PCB size.
Supported Design Components
Some constraints within this reference indicate that they are supported by design components
that may be included in your constraint-driven design flow. Please refer to the following
definitions for an understanding of each design component:
Analysis-driven routing Routing using simulation to determine how to adjust routing
to meet simulated timing constraints. This component is available in Expedition PCB.
AutoActive
Integrated place and route environment of Expedition PCB, Board

Station XE, and Board Station RE.
Using This Constraint Reference
Hazards Dynamically updated design rule checking for placement and routing
constraint information. This component is available in Expedition PCB, Board Station
XE, and Board Station RE.
High-speed routing Routing using estimation to determine how to adjust routing to
meet high-speed constraints (e.g. time of flight delay or length delay). This component
is available in Expedition PCB, Board Station XE, and Board Station RE.
ICX Pro Verify Design verification through full-board simulation of nets.
Related Topics
Defining Constraints With CES Spreadsheets on page 87
Creating Constraint Groups on page 100
Trace and Via Properties
Please refer to the trace and via property constraint reference topics that follow. These
constraints are accessible from the CES Spreadsheet Trace & Via Properties page.
Index
Displays the layer number for a board layer. This constraint is also displayed on the Clearances
page and Z-Axis Clearances page.
Constraint Type
Reference
Example
1
Type
Displays the type of printed circuit board layer (e.g. signal, power, and ground). This constraint
is also displayed on the Clearances page.
Note
When Type is Flooded Signal, the Typical Impedance constraint is calculated based on
the test width and the Trace to Plane constraint for that layer in the (Master) scheme's
(Default Rule).
Constraint Type
Reference
Example
Power
Related Constraints
Trace To Plane on page 255
Typical Impedance on page 247
Via Assignments
Defines the via assignment for a net class.
Default means that the net class is using the via assignment defaults defined in CES setup,
which are general via settings for a design. Custom indicates that the via assignment design
defaults are not being used for this net class.
This constraint is supported during high-speed routing, analysis-driven routing, and by Hazards
in the AutoActive environment.
For a definition of each supported design component, please refer to Supported Design
Components on page 237.
Constraint Type
Modifiable
Example
(default)
Related Topics
Specifying Trace and Via Rules for Rule-Area Schemes on page 118
Route
Defines whether the board layer is routed during PCB fabrication. You can define Route
individually or for all board layers of a net class.
Constraint Type
Modifiable
Related Topics
Trace Width Minimum
Defines the minimum acceptable trace width. You can define Trace Width Minimum
individually or for all board layers of a net class.
Trace Width Minimum is used whenever the router can successfully route at this trace width.
Figure A-2. Trace Width Minimum
Constraint Type
Modifiable
Example
8 mil
Related Constraints
Trace Width Expansion on page 246
Trace Width Typical on page 245
Related Topics
Trace Width Typical
Defines the typical acceptable trace width. You can define Trace Width Typical individually or
for all boards layers of a net class.
This trace width is used by the router whenever possible.
Figure A-3. Trace Width Typical
Constraint Type
Modifiable
Example
9 mil
Related Constraints
Trace Width Expansion on page 246
Trace Width Minimum on page 244
Related Topics
Trace Width Expansion
Defines the expansion, or maximum acceptable trace width.You can define Trace Width
Expansion individually or for all board layers of a net class.
When the router needs to increase trace width to satisfy routing requirements, this trace width is
used.
Figure A-4. Trace Width Expansion
Constraint Type
Modifiable
Example
10 mil
Related Constraints
Related Topics
Typical Impedance
Defines signal impedance for the Trace Width Typical constraint. When you enter a value into
the Trace Width Typical cell, impedance at this width is calculated and placed into the Typical
Impedance cell.
When calculating impedance, the following stackup properties are included as necessary:
Layer thickness
Dielectric constants
Position of plane layers
Copper thickness for metal layers
Note
When you adjust this constraint, Trace Width Typical is always updated unless you do
not have a valid stackup.
This constraint is supported during high-speed routing, analysis-driven routing, and by Hazards.
Constraint Type
Modifiable
Related Constraints
Related Topics
Diff Pair Spacing
Defines the required parallel distance between trace segments that comprise a differential pair.
You can define Diff Pair Spacing individually or for all board layers of a net class.
Figure A-5. Diff Pair Spacing
Tip: When applied in conjunction with Diff Pair Spacing, Trace Width Minimum gives
you the ability to define a smaller Diff Pair Spacing constraint. As trace width decreases,
potential aggressor net interference between differential pair nets reduces as the total
conductive surface area decreases.
This constraint is supported during high-speed routing, analysis-driven routing, and by Hazards.
Constraint Type
Modifiable
Example
0.5 mm
Related Constraints
Related Topics
Clearances
Clearances
Please refer to the clearance constraint reference topics that follow. These constraints are
accessible from the CES Spreadsheet Clearances page.
Note
By default, the clearance constraints defined in the (Defaut Rule) are used between all net
classes unless you create additional clearance rule sets and then assign them between
specific net classes.
Clearances
Index
Displays the layer number for a board layer. This constraint is also displayed on the Trace &
Via Properties page and Z-Axis Clearances page.
Constraint Type
Reference
Example
1
Clearances
Type
Displays the type of printed circuit board layer (e.g. signal, power, and ground). This constraint
is also displayed on the Trace & Via Properties page.
Constraint Type
Reference
Example
Signal
Clearances
Trace To Trace
Defines the minimum clearance distance between trace segments. You can define Trace to
Trace individually or for all board layers of a clearance rule.
Figure A-6. Trace To Trace
This constraint is supported by Hazards in the AutoActive environment.
Constraint Type
Modifiable
Example
10 mil
Related Topics
Clearances
Trace To Pad
Defines the minimumclearance distance between traces and pads. You can define Trace To Pad
Figure A-7. Trace To Pad
Constraint Type
Modifiable
Example
12 mil
Related Topics
Clearances
Trace To Via
Defines the minimum clearance distance between traces and vias. You can define Trace To Via
Figure A-8. Trace To Via
Constraint Type
Modifiable
Example
8 mil
Related Topics
Clearances
Trace To Plane
Defines the minimum clearance distance between traces and planes. You can define Trace To
Plane individually or for all board layers of a clearance rule.
Figure A-9. Trace To Plane
Constraint Type
Modifiable
Example
20 mil
Related Topics
Clearances
Trace To SMD Pad
Defines the minimum clearance distance between the pads of surface mount devices and traces.
You can define Trace To SMD Pad individually, or for all board layers of a clearance rule.
This constraint is available in CES sessions launched from Design Capture, DesignView,
DxDesigner, Board Station RE, Board Station XE, and Expedition PCB.
Figure A-10. Trace To SMD Pad
Constraint Type
Modifiable
Example
15 mil
Related Topics
Clearances
Pad To Pad
Defines the minimumclearance distance between pads. You can define Pad To Pad individually
or for all board layers of a clearance rule.
Figure A-11. Pad To Pad
Constraint Type
Modifiable
Example
10 mil
Related Topics
Clearances
Pad To Via
Defines the minimum clearance distance between pads and vias. You can define Pad To Via
Figure A-12. Pad To Via
Constraint Type
Modifiable
Example
8 mil
Related Topics
Clearances
Pad To Plane
Defines the minimum clearance distance between pads and planes. You can define Pad To
Plane individually or for all board layers of a clearance rule.
Figure A-13. Pad To Plane
Constraint Type
Modifiable
Example
20 mil
Related Topics
Clearances
Via To Via
Defines the minimum clearance distance between vias. You can define Via To Via individually
or for all board layers of a clearance rule.
Figure A-14. Via To Via
Constraint Type
Modifiable
Example
10 mil
Related Topics
Clearances
Via To Plane
Defines the minimumclearance distance between vias and planes. You can define Via To Plane
Figure A-15. Via To Plane
Constraint Type
Modifiable
Example
10 mil
Related Topics
Clearances
Via To SMD Pad
Defines the minimum clearance distance between the pads of surface mount devices and vias.
You can define Via To SMD Pad individually, or for all board layers of a clearance rule.
Figure A-16. Via To SMD Pad
Constraint Type
Modifiable
Example
15 mil
Related Topics
Clearances
Plane To Plane
Defines the minimum clearance distance between planes. You can define Plane To Plane
Figure A-17. Plane To Plane
Note
When working in an Expedition PCB flow, you can only define this constraint at the
(Master) scheme level.
Constraint Type
Modifiable
Example
20 mil
Related Topics
Clearances
Embedded Resistor To Trace
Defines the minimum clearance distance between the resistive material of embedded thick-film
resistors and traces. You can define Embedded Resistor To Trace individually or for all board
DxDesigner, Board Station XE, and Expedition PCB.
Figure A-18. Embedded Resistor To Trace
Constraint Type
Modifiable
Example
15 mil
Related Topics
Clearances
Embedded Resistor To Pad
resistors and pads. You can define Embedded Resistor To Pad individually or for all board
Figure A-19. Embedded Resistor To Pad
Constraint Type
Modifiable
Example
15 mil
Related Topics
Clearances
Embedded Resistor To Via
resistors and vias. You can define Embedded Resistor To Via individually or for all board layers
Figure A-20. Embedded Resistor To Via
Constraint Type
Modifiable
Example
15 mil
Related Topics
Clearances
Embedded Resistor To Resistor
resistors. You can define Embedded Resistor To Resistor individually or for all board layers of
a clearance rule.
Figure A-21. Embedded Resistor To Resistor
Constraint Type
Modifiable
Example
15 mil
Related Topics
Clearances
EP Mask To Trace
Defines the minimum clearance distance between the production mask of embedded thin-film
resistors and traces. You can define EP Mask To Trace individually or for all board layers of a
clearance rule.
Figure A-22. EP Mask To Trace
Constraint Type
Modifiable
Example
15 mil
Related Topics
Clearances
EP Mask To Pad
resistors and pads. You can define EP Mask To Pad individually or for all board layers of a
clearance rule.
Figure A-23. EP Mask To Pad
Constraint Type
Modifiable
Example
15 mil
Related Topics
Clearances
EP Mask To Via
resistors and vias. You can define EP Mask To Via individually or for all board layers of a
clearance rule.
Figure A-24. EP Mask To Via
Constraint Type
Modifiable
Example
15 mil
Related Topics
Clearances
EP Mask To Resistor
resistors and the resistive material of embedded thick-film resistors. You can define EP Mask
To Resistor individually or for all board layers of a clearance rule.
Figure A-25. EP Mask To Resistor
Constraint Type
Modifiable
Example
15 mil
Related Topics
Z-Axis Clearances
Z-Axis Clearances
Please refer to the z-axis clearance constraint reference topics that follow. These constraints are
accessible from the CES Spreadsheet Z-Axis Clearances page.
Note
By default, z-axis clearance constraints, even those defined in the (Defaut Z-Axis Rule),
are not used between any net classes. In order to use your values for these constraints, you
must assign z-axis clearance rule sets between specific net classes.
Z-Axis Clearances
Index
Displays the layer number for a board layer. This constraint is also displayed on the Trace &
Via Properties page and Clearances page.
Constraint Type
Reference
Example
1
Z-Axis Clearances
Trace To Trace
Defines the minimum clearance distance between trace segments located on different signal
layers. You can define Trace To Trace individually or for all board layers of a clearance rule.
Figure A-26. Trace To Trace
Constraint Type
Modifiable
Example
10 mil
Related Topics
Assigning Z-Axis Class-To-Class Clearance Rules on page 126
Z-Axis Clearances
Trace To Pad
Defines the minimum clearance distance between traces and pads located on different signal
layers. You can define Trace To Pad individually or for all board layers of a clearance rule.
Figure A-27. Trace To Pad
Constraint Type
Modifiable
Example
12 mil
Related Topics
Z-Axis Clearances
Trace To Via
Defines the minimum clearance distance between traces and vias located on different signal
layers. You can define Trace To Via individually or for all board layers of a clearance rule.
Figure A-28. Trace To Via
Constraint Type
Modifiable
Example
8 mil
Related Topics
Z-Axis Clearances
Trace To Plane
Defines the minimum clearance distance between traces and planes located on different signal
layers. You can define Trace To Plane individually or for all board layers of a clearance rule.
Figure A-29. Trace To Plane
Constraint Type
Modifiable
Example
20 mil
Related Topics
Z-Axis Clearances
Trace To SMD Pad
Defines the minimum clearance distance between the pads of surface mount devices and traces
located on internal signal layers. You can define Trace To SMD Pad individually, or for all
Figure A-30. Trace To SMD Pad
Constraint Type
Modifiable
Example
15 mil
Related Topics
Nets
Nets
Please refer to the net constraint reference topics that follow. These constraints are accessible
from the CES Spreadsheet Nets page.
Nets
# Pins
Displays the number of pins that comprise the net.
Nets Spreadsheet Group
Net Properties and All
Constraint Type
Reference
Example
2
Nets
Analog
Defines the net as analog and prevents physical nets that comprise an electrical net or
differential pair from being merged into an electrical net or differential pair. You can define
Analog individually or for all nets of a constraint class.
Constraint Type
Modifiable
Related Topics
Specifying General Net Constraints on page 155
Nets
Bus
Defines the constraint class as a bus. Nets within the constraint class should be limited to those
nets that comprise the bus.
The Bus constraint is also used to indicate that Expedition PCB should enable bus planning and
routing capabilities for a specific constraint class.
Constraint Type
Modifiable
Related Topics
Nets
Net Class
Displays the net class name to which the net belongs.
When you create a constraint template, this constraint is included.
Net Properties, Diff Pair, and Delays and Lengths, and All
Constraint Type
Reference
Nets
Template Name
Optionally, defines the constraint template to which the net is assigned. You can define
Template Name individually or for all nets of a constraint class.
Template and All
Constraint Type
Modifiable
Nets
Template Status
Displays the synchronization status of the net with regard to the current values stored in the
constraint template.
When one or more constraints values of a constraint template are modified after it was assigned
to one or more nets, the Template Status cell will indicate that the net no longer includes the
latest template values.
Template and All
Constraint Type
Reference
Related Topics
Updating a Net With Constraint Template Changes on page 202
Nets
Topology Type
Defines the topology type used for routing, which can be an automatic routing pattern, or
custom routing pattern that you define. You can define Topology Type individually or for all
You can choose from the following automatic topology types, each of which has a
corresponding Topology toolbar button:
MST (Minimum Spanning Tree) tells the router to connect the pins in any way
possible.
Chained instructs the router to connect nets from pin to pin beginning with all
sources, all loads, and then all terminators.
TShape tells the router to connect pins based upon a T-shaped physical model.
Star instructs the router to connect pins based upon a star-shaped physical model.
HTree tells the router to connect pins based upon a hierarchical tree model.
Custom/Complex When creating a custom topology type, you can define Topology
Type as either Custom or Complex. Custom is used for netline ordering that does not
include pin sets. Complex is used for netline ordering that does include pin sets. When
you begin the process of netline ordering a Custom topology, if you add a pin set, its
type is changed to Complex.
Constraint Type
Modifiable
Related Constraints
Topology Ordered on page 288
Nets
Related Topics
Specifying Topologies for Nets and Constraint Classes on page 156
Nets
Topology Ordered
For Topology Type Custom or Complex, displays whether the custom topology type has
undergone netline ordering, which is required for each user-specific topology type.
When defining netline ordering for a Complex topology, the Topology Ordered cell will not
update to state Yes until the next time you launch CES from the PCB layout system. This is
because the PCB layout system needs to analyze your usage of pin sets and fromtos to ensure
that the Complex topology is in fact fully ordered.
Constraint Type
Reference
Related Constraints
Topology Type on page 286
Nets
Stub Length Max
Defines the maximum stub length that can be created when routing this net as a custom,
complex, or chained Topology Type. You can define Stub Length Max individually or for all
When available, the actual value for this constraint is displayed in the Actual cell to its right.
Constraint Type
Modifiable
Related Topics
Specifying Topologies for Nets and Constraint Classes on page 156
Nets
# Vias Max
Defines the maximum number of vias that can be created when routing a net. This constraint
value must be between 1 and 1000. You can define # Vias Max individually or for all nets of a
constraint class.
Constraint Type
Modifiable
Related Topics
Nets
Max Restricted Layer Length External
Defines the maximum trace length that can be routed on external restricted board layers. You
can define Max Restricted Layer Length External individually or for all nets of a constraint
class.
Restricted layers are those that do not have routing enabled through the Route constraint, which
is located on the Trace & Via Properties page of the CES Spreadsheet.
Figure A-31. Cross Section of a 6-Layer PCB (External)
An external layer is a surface layer, either the top or bottom layer of the board. In the above
example, the PCB has two external layers and four internal layers.
Constraint Type
Modifiable
Related Constraints
Max Restricted Layer Length Internal on page 292
Related Topics
Nets
Max Restricted Layer Length Internal
Defines the maximum trace length that can be routed on internal restricted board layers. You
can define Max Restricted Layer Length Internal individually or for all nets of a constraint
class.
Restricted layers are those that do not have routing enabled through the Route constraint, which
is located on the Trace & Via Properties page of the CES Spreadsheet.
Figure A-32. Cross Section of a 6-Layer PCB (Internal)
An internal layer is a non-surface layer, sandwiched somewhere between the top and bottom
board layers. In the above example, the PCB has four internal layers.
Constraint Type
Modifiable
Related Constraints
Max Restricted Layer Length External on page 291
Related Topics
Nets
From To Constraints Layer
Defines the board layer on which to route a from-to that uses Topology Type Custom. You can
define From To Constraints Layer individually for each from-to.
Note
In order to apply this constraint, you must enable from-to rows on the CES Spreadsheet.
To do so, from the Filters menu, click Levels, and then click to enable FromTos.
This constraint is supported during high-speed routing, and by Hazards in the AutoActive
environment.
Constraint Type
Modifiable
Related Constraints
From To Constraints Trace Width on page 294
Related Topics
Nets
From To Constraints Trace Width
Optionally defines the trace width to which to route a from-to. You can define From To
Constraints Trace Width individually for each from-to.
From To Constraints Trace Width overrides any trace width constraints defined for a net on the
Trace &Via Properties page (e.g. Trace Width Typical). When you define FromTo Constraints
Layer without defining an override width, the trace width constraints of the net class are used.
Note
In order to apply this constraint, you must enable from-to rows on the CES Spreadsheet.
environment.
Constraint Type
Modifiable
Related Constraints
From To Constraints Z0 on page 295
Related Topics
Nets
From To Constraints Z0
Displays an impedance calculation based on the trace width override value defined in From To
Constraints Trace Width.
Note
In order to view this constraint, you must enable from-to rows on the CES Spreadsheet.
environment.
Constraint Type
Reference
Related Constraints
From To Constraints Trace Width on page 294
Nets
Jumpers Allowed
Displays whether jumpers are allowed on a net.
This constraint is available in CES sessions launched fromBoard Station XE and Board Station
RE.
This constraint is supported in the AutoActive environment.
Constraint Type
Reference
Nets
Length or TOF Delay Type
Defines the delay type for a net, which can be controlled electrically (TOF) or physically
(Length). You can define Length or TOF Delay Type individually, for pin pairs, for differential
TOF Delay Type gives you the ability to specify time of flight based upon how long it takes the
signal to propagate through the net. Length Delay Type gives you the ability to set length
constraints that instruct the router to keep the net length within a specific range.
environment.
Delays and Lengths and All
Constraint Type
Modifiable
Related Constraints
Length or TOF Delay Delta on page 305
Length or TOF Delay Max on page 299
Length or TOF Delay Min on page 298
Related Topics
Specifying Delay Rules for Nets on page 164
Nets
Length or TOF Delay Min
Defines the minimum acceptable physical routing length or signal propagation delay (e.g. time)
between design connections. You can define Length or TOF Delay Min individually, for pin
pairs, for differential pairs, or for all nets of a constraint class.
Figure A-33. Length or TOF Delay Min
environment.
Constraint Type
Modifiable
Related Constraints
Length or TOF Delay Max on page 299
Length or TOF Delay Type on page 297
Related Topics
Nets
Length or TOF Delay Max
Defines the maximumacceptable physical routing length or signal propagation delay (e.g. time)
between design connections. You can define Length or TOF Delay Max individually
individually, for pin pairs, for differential pairs, or for all nets of a constraint class.
Figure A-34. Length or TOF Delay Max
Manhattan Length
To derive maximum length from the Manhattan length computed during routing, enter a value
between 1 and 100, and follow it with a percentage sign (%). For example, to use 110% of
Manhattan length, enter 10%.
environment.
Constraint Type
Modifiable
Related Constraints
Length or TOF Delay Min on page 298
Length or TOF Delay Type on page 297
Nets
Related Topics
Nets
Length or TOF Delay Manhattan
Displays the Manhattan net length. This length is replaced with Length or TOF Delay Actual
when the net is routed.
Constraint Type
Reference
Nets
Length or TOF Delay Min Length
Displays the straight line length between two pin pairs when both components are placed. This
length is replaced with Length or TOF Delay Actual when the net is routed.
Constraint Type
Reference
Related Topics
Nets
Length or TOF Delay Match
Defines a match character or string (e.g. 1) you can use to group nets for similar length or time
of flight delay routing. You can apply Length or TOF Delay Match individually, for pin pairs,
or for differential pairs.
To duplicate the delay in a net row that has a defined match character, enter the match character
into the Length or TOF Delay Match cell of the net for which you have not defined delay.
environment.
Constraint Type
Modifiable
Related Constraints
Formulas Formula on page 307
Related Topics
Nets
Length or TOF Delay Tol
Introduces a tolerance range around the net routing delay requirements for nets that duplicate a
Length or TOF Delay Match (e.g. 1). You can also define this constraint at the constraint class
level without the pre-requirement of defining a match character or string.
environment.
Constraint Type
Modifiable
Example
5 ns
Related Topics
Matching Delay Tolerance at the Constraint Class Level on page 169
Nets
Length or TOF Delay Delta
Displays estimates for routing results that can be achieved without constraint modification.
Constraint Type
Reference
Nets
Length or TOF Delay Range
Displays the range of length or time of flight actuals for all nets and/or constraint classes that are
part of the same match group.
For example, a value of 3000:5000 indicates that the smallest actual among matched design
objects is 3000; the largest actual is 5000.
Constraint Type
Reference
Related Constraints
Length or TOF Delay Match on page 303
Nets
Formulas Formula
Defines a formula that can be used to create delay relationships between nets and pin pairs. You
can define Formulas Formula individually or for pin pairs.
environment.
Constraint Type
Modifiable
Related Constraints
Length or TOF Delay Match on page 303
Related Topics
Defining Formulas to Create Net Relationships on page 170
Nets
Formulas Violation
Displays formula violation information based on the Formulas Formula constraint.
Constraint Type
Reference
Nets
Static Low Overshoot Max
Defines the standard acceptable maximum low operating voltage (i.e. minimum) for the signal.
You can define Static Low Overshoot Max individually, for differential pairs, or for all nets of a
constraint class.
You must enter rail-relative (rr) values, where:
rr = VLmin abs for low
rr = abs VHmax for high
By defining Dynamic Low Overshoot Max, you can specify an operating voltage below this
value for a specific duration.
Figure A-35. Static Low Overshoot Max
Note
In order to use this constraint, you must have an Electrical CES license. In order to
calculate the actual value for this constraint, you must be using ICX Pro Verify within
your design flow.
This constraint is supported by Hazards and ICX Pro Verify.
Overshoot/Ringback and All
Constraint Type
Modifiable
Nets
Example
0.3 V
Related Constraints
Dynamic High Overshoot Max on page 315
Dynamic Low Overshoot Max on page 313
Static High Overshoot Max on page 311
Related Topics
Defining Overshoot and Ringback Constraints on page 177
Nets
Static High Overshoot Max
Defines the standard acceptable maximumhigh operating voltage (i.e. maximum) for the signal.
You can define Static High Overshoot Max individually, for differential pairs, or for all nets of
a constraint class.
By defining Dynamic High Overshoot Max, you can specify an operating voltage above this
value for a specific duration.
Figure A-36. Static High Overshoot Max
Note
your design flow.
Constraint Type
Modifiable
Nets
Example
0.2 V
Related Constraints
Static Low Overshoot Max on page 309
Related Topics
Nets
Dynamic Low Overshoot Max
Defines an acceptable smaller maximum low operating voltage (i.e. below minimum) for the
signal for a specific duration. You can define Dynamic Low Overshoot Max individually, or for
all nets of a constraint class.
Static Low Overshoot Max defines the standard low operating voltage. Dynamic Low
Overshoot Max give you the ability to define an exception-based low overshoot. This constraint
requires both a time and voltage value, which you separate with a : character.
Figure A-37. Dynamic Low Overshoot Max
Note
your design flow.
Constraint Type
Modifiable
Nets
Example
0.6:5 (i.e. 0.6 V for 5 ns)
Related Constraints
Related Topics
Nets
Dynamic High Overshoot Max
Defines an acceptable larger maximum high operating voltage (i.e. above maximum) for the
signal for a specific duration. You can define Dynamic High Overshoot Max individually, for
differential pairs, or for all nets of a constraint class.
Static High Overshoot Max defines the standard high operating voltage. Dynamic High
Overshoot Max give you the ability to define an exception-based high overshoot. This
constraint requires both a time and voltage value, which you separate with a : character.
Figure A-38. Dynamic High Overshoot Max
Note
your design flow.
Constraint Type
Modifiable
Nets
Example
0.4:5 (i.e. 0.4 V for 5 ns)
Related Constraints
Related Topics
Nets
Ringback Margin High Min
Defines the minimum allowed difference between the high switching threshold (Vinh) and a
ringback wave. You can define Ringback Margin High Min individually, for differential pairs,
Excessive ringback voltage can cause a device to momentarily switch out of the intended logic
state. When available, the actual value for this constraint is displayed in the Actual cell to its
right.
Note
your design flow.
Constraint Type
Modifiable
Related Topics
Nets
Ringback Margin Low Min
Defines the minimum allowed difference between the low switching threshold (Vinl) and a
ringback wave. You can define Ringback Margin Low Min individually, for differential pairs,
Excessive ringback voltage can cause a device to momentarily switch out of the intended logic
state. When available, the actual value for this constraint is displayed in the Actual cell to its
right.
Note
your design flow.
Constraint Type
Modifiable
Related Topics
Nets
Non-Monotonic Edge
Defines a non-monotonicity requirement for the rising edge, falling edge, or both signal edges.
You can define Non-Monotonic Edge individually, for differential pairs, or for all nets of a
constraint class. For example, when you set Non-Monotonic Edge to Rising, an error is reported
only if the rising signal edge is non-monotonic.
A monotonic signal edge progresses toward the opposite signal state without any digression
back to the original signal state.
Figure A-39. Non-Monotonic Edge
Note
your design flow.
Constraint Type
Modifiable
Related Topics
Nets
Single Ended Characteristic Impedance Value
Defines the single-ended characteristic impedance for net traces. You can define Single Ended
Characteristic Impedance Value individually, for differential pairs, or for all nets of a constraint
class.
When available, the minimum and maximum actual values for this constraint are displayed in
the Actual cells to its right.
When you define this constraint at the differential pair level, and the individual net level for nets
that comprise a differential pair, in the case of a conflict, the value at the differential pair level is
used.
Constraint Type
Modifiable
Related Topics
Nets
Single Ended Characteristic Impedance Tol
Introduces a tolerance range around Single Ended Characteristic Impedance Value. You can
define Single Ended Characteristic Impedance Tol individually, for differential pairs, or for all
For example, a tolerance of 5 ohms allows a Single Ended Characteristic Impedance Value of
40 ohms to tolerate a value between 35 ohms and 45 ohms.
Constraint Type
Modifiable
Related Topics
Nets
Simulation Settings
Defines the simulation settings to use when generating actual values for Nets Spreadsheet
Overshoot/Ringback and Simulated Delays groups. You can define Simulation Settings
individually, for differential pairs, or for all nets of a constraint class.
Both Simulation Stimulus and Simulation Settings affect the generation of actual values.
Note
In order to use this constraint, you must have an Electrical CES license.
Overshoot/Ringback
For Overshoot/Ringback, Simulation Settings and Simulation Stimulus generate actual values
for the following constraints:
Ringback Margin High Min on page 317
Ringback Margin Low Min on page 318
Non-Monotonic Edge on page 319
Simulated Delays
For Simulated Delays, Simulation Settings and Simulation Stimulus generate actual values for
the following constraints:
Simulated Delay Min on page 327
Simulated Delay Max on page 328
Simulated Delay Max Range on page 329
Simulated Delay Match on page 331
This constraint is supported by ICX Pro Verify.
Nets
Overshoot/Ringback, Simulated Delays, and All
Constraint Type
Modifiable
Related Constraints
Simulation Stimulus on page 324
Related Topics
Specifying Simulated Delay Rules for Nets on page 174
Nets
Simulation Stimulus
Defines the simulation stimulus to use when generating actual values for Nets Spreadsheet
Overshoot/Ringback and Simulated Delays groups. You can define Simulation Stimulus
individually, for differential pairs, or for all nets of a constraint class.
Both Simulation Stimulus and Simulation Settings affect the generation of these actual values.
Note
Overshoot/Ringback, Simulated Delays, and All
Constraint Type
Modifiable
Related Constraints
Simulation Settings on page 322
Related Topics
Nets
Simulated Delay Edge
Defines the simulated delay edge to constrain, which controls the switching time between signal
states. You can define Simulated Delay Edge individually, for differential pairs, for pin pairs, or
Figure A-40. Simulated Delay Edge
Note
Simulated Delay Edge can be one of the following signal-edge selections:
Rise Constrain the rising time between low and high signal states.
Fall Constrain the falling time between high and low signal states.
Rise:Fall Constrain both rising and falling times between signal states with unique
minimum and maximum values.
Example: Avalue of 100:120 in the Simulated Delay Min field constrains the minimum
rising delay to 100, and the minimum falling delay to 120.
Both Constrain both rising and falling times, between signal states, with the same
minimum and maximum values.
Simulated Delays and All
Constraint Type
Modifiable
Nets
Related Topics
Nets
Simulated Delay Min
Defines the minimum acceptable simulated delay for the Simulated Delay Edge value (e.g.
Rise, Fall). You can define Simulated Delay Min individually, for differential pairs, for pin
When Simulated Delay Edge is set to Rise:Fall, separate the rising and falling minimums with a
: character. To use the same minimumvalue for each switching delay, enter a single value. After
you press Enter, CES completes the constraint value by duplicating the value you entered and
inserting a colon between them.
Note
your design flow.
Constraint Type
Modifiable
Related Constraints
Simulated Delay Edge on page 325
Related Topics
Nets
Simulated Delay Max
Defines the maximum acceptable simulated delay for the Simulated Delay Edge value (e.g.
Rise:Fall, Both). You can define Simulated Delay Max individually, for differential pairs, for
pin pairs, or for all nets of a constraint class.
When Simulated Delay Edge is set to Rise:Fall, separate the rising and falling maximums with a
: character. To use the same maximum value for each switching delay, enter a single value.
After you press Enter, CES completes the constraint value by duplicating the value you entered
and inserting a colon between them.
Note
your design flow.
Constraint Type
Modifiable
Related Constraints
Related Topics
Nets
Simulated Delay Max Range
Defines a maximum acceptable range of difference between Simulated Delay Actual Min and
Simulated Delay Actual Max for the Simulated Delay Edge value (e.g. Fall, Both). You can
define Simulated Delay Max Range individually, for differential pairs, for pin pairs, or for all
You can define this constraint with or without defined Simulated Delay Min and Simulated
Delay Max constraints. When Simulated Delay Edge is set to Rise:Fall, separate the rising and
falling maximum ranges with a : character.
Note
your design flow.
Constraint Type
Modifiable
Related Constraints
Related Topics
Nets
Simulated Delay Match To
Defines the hierarchical level of matching for the Simulated Delay Match constraint. You can
match to the constraint class, net, or pin-pair level. You can define Simulated Delay Match To
individually, for differential pairs, for pin pairs, or for all nets of a constraint class.
Note
your design flow.
Constraint Type
Modifiable
Related Constraints
Related Topics
Nets
Defines the electrical net, pin pair, or constraint class to which to match the Simulated Delay
constraints (e.g. Simulated Delay Edge, Simulated Delay Min, Simulated Delay Max). You can
define Simulated Delay Match individually, for differential pairs, for pin pairs, or for all nets of
a constraint class.
When available, the minimum, maximum, and range actual values for this constraint are
displayed in the Actual cells to its right.
When matching a net to a constraint class that has unique Simulated Delay constraints for each
net, the mean of the delay range for nets in the constraint class is used as the matching simulated
delay. For example, a constraint class contains three nets with unique Simulated Delay Min
constraints of 100, 115, and 145. When assigning this constraint class to a net, the average value
of 120 is used for minimum delay.
Note
your design flow.
Constraint Type
Modifiable
Related Constraints
Simulated Delay Match To on page 330
Simulated Delay Offset on page 333
Simulated Delay Tol on page 334
Nets
Related Topics
Nets
Simulated Delay Offset
Introduces a positive or negative offset (e.g. 50 ns, -50 ns) from Simulated Delay Min and
Simulated Delay Max when matching the simulated delay of an electrical net or constraint class
(Simulated Delay Match). You can define Simulated Delay Offset individually, for differential
pairs, for pin pairs, or for all nets of a constraint class.
This offset is used for all edge rates constrained through Simulated Delay Edge of the matched
net or constraint class.
Note
Constraint Type
Modifiable
Related Constraints
Simulated Delay Tol on page 334
Related Topics
Nets
Simulated Delay Tol
Introduces a tolerance range (e.g. 5 ns) around Simulated Delay Min and Simulated Delay Max
when matching the simulated delay of an electrical net or constraint class (Simulated Delay
Match). You can define Simulated Delay Tol individually, for differential pairs, for pin pairs, or
This tolerance is used for all edge rates constrained through Simulated Delay Edge of the
matched net or constraint class.
Note
Constraint Type
Modifiable
Related Constraints
Simulated Delay Offset on page 333
Related Topics
Nets
Pair Tol Max
Defines the tolerance of the time of flight or length delay between differential pair nets. You can
define Pair Tol Max individually for each differential pair.
This constraint is supported during high-speed routing and by Hazards in the AutoActive
environment.
Diff Pair and All
Constraint Type
Modifiable
Example
5 ns
Related Topics
Nets
Convergence Tolerance Max
Defines the maximum allowed difference in trace length from pads to the point where traces
start routing differentially at the Differential Spacing constraint. You can define Convergence
Tolerance Max individually for each differential pair.
Figure A-41. Convergence Tolerance Max
environment.
Diff Pair and All
Constraint Type
Modifiable
Example
500 mil
Related Topics
Nets
Distance to Convergence Max
Defines the maximumdistance that differential traces are allowed to route before they converge
as a differential pair. Convergence is met when traces start routing at the Differential Spacing
constraint.You can define Distance to Convergence Max individually for each differential pair.
Figure A-42. Distance to Convergence Max
environment.
Diff Pair and All
Constraint Type
Modifiable
Example
5000 mil
Related Topics
Nets
Separation Distance Max
Defines the maximum allowed distance that differential traces are allowed to route at a spacing
greater or less than the Differential Spacing constraint. You can define Separation Distance
Max individually for each differential pair.
Figure A-43. Separation Distance Max
environment.
Diff Pair and All
Constraint Type
Modifiable
Example
200 mil
Related Topics
Nets
Differential Spacing
Displays the required parallel distance between trace segments that comprise a differential pair.
When separate spacing values are defined for each board layer, CES displays the values as a
colon-separated list (e.g. 5:8).
Figure A-44. Differential Spacing
environment.
Diff Pair and All
Constraint Type
Reference
Example
30 mil
Related Constraints
Diff Pair Spacing on page 248
Related Topics
Nets
Differential Impedance Target
Defines the target differential impedance. You can define this constraint for differential-pair
electrical nets, and differential pairs.
When available, the minimum and maximum actual values for this constraint are displayed in
the Actual cells to its right.
When this constraint cannot be met, Differential Spacing is used. Currently, routers do not obey
Differential Impedance Target, but Hazards displays violations.
Diff Pair and All
Constraint Type
Modifiable
Related Constraints
Differential Impedance Tolerance on page 341
Differential Spacing on page 339
Related Topics
Nets
Differential Impedance Tolerance
Introduces a tolerance range around Differential Impedance Target. You can define this
constraint for differential-pair electrical nets, and differential pairs.
When this constraint cannot be met, Differential Spacing is used. For example, to allow a 5 ohm
tolerance range against a Differential Impedance Target value of 25 ohms, enter 5. This
tolerance value specifies an acceptable impedance range of 20 to 30 ohms.
Diff Pair and All
Constraint Type
Modifiable
Related Constraints
Differential Impedance Target on page 340
Differential Spacing on page 339
Related Topics
Nets
I/O Designer I/O Standard
Defines the technology standard for an FPGA signal net. You can define I/O Designer I/O
Standard individually, or for all nets of a constraint class.
In I/O Designer, you can set this constraint through the Signals List or Pins List by modifying
the I/O Standard attribute.
Note
I/O Designer and All
Constraint Type
Modifiable
Example
PCI
Related Topics
Modifying I/O Designer FPGA Constraints on page 180
Parts
Parts
Please refer to the part constraint reference topics that follow. These constraints are accessible
from the CES Spreadsheet Parts page.
Parts
Hierarchical Path
Displays the hierarchical component path, when applicable.
Constraint Type
Reference
Parts
Part Number
Displays the part number for a design component.
Constraint Type
Reference
Parts
Qty
Displays the number of times a part is used throughout your design.
Constraint Type
Reference
Parts
Part Type
Displays the part-type value associated with a design component.
Constraint Type
Reference
Parts
Series
Defines whether a series-class component (e.g. resistor) should actually be considered a series
element, and therefore not used for electrical net generation. You can define Series for parts and
part instances.
Tip: You can also modify the series specification for a part instance from the Nets tab of
the CES Spreadsheet. To do so, expand a physical net, right-click a pin instance (e.g. R1-
1), and then click Make series or Make non-series. This change affects only the part
instance.
When an extensive electrical net includes other electrical nets that should not stay grouped into
the top-level, extensive electrical net, you can disable the Series checkbox of any
connecting/shared components to separate the electrical nets of interest. Acommon reason to do
this is when you need to define two electrical nets as a differential pair for the purpose of
constraint definition, but they do not show up as independent electrical nets (or a pre-defined
diff pair) because of their association with the comprehensive electrical net (e.g. power net).
In the following example of a missing differential pair, CES did not recognize a differential pair
that shares a series discrete component. Instead, CES interprets the design methodology of the
net as an electrical net ("^^^"). To change this recognition, you would uncheck the Series
checkbox, and then automatically or manually define the differential pair.
Constraint Type
Modifiable
Parts
IBIS Component Name
Defines the IBIS model used for a part. You can define IBIS Component Name individually, or
for all instances of a part.
IBIS models contain the greatest amount of part detail, including package information for each
pin, and represent parts most accurately. CES uses your design information to assign a default
value to this cell. In most cases it will be correct, though, it is important to understand the
process that CES uses to make the assignment. For more information, please refer to
Hierarchical Assignment Process on page 212.
Note
When both IBIS Component Name and Technology constraints are defined for a part,
IBIS Component Name is used.
Constraint Type
Modifiable
Related Constraints
Technology on page 350
Related Topics
Overriding IBIS Values on page 217
Parts
Technology
Defines the technology model used for a part. You can define Technology individually, or for
all instances of a part.
Because they model parts broadly by technological classification, technology models do not
provide as much detail as IBIS models. A common difference between technology models and
IBIS models is that technology models include information for each pin type, while IBIS
models include information for each pin.
Note
When both IBIS Component Name and Technology constraints are defined for a part,
IBIS Component Name is used.
Constraint Type
Modifiable
Related Constraints
IBIS Component Name on page 349
Related Topics
Parts
Value
Defines the electrical value associated with a discrete part, which can be resistance, inductance,
or capacitance. You can define Value individually or for all instances of a part.
The Value constraint can be used for two-pin resistors, capacitors, inductors, Thevenin and AC
terminators, and passive modules that contain multiple two-pin slots/gates.
Note
When assigning a Value constraint to a discrete part row, its reference designator (e.g. R,
L, C), must be defined. For more information, please refer to To Specify Discrete
Component Prefixes on page 57.
Constraint Type
Modifiable
Related Topics
Overriding IBIS Values on page 217
Parts
IBIS Pin Type
Displays the IBIS pin type for a pin instance.
IBIS Pin Type comes from library information in IBIS Component Name.
Constraint Type
Reference
Related Constraints
IBIS Component Name on page 349
Parts
Schematic Pin Type
Displays the schematic pin type for a pin instance.
Constraint Type
Reference
Parts
Topology Pin Type
Defines the chaining pin type for a pin instance. Chaining pin types are source, load, or
terminator (i.e. S, L, T).
This constraint is supported during high-speed routing and in the AutoActive environment.
Constraint Type
Modifiable
Parts
Pin Package Length
Defines a pin's internal package length between the substrate and dielectric layers of the
component. This constraint is commonly used to define wire bonding length.
This constraint is supported during high-speed routing and in the AutoActive environment.
Constraint Type
Modifiable
Parts
Thermal Power Dissipation
Defines a parts power dissipation as a subset of the total amount of power needed to run the
component.
Constraint Type
Modifiable
Example
1 W
Parts
Thermal Power Scaling Factor
Defines a part instances scaling factor with regard to power dissipation.
Constraint Type
Modifiable
Example
1
Parts
Thermal Theta-jc
Defines a parts junction-to-casing thermal resistance. This is also commonly referred to as die-
to-package heat resistance.
Constraint Type
Modifiable
Example
7 degC/watt
Parts
Thermal Casing Temperature Limit
Defines a parts maximum allowable temperature for the component casing or package.
Constraint Type
Modifiable
Example
60 degC
Parts
Thermal Junction Temperature Limit
Defines a parts maximum allowable temperature for component junctions. A component
junction is also commonly referred to as a die.
Constraint Type
Modifiable
Example
70 degC
Parts
I/O Designer I/O Standard
Displays the defined technology standard for an FPGA signal net. When on the CES
Spreadsheet Nets page, you can define I/O Designer I/O Standard individually, or for all nets of
a constraint class.
In I/O Designer, you can set this constraint through the Signals List or Pins List by modifying
the I/O Standard attribute.
Note
Constraint Type
Reference
Example
PCI
Related Topics
Modifying I/O Designer FPGA Constraints on page 180
Noise Rules
Noise Rules
Please refer to the noise rule constraint reference topics that follow. These constraints are
accessible from the CES Spreadsheet Noise Rules page.
Noise Rules
Noise Type
Defines the noise type for a specific parallelism rule and/or Crosstalk Max constraint and
Crosstalk Level.
Noise Type can be either net-to-net or class-to-class.
environment.
Constraint Type
Modifiable
Related Constraints
Diff Pair Spacing on page 248
Related Topics
Noise Rules
Constraint Class or Electrical Net Name Victim
Defines the victim constraint class or electrical net of the aggressor-victim relationship.
You can use these relationships to define both crosstalk and parallelism rules.
environment.
Constraint Type
Modifiable
Related Constraints
Crosstalk Level on page 371
Crosstalk Max on page 367
Parallelism Rule on page 366
Related Topics
Noise Rules
Constraint Class or Electrical Net Name Aggressor
Defines the aggressor constraint class or electrical net of the aggressor-victim relationship.
You can use these relationships to define both crosstalk and parallelism rules.
environment.
Constraint Type
Modifiable
Related Constraints
Parallelism Rule on page 366
Related Topics
Noise Rules
Parallelism Rule
Defines the parallelism rule for a class-to-class or net-to-net parallelism relationship.
The ParallelismRule constraint can be one of the parallelismrules you defined previously. You
can also create a new parallelism rule by selecting New in the cell for this constraint.
environment.
Constraint Type
Modifiable
Related Topics
Noise Rules
Crosstalk Max
Defines the maximum acceptable crosstalk that a net or all nets within a constraint class can be
subjected to as victim nets. You can define Crosstalk Max individually or for all nets of a
constraint class.
Crosstalk results when another net (i.e. aggressor) causes electromagnetic interference on a
victim net. In the following illustration, the electromagnetic field produced by net A is strong
enough to interfere with net B.
Figure A-45. Crosstalk Max
In the CES Spreadsheet, you define aggressor nets using Constraint Class or Electrical Net
Name Aggressor. You define victim nets using Constraint Class or Electrical Net Name Victim.
Note
In order to calculate the simulation actual for this constraint, you must be using ICX Pro
Verify within your design flow.
environment.
Constraint Type
Modifiable
Related Constraints
Constraint Class or Electrical Net Name Aggressor on page 365
Constraint Class or Electrical Net Name Victim on page 364
Noise Rules
Related Topics
Noise Rules
Crosstalk Est Actual
Displays the actual value for Crosstalk Max based on AutoActive calculations.
environment.
Constraint Type
Reference
Related Constraints
Noise Rules
Crosstalk Sim Actual
Displays the actual value for Crosstalk Max based on ICX Pro Verify calculations.
Note
In order to calculate this actual value, you must be using ICX Pro Verify within your
design flow.
Constraint Type
Reference
Related Constraints
Noise Rules
Crosstalk Level
Defines the signal state of the victim net in a crosstalk relationship.
You can define Crosstalk Level using one of the following choices:
High & Low Require Crosstalk Max to be met for both high and low signal states.
High The victim net is on (i.e. in its high state). The voltage level is at or above the
high threshold (e.g. 5.1 V).
Low The victimnet is off (i.e. in its low state). The voltage level is at or below the low
threshold (e.g. 0.9 V).
Tristate Require Crosstalk Max to be met for just tristate signal states. During tristate,
the victim net is off, but a small voltage still flows from the receiver to ground (e.g. 0.5
V).
High & Tristate Require Crosstalk Max to be met for both high and tristate signal
states. During tristate, the victim net is off, but a small voltage still flows from the
receiver to ground (e.g. 0.5 V).
Low&Tristate Require Crosstalk Max to be met for both lowand tristate signal states.
During tristate, the victim net is off, but a small voltage still flows from the receiver to
ground (e.g. 0.5 V).
All Require Crosstalk Max to be met for all signal states.
Constraint Type
Modifiable
Related Constraints
Constraint Class or Electrical Net Name Aggressor on page 365
Constraint Class or Electrical Net Name Victim on page 364
Related Topics
Noise Rules
Crosstalk Auto Route Usage
Defines the noise rule type that should be used during auto routing.
This constraint is applicable only when a net-to-net or class-to-class relationship includes both a
Parallelism Rule and a Crosstalk Max value.
This constraint is supported by AutoActive.
Constraint Type
Modifiable
Example
Crosstalk
Related Topics
373
A B F G D C E H I J K L M N O P Q R S T U V X W Y Z
Constraint Editor System (CES) Users Manual, EE 7.9
Symbols
# Pins, 280
# Vias Max, 290
$change_design_property, 51, 52
(Minimum) scheme, 117
Numerics
2-pin, 58
A
Analog, 281
Assigning, 126
Auto bus, 150
B
Back-end, 227
Before you begin, 47
Board Architect, 46
Board Station RE, 46
Board Station XE, 46
Board Station XE Design Flow
CES synchronization, 228
Bus, 282
Bus constraint classes, 150
C
Capture net constraints, 197
CES, 45
Ces_RE.txt, 116
Clearance rule sets
Assign, 125
Create, 120
Clearances, 249
Colors, 61
Command quick-reference, 14
Commands, 14
Component pin pairs, 161
Concurrent design, 46
Constraint
Classes, 147
Conflicts, 232
Data, 87
Groups, 100
Templates, 197
Constraint class
Add nets, 149
Auto bus, 150
Copy, 153
Create, 147
Delete, 153
Hierarchy, 147
Rename, 148
Constraint Class or Electrical Net Name
Aggressor, 365
Constraint Class or Electrical Net Name
Victim, 364
Constraint Editor System (CES), 45
Constraint quick-reference, 27
Constraint Reference, 237
Constraint template
Apply, 199
Convergence Tolerance Max, 336
Cross probing, 55
Cross select, 55
Crosstalk Auto Route Usage, 372
Crosstalk Est Actual, 369
Crosstalk Level, 371
Crosstalk Max, 367
Crosstalk rules, 188
Crosstalk Sim Actual, 370
Customization, 73
D
Default
Rules, 136
Tolerances, 56
Delay
Calculations, 166
Default value, 167
Rules, 164
Delete
Index
Constraint class, 153
Net class, 144
Rule-area scheme, 136
Design
Preferences, 56
Reuse, 203
Setup, 56
Design Architect, 46
Design Capture, 46
Design-flow manuals, 227
DesignView, 46
Diff Pair Spacing, 248
Differential Impedance Target, 340
Differential Impedance Tolerance, 341
Differential pair
Assign rules, 194
Define automatically, 192
Define manually, 191
Delete, 192
Diff_Pin, 194
Differential Spacing, 339
Discrete component prefixes, 57
Discrete pin pairs, 161
Display
Settings, 56
Units, 62
Distance to Convergence Max, 337
DxDesigner, 45
Dynamic High Overshoot Max, 315
Dynamic Low Overshoot Max, 313
Dynamic overshoot, 179
E
EBD pin pairs, 163
Electrical
Preferences, 57
Rules, 147
Units, 64
Embedded Resistor to Pad, 265
Embedded Resistor to Resistor, 267
Embedded Resistor to Trace, 264
Embedded Resistor to Via, 266
Embedded resistors, 123
Engineering format, 65
EP Mask to Pad, 269
EP Mask to Resistor, 271
EP Mask to Trace, 268
EP Mask to Via, 270
Exit, 55
Expedition PCB, 45
Export
Constraint Templates, 203
Constraints, 205
F
Filters, 97, 99
Find, 94
Fonts, 61
Formulas, 170
Formulas Formula, 307
Formulas Violation, 308
FPGA constraints, 180
From To Constraints Layer, 293
From To Constraints Trace Width, 294
From To Constraints Z0, 295
From-tos, 156
Front-end, 45
G
General
Clearance rules, 133
Options, 56
Preferences, 56
Global rules, 117
Ground nets, 58
GUI quick-reference, 20
I
I/O Designer I/O Standard, 342, 361
IBIS Component Name, 349
IBIS Pin Type, 352
Icons, 90
ICX Pro Explorer, 220
Import constraints, 205
Improve design accuracy, 45
Index (Clearances), 250
Index (Trace and Via Properties), 240
Index (Z-Axis Clearances), 273
Intellectual property, 45
Interdigitated capacitors, 124
Interface quick-reference, 20
J
Jumpers Allowed, 296
K
Keyin netlist, 46
L
Layer differences, 209
Layout, 227
Length or TOF Delay Delta, 305
Length or TOF Delay Manhattan, 301
Length or TOF Delay Match, 303
Length or TOF Delay Max, 299
Length or TOF Delay Min, 298
Length or TOF Delay Min Length, 302
Length or TOF Delay Range, 306
Length or TOF Delay Tol, 304
Length or TOF Delay Type, 297
Libraries, 198
M
Manhattan length, 165
Mask, 125
Matching delay, 167
Max Restricted Layer Length External, 291
Max Restricted Layer Length Internal, 292
Mezzanine capacitors, 124
MGC_ENABLE_CES, 52
Monotonic Edge, 319
Multiple loads, 157
N
Navigator, 74
Net Class, 283, 284, 285
Net class
Add nets, 141
BA or DA schematic nets, 142
Copy, 144
Create, 139
Delete, 144
Determine assignments, 143
Hierarchy, 139
Power nets, 142
Rename, 140
Net class assignments, 143
Net line ordering, 156
Nets, 279
Noise Rules, 362
Noise Type, 363
Notation, 64
O
Options, 56
Output, 74
Overshoot, 177
Overwrite log file, 116
P
Pad to Plane, 259
Pad to Via, 258
Pair Tol Max, 335
Parallelism, 183
Parallelism mode, 56
Parallelism Rule, 366
Parallelism rules, 184
Assign, 186
Parallelism rules hierarchy, 184
Part Number, 345
Part Type, 347
Part-model assignments, 211
Parts, 343
PCB, 45
Pin Package Length, 355
Pin pairs, 156
Plane to Plane, 263
Power nets, 58, 142
Precision, 63
Production mask, 125
Q
Qty, 346
R
Reuse, 203
Ringback, 177
Ringback Margin High Min, 317
Ringback Margin Low Min, 318
Roll back, 113
Route, 243
Rule-area schemes, 117
Rules, 183
S
Same constraints
Electrical rules, 153
Physical rules, 144
Save, 115
Schematic, 227
Schematic Pin Type, 353
Schemes, 117
Screen-printed capacitors, 124
Scripting, 74
Scripts, 79
Search, 94
Separation Distance Max, 338
Series, 348
Settings, 56
Signal edge rates, 174
Signal integrity exploration, 220
Simulated Delay Edge, 325
Simulated Delay Match, 331
Simulated Delay Match To, 330
Simulated Delay Max, 328
Simulated Delay Max Range, 329
Simulated Delay Min, 327
Simulated Delay Offset, 333
Simulated delay rules, 174
Simulated Delay Tol, 334
Simulation options, 65
Simulation Settings, 322
Simulation Stimulus, 324
Single Ended Characteristic Impedance Tol,
321
Single Ended Characteristic Impedance Value,
320
SMD Pad to Trace, 256, 278
SMD Pad to Via, 262
Spreadsheet icons, 90
Spreadsheet pages, 88
Stackup, 209
Stackup layers, 184
Start CES, 54
Static High Overshoot Max, 311
Static Low Overshoot Max, 309
Static overshoot, 177
Status Bar, 74
Stub Length Max, 289
T
Technology, 350
Thermal Casing Temperature Limit, 359
Thermal Junction Temperature Limit, 360
Thermal Power Dissipation, 356
Thermal Power Scaling Factor, 357
Thermal Theta-jc, 358
Thick-film resistors, 123
Thin-film resistors, 123
Toolbars, 74
Topology Ordered, 288
Topology Pin Type, 354
Topology Type, 286
Trace and Via Properties, 239
Trace and via rules, 118
Trace to Plane, 255, 277
Trace to Trace, 252, 274
Trace to Via, 254, 276
Trace Width Expansion, 246
Trace Width Minimum, 244
Trace Width Typical, 245
Type, 241, 251
Typical Impedance, 247
U
Units, 62
User interface quick reference, 20
V
Validate constraints, 108
Value, 351
Via Assignments, 242
Via rules, 118
Via to Plane, 261
Via to Via, 260
W
Window customization, 73
Z
Z-axis clearance rule sets
Assign, 126
Create, 120
Z-Axis Clearances, 272
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