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Digital Integrated Circuit (IC) Layout and Digital Integrated Circuit (IC) Layout and
Design Design - - Week 3, Lecture 5 Week 3, Lecture 5
! http://www.ee.ucr.edu/~rlake/EE134.html
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Reading and Reading and Prelab Prelab
"Week 1 - Read Chapter 1 of text.
"Week 2 - Read Chapter 2 of text.
"Week 3 - Read Chapter 3 of text.
"Prelab - Lab 1.
! Read insert A of text, pp. 67 - 71.
! The lab will make more sense if you read this
before lab.
! There is nothing to turn in.
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Agenda Agenda
"Last Lecture
! Design rules
! Layout and Design
! Ties to V
DD
and GND
! Padframes
! Pin Packages
"Todays Lecture
! Contacts
! Basic MOS transistor operation
! Large-signal MOS model for manual analysis
! The CMOS inverter
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Course Emphasis / Design Styles Course Emphasis / Design Styles
"Physical design of CMOS digital ICs
"Application Specific IC (ASIC)
! Full Custom (What we are doing)
Most flexible approach
Higher speed
Smaller designs
Expensive
Requires device-level (i.e. transistor level) knowledge
Push limits of a technology - must understand
parasitics: stray C, L, pn jns., BJTs, breakdown,
stored charge, latch-up, etc.
Used for high-volume chips - !"processors &
memory
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Design Styles (cont.) Design Styles (cont.)
"ASIC (cont.)
! Standard Cell
Logic gate level
Low volume
Quick turnaround
Lower density
! Gate Array (FPGA)
Lowest density - speed - cost.
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Flowchart Flowchart
Define circuit specs
Circuit Schematic
Circuit Simulation
Layout
Parasitic Extraction (R,C)
Re-simulate with Parasitics
Prototype Fabrication
Test and Evaluate
Production
Meet Specs?
Meet Specs?
Meet Specs?
No
No
Yes No
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Tie n Tie n- -well to VDD and Substrate to well to VDD and Substrate to
Ground Ground
A A
n
p-substrate Field
Oxide p
+
n
+
In
Out
GND V
DD
(a) Layout
A A
V
DD
n
+
V
n
+ p
+
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Reason for GND and V Reason for GND and V
DD DD
Ties Ties
n
p-substrate
p
+
n
+
V
DD
n
+
V
out
n
+
p
+
p-substrate
Parasitic Diodes
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Contacts to Silicon Contacts to Silicon
"Ohmic Contacts
! Metal on highly doped n
+
or p
+
Si.
! What you want to pin the substrate to ground or
the n-well to V
DD
.
"Schottky Contacts (we wont use these)
! Metal on lightly doped n or p Si.
! Creates a Schottky diode which has an I-V curve
similar to a p-n junction diode.
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Ohmic Ohmic contact contact
"Metal on n
+
or p
+
Si.
"Simple picture:
"Need heavy doping to get the ultra short
screening length needed for an OHMIC
contact.
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Schottky Schottky Contact Contact
"Metal on n or p Si.
"Simple picture:
"Light n or p doping gives long screening
length giving Schottky Barrier.
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Ohmic Ohmic Contacts for Voltage Pinning Contacts for Voltage Pinning
"Ohmic contact to the n-well
"You need the
! Active and Select to
define the n+
region.
! Contact to put hole
in thick passivation
oxide / nitride so
that the metal
contacts the Si.
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Ohmic Ohmic Contacts for Voltage Pinning Contacts for Voltage Pinning
"Ohmic contact to the p-substrate
"You need the
! Active and Select to define
the p+ region.
! Contact to put hole in
thick passivation oxide /
nitride so that the metal
contacts the Si.
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Pin n Pin n- -well to V well to V
DD DD
and p and p- -substrate to GND substrate to GND
M1
V
DD
M1
GND
Power
Bus
Ground
Bus
PMOS
NMOS
p+
p+
n+
n-well
n+
n+
p+
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The Active Layer The Active Layer
"Cut in the Field Oxide (FOX) to get down to
the Si.
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Active and Select Layers Active and Select Layers
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Active and Select Layers (cont) Active and Select Layers (cont)
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4 Concepts to Remember: 4 Concepts to Remember:
"Need to put down an n+ region on the n-well
to make an ohmic contact to the n-well.
"Need to put down a p+ region on the p-
substrate to make an ohmic contact to the
p-substrate.
"These are your active / select layers.
"Finally, you need a contact layer to drill
through the thick oxide / nitride passivation.
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BAD MOS Layout BAD MOS Layout
"DO NOT DO THIS!!!!!!!
active - hole cut in FOX
n+ select
Self-aligned process
The Poly gate serves as an implant mask during the n+
implant.
There is no gap between the source/gate and drain/gate.
poly-gate
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Outline Outline
"MOS Transistor
! Basic Operation
! Modes of Operation
! Deep sub-micron MOS
"CMOS Inverter
Ch. 3
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What is a Transistor? What is a Transistor?
V
GS

#
V
T
R
on
S
D
A Switch!
An MOS Transistor
D S
G
V
GS
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Switch Model of CMOS Transistor Switch Model of CMOS Transistor
D S
G
V
GS
S
R
on
D S
D
|V
GS
| < |V
T
|
|V
GS
| > |V
T
|
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Transistor Circuit Symbols Transistor Circuit Symbols
"NMOS
Body (p-Si substrate)
Drain
Source
Gate
D
S
G B = S #
D
S
G
We always want
D
S
G
Body tied to Source
B
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NMOS Body Terminal (B) NMOS Body Terminal (B)
M1
V
DD
M1
GND
PMOS
NMOS
p+
p+
n+
n-well
n+
n+
p+
S
D
B
D
S
G B = S = GND
Circuit
Schematic
Layout
A transistor is a 4
terminal device.
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Transistor Circuit Symbols Transistor Circuit Symbols
"PMOS
Body (n-well)
Drain
Source
Gate
D
S
G B = S #
We always want
D
S
G
Body tied to Source
B
V
DD
D
S
G
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PMOS Body Terminal (B) PMOS Body Terminal (B)
D
S = V
DD
G B = S = V
DD
M1
V
DD
M1
GND
PMOS
NMOS
p+
p+
n+
n-well
n+
n+
p+
S
D
B
Layout
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NMOS and PMOS NMOS and PMOS
"PMOS is complementary to NMOS
"Turn it upside down and switch all signs of
voltages, V
SD
#V
DS
, V
GS
#V
SG
.
V
GS
> 0
D
S
G
+
-
NMOS
-
V
SG
> 0
D
S
G
+
PMOS
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Outline Outline
"MOS Transistor
! Basic Operation
! Modes of Operation
! Deep sub-micron MOS
"CMOS Inverter
Ch. 3
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Threshold Voltage: Concept Threshold Voltage: Concept
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The Threshold Voltage The Threshold Voltage
q
T k
B
F
$
%
%
&
'
(
(
)
*
$
T
i
A
T
n
N
ln -
+
+ +
2+
F
! -0.6V for p-type substrates
, is the body factor
V
T0
= 0.76 V (NMOS)
0.95 V (PMOS)
AMI C5 process
Fermi Potential
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The Body Effect The Body Effect
V
TO
reverse body bias
0 -0.5 -1.0 -1.5 -2 -2.5
V
SB
0.4
0.5
0.6
0.7
0.8
0.9
V
T
(
V
)
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The Drain Current The Drain Current
"Charge in the channel is controlled by the
gate voltage:
"Drain current is proportional to charge x
velocity:
- .
T GS ox i
V x V V C x Q " " " $ ) ( ) (
ox
ox
ox
t
C
/
$
dx
dV
x x v
W x Q x v I
n n n
i n D
! 0 ! $ 1 " $
1 1 " $
) ( ) (
) ( ) (
v
n
= velocity; W =channel width; 0 =electric field; !
n
=mobility
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The Drain Current The Drain Current
"Combining velocity and charge:
"Integrating along the length of the channel
from source to drain:
2 3 dV V V V W C dx I
T GS ox n D
1 " " 1 1 1 $ 1 !
2 3
4 4
1 " " 1 1 1 $ 1
DS G
V
T GS ox n
L
D
dV V V V W C dx I
0 0
!
ox
ox n
ox n n
t
C k
/ !
!
1
$ 1 $ 5
2 3
6
7
8
9
:
;
" 1 " 1 1 1 $
2
2
DS
DS T GS ox n D
V
V V V
L
W
C I !
n
+
n
+
D
S
G
V
GS
x L
V(x)
+
V
DS
I
D
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Outline Outline
"MOS Transistor
! Basic Operation
! Modes of Operation
! Deep sub-micron MOS
"CMOS Inverter
Ch. 3
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Transistor in Linear Mode Transistor in Linear Mode
n
+
n
+
p-substrate
D
S
G
B
V
GS
x L
V(x)
+
V
DS
I
D
V
GS
> V
DS
+ V
T
Device turned on (V
GS
> V
T
)
2 3
6
7
8
9
:
;
" 1 " 1 1 1 $
2
2
DS
DS T GS ox n D
V
V V V
L
W
C I !
V
DS
< V
GS
- V
T
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Transistor in Saturation Transistor in Saturation
n+ n+
S
G
V
GS
D
V
DS
>V
GS
- V
T
V
GS
- V
T
+ -
Pinch-off
V
T
< V
GS
< V
DS
+ V
T
V
DS
> V
GS
- V
T
2 3
6
7
8
9
:
;
" 1 " 1 1 1 $
2
2
DS
DS T GS ox n D
V
V V V
L
W
C I !
2 3
2
2
T GS
ox n
D
V V
L
W C
I " 1 1
1
$
!
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"For V
DS
> V
GS
- V
T
, the drain current
saturates:
"Including channel-length modulation:
2 3
2
2
T GS
ox n
D
V V
L
W C
I " 1 1
1
$
!
Saturation Saturation
2 3 2 3
DS T GS
ox n
D
V V V
L
W C
I <
!
= 1 " 1 1
1
$ 1
2
2
0 0.5 1 1.5 2 2.5
0
1
2
3
4
5
6
x 10
-4
V
DS
(V)
I
D
(
A
)
slope = < V
DS
= V
DS
/V
A
V
A
= 1/< = Early voltage
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Modes of Operation Modes of Operation
"Cutoff:
"Resistive or Linear:
"Saturation
V
GS
< V
T
I
D
= 0
V
DS
< V
GS
- V
T
&
V
GS
> V
T
V
DS
> V
GS
- V
T
V
GS
> V
T
2 3
2
2
T GS
ox n
D
V V
L
W C
I " 1 1
1
$
!
2 3
6
7
8
9
:
;
" 1 " 1 1 1 $
2
2
DS
DS T GS ox n D
V
V V V
L
W
C I !
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Current Current- -Voltage Relations Voltage Relations
A good A good ol ol Transistor Transistor
Quadratic
Relationship
0 0.5 1 1.5 2 2.5
0
1
2
3
4
5
6
x 10
-4
V
DS
(V)
I
D
(
A
)
VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
Resistive Saturation
V
DS
= V
GS
- V
T
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A model for manual analysis A model for manual analysis
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Outline Outline
"MOS Transistor
! Basic Operation
! Modes of Operation
! Deep sub-micron MOS
"CMOS Inverter
Ch. 3
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Current Current- -Voltage Relations Voltage Relations
The Deep The Deep- -Submicron Era Submicron Era
Linear
Relationship
-4
V
DS
(V)
0 0.5 1 1.5 2 2.5
0
0.5
1
1.5
2
2.5
x 10
I
D
(
A
)
VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
Early Saturation
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Velocity Saturation Velocity Saturation
0 (V/m)
0
c
=1.5
>
n
(
m
/
s
)
>
sat
=10
5
Constant mobility (slope =)
Constant velocity
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Velocity Saturation Velocity Saturation
I
D
Long-channel device
Short-channel device
V
DS
V
DSAT
V
GS
- V
T
V
GS
= V
DD
Saturates sooner
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I I
D D
versus V versus V
GS GS
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I I
D D
versus V versus V
DS DS
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Including Velocity Saturation Including Velocity Saturation
!
n
chosen empirically
so that
sat
v
c n
$
2
0 !
#!
n
depends on the
SPICE model.
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Simple Cheesy Derivation for Velocity Simple Cheesy Derivation for Velocity
Saturation and Linear Dependence on Saturation and Linear Dependence on
V V
GS GS
2 3
D D
TH GS ox
velocity
n D
v W I
x V V V C
dx
dV
W I
D
2
2
) (
?
!
?

density) (charge
$
" " 5 $
! ! ! ! " ! ! ! ! # $
" # $
By definition,
dx dV
v v
n
$ @
0
!
2 3
sat DS,
sat
dx dV
V V V C
dx
dV v
W I
TH GS ox D
" " 5 $
2 3
sat DS, sat
V V V C v W I
TH GS ox D
" " 5 $
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I I
D D
versus V versus V
DS DS
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Regions of Operation Regions of Operation
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A Unified Model for Manual Analysis A Unified Model for Manual Analysis
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Simple Model versus SPICE Simple Model versus SPICE
0 0.5 1 1.5 2 2.5
0
0.5
1
1.5
2
2.5
x 10
-4
V
DS
(V)
I
D
(
A
)
Velocity
Saturated
Linear
Saturated
V
DSAT
=V
GT
V
DS
=V
DSAT
V
DS
=V
GT
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A PMOS Transistor A PMOS Transistor
-2.5 -2 -1.5 -1 -0.5 0
-1
-0.8
-0.6
-0.4
-0.2
0
x 10
-4
V
DS
(V)
I
D
(
A
)
Assume all variables
negative!
VGS = -1.0V
VGS = -1.5V
VGS = -2.0V
VGS = -2.5V
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Sub Sub- -Threshold Conduction Threshold Conduction
(Cut (Cut- -off) off)
0 0.5 1 1.5 2 2.5
10
-12
10
-10
10
-8
10
-6
10
-4
10
-2
V
GS
(V)
I
D
(
A
)
V
T
Linear
Exponential
Quadratic
Typical values for S:
60 .. 100 mV/decade
The Slope Factor
ox
D
nkT
qV
D
C
C
n e I I
GS
= $ 1 , ~
0

S is AV
GS
for I
D2
/I
D1
=10
V
DS
= V
DD
S = inverse subtheshold slope
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Subthreshold Subthreshold
"Inverse sub-threshold slope (S)
! Ideal value @ T=300K, n=1,
! For each 60 mV of V
GS
, the current drops by a
factor of 10. This is the best that you can do.
! For V
DD
= 0.4V, the maximum on-off current ratio
that you can have at T=300K is
! At 373K, the ratio is
2 3
decade
mV
10 ln 60 $ $
q
T k
S
B
6
60
400
10 6 . 4 10 B $
5
74
400
10 3 . 2 10 B $
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Subthreshold Subthreshold
"Current in subthreshold
2 3
DS
q T k
V
q T nk
V
S D
V e e I I
B
DS
B
GS
< =
%
%
%
&
'
(
(
(
)
*
" $
"
1 1
/ /
2 3
10

10 ln
log
10
ln
1 1
1 1
q
T nk
S
dV
dI
I dV
I d
S
B
GS
DS
DS GS
DS
$
%
%
&
'
(
(
)
*
$
%
%
&
'
(
(
)
*
@
" "
"Inverse subthreshold slope definition
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Subthreshold Subthreshold Concepts Concepts
"FETs turn off exponentially.
2 3
%
C
D
E
$ $
$
C 100 @ mV/dec
C 27 @ mV/dec
10 ln
o
o
74
60
1 n
B
q
T nk
S
"Inverse subthreshold slope, S (mV/dec), is
the figure of merit that tells how well they
shut off.
1.5 typically and F # 1 n
"The maximum possible on-off current ratio
is
S V
off
on
DD
I
I
10 | $
max
"2018 ITRS node has V
DD
= 0.4V - hence the
static power problem.
Know this if you are in an interview with a semiconductor co.
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Transistor Model Transistor Model
for Manual Analysis for Manual Analysis