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Chapter 1 - Introduction

1.17 FIELD-PROGRAMMABLE GATE ARRA! RAM


A Field-programmable Gate Array (FPGA) is an integrated circuit designed to be
configured by the customer or designer after manufacturinghence "field-programmable". The
FPGA configuration is generally specified using a hardare description language (!"#)$ similar
to that used for an application-specific integrated circuit (A%&') (circuit diagrams ere
pre(iously used to specify the configuration$ as they ere for A%&'s$ but this is increasingly
rare).
FPGAs can be used to implement any logical function that an A%&' could perform. The
ability to update the functionality after shipping$ partial re-configuration of the portion of the
design)*+ and the lo non-recurring engineering costs relati(e to an A%&' design
(notithstanding the generally higher unit cost)$ offer ad(antages for many applications.
FPGAs contain programmable logic components called "logic bloc,s"$ and a hierarchy of
reconfigurable interconnects that allo the bloc,s to be "ired together"somehat li,e many
(changeable) logic gates that can be inter-ired in (many) different configurations. #ogic bloc,s
can be configured to perform comple- combinational functions$ or merely simple logic gates li,e
A." and /01. &n most FPGAs$ the logic bloc,s also include memory elements$ hich may be
simple flip-flops or more complete bloc,s of memory.
&n addition to digital functions$ some FPGAs ha(e analog features. The most common
analog feature is programmable sle rate and dri(e strength on each output pin$ alloing the
engineer to set slo rates on lightly loaded pins that ould otherise ring unacceptably$ and to
set stronger$ faster rates on hea(ily loaded pins on high-speed channels that ould otherise run
too slo.
Another relati(ely common analog feature is differential comparators on input pins
designed to be connected to differential signaling channels. A fe "mi-ed signal FPGAs" ha(e
integrated peripheral Analog-to-"igital 'on(erters (A"'s) and "igital-to-Analog 'on(erters
("A's) ith analog signal conditioning bloc,s alloing them to operate as a system-on-a-chip.
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Chapter 1 - Introduction
%uch de(ices blur the line beteen an FPGA$ hich carries digital ones and 2eros on its
internal programmable interconnect fabric$ and field-programmable analog array (FPAA)$ hich
carries analog (alues on its internal programmable interconnect fabric.
1.1" FPGA DE#IG$ A$D PROGRAMMI$G
To define the beha(ior of the FPGA$ the user pro(ides a hardare description language
(!"#) or a schematic design. The !"# form is more suited to or, ith large structures
because it3s possible to 4ust specify them numerically rather than ha(ing to dra e(ery piece by
hand. !oe(er$ schematic entry can allo for easier (isuali2ation of a design.
Then$ using an electronic design automation tool$ a technology-mapped net list is
generated. The net list can then be fitted to the actual FPGA architecture using a process called
place-and-route$ usually performed by the FPGA company3s proprietary place-and-route
softare.
The user ill (alidate the map$ place and route results (ia timing analysis$ simulation$
and other (erification methodologies. 0nce the design and (alidation process is complete$ the
binary file generated (also using the FPGA company3s proprietary softare) is used to
(re)configure the FPGA.
Going from schematic5 !"# source files to actual configuration6 The source files are fed
to a softare suite from the FPGA5'P#" (endor that through different steps ill produce a file.
This file is then transferred to the FPGA5'P#" (ia a serial interface (7TAG) or to an e-ternal
memory de(ice li,e an 88P109.
The most common !"#s are :!"# and :erilog $ although in an attempt to reduce the
comple-ity of designing in !"#s$ hich ha(e been compared to the e;ui(alent of assembly
languages$ there are mo(es to raise the abstraction le(el through the introduction of alternati(e
languages.
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Chapter 1 - Introduction
.ational &nstrument3s #ab :&8< graphical programming language (sometimes referred
to as "G" ) has an FPGA add-in module a(ailable to target and program FPGA hardare. To
simplify the design of comple- systems in FPGAs$ there e-ist libraries of predefined comple-
functions and circuits that ha(e been tested and optimi2ed to speed up the design process.
These predefined circuits are commonly called &P cores$ and are a(ailable from FPGA
(endors and third-party &P suppliers (rarely free$ and typically released under proprietary
licenses). 0ther predefined circuits are a(ailable from de(eloper communities such as 0pen
'ores (typically released under free and open source licenses such as the GP#$ =%" or similar
license)$ and other sources.
&n a typical design flo$ an FPGA application de(eloper ill simulate the design at
multiple stages throughout the design process. &nitially the 1T# description in :!"# or :erilog
is simulated by creating test benches to simulate the system and obser(e results.
Then$ after the synthesis engine has mapped the design to a net list$ the net list is
translated to a gate le(el description here simulation is repeated to confirm the synthesis
proceeded ithout errors. Finally the design is laid out in the FPGA at hich point propagation
delays can be added and the simulation run again ith these (alues bac,-annotated onto the net
list.
1.1% #RAM
%ynchronous dynamic random access memory (%"1A9) is dynamic random access
memory that has a synchronous interface. Traditionally$ dynamic random access memory
("1A9) has an asynchronous interface$ hich means that it responds as ;uic,ly as possible to
changes in control inputs.
%"1A9 has a synchronous interface$ meaning that it aits for a cloc, signal before
responding to control inputs and is therefore synchroni2ed ith the computer3s system bus. The
cloc, is used to dri(e an internal finite state machine that pipelines incoming instructions.
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Chapter 1 - Introduction
1.&' FLA#( MEMOR
Flash memory is a non-(olatile computer storage chip that can be electrically erased and
reprogrammed. &t is primarily used in memory cards$ >%= flash dri(es$ 9P? players and solid-
state dri(es for general storage and transfer of data beteen computers and other digital
products.
&t is a specific type of 88P109 (electrically erasable programmable read-only memory)
that is erased and programmed in large bloc,s@ in early flash the entire chip had to be erased at
once.
Flash memory costs far less than byte-programmable 88P109 and therefore has
become the dominant technology here(er a significant amount of non-(olatile$ solid state
storage is needed. 8-ample applications include P"As (personal digital assistants)$ laptop
computers$ digital audio players$ digital cameras and mobile phones.
&t has also gained popularity in console (ideo game hardare$ here it is often used
instead of 88P109s or battery-poered static 1A9 (%1A9) for game sa(e data.
Flash memory is non-(olatile$ meaning no poer is needed to maintain the information
stored in the chip. &n addition$ flash memory offers fast read access times (although not as fast as
(olatile "1A9 memory used for main memory in P's) and better ,inetic shoc, resistance than
hard dis,s.
These characteristics e-plain the popularity of flash memory in portable de(ices. Another
feature of flash memory is that hen pac,aged in a "memory card$" it is e-tremely durable$
being able to ithstand intense pressure$ e-tremes of temperature$ and e(en immersion in ater.
Although technically a type of 88P109$ the term "88P109" is generally used to refer
specifically to non-flash 88P109 hich is erasable in small bloc,s$ typically bytes. =ecause
erase cycles are slo$ the large bloc, si2es used in flash memory erasing gi(e it a significant
speed ad(antage o(er old-style 88P109 hen riting large amounts of data.
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Chapter 1 - Introduction
Flash memory is a type of 88P109 chip$ hich stands for 8lectronically 8rasable
Programmable 1ead 0nly 9emory. &t has a grid of columns and ros ith a cell that has to
transistors at each intersection.
The to transistors are separated from each other by a thin o-ide layer. 0ne of the
transistors is ,non as a floating gate$ and the other one is the control gate. The floating gate3s
only lin, to the ro$ or ord line$ is through the control gate.
Fi) 1.1.% * FLA#( MEMOR
1.21 COMMERCIALLY AVAILABLE FPGAS
As one of the largest groing segments of the semiconductor industry$ the FPGA mar,et-
place is (olatile. As such$ the pool of companies in(ol(ed changes rapidly and it is somehat
difficult to say hich products ill be the most significant hen the industry reaches a stable
state.
For this reason$ and to pro(ide a more focused discussion$ e ill not mention all of the
FPGA manufacturers that currently e-ist$ but ill instead focus on those companies hose
products are in ide- spread use at this time. &n describing each de(ice e ill list its capacity$
nominally in A-input .A." gates as gi(en by the (endor.
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Chapter 1 - Introduction
Gate count is an especially contentious issue in the FPGA industry$ and so the numbers
gi(en in this paper for all manufacturers should not be ta,en too seriously. <ags ha(e ta,en to
calling them BdogC gates$ in reference to the traditional ratio beteen human and dog years.
There are to basic categories of FPGAs on the mar,et today6 *. %1A9-based FPGAs and A.
antifuse-based FPGAs.
&n the rst category$ /ilin- and Altera are the leading manufacturers in terms of number of
users$ ith the ma4or competitor being ATDT. For antifuse-based products$ Actel$ Euic, logic
and 'ypress$ and /ilin- offer competing products.
1.&& +ILI$+ #RAM-BA#ED FPGA,
The basic structure of /ilin- FPGAs is array-based$ meaning that each chip comprises a
to- dimensional array of logic bloc,s that can be interconnected (ia hori2ontal and (ertical
routing channels. /ilin- introduced the rst FPGA family$ called the /'AFFF series$ in about
*GHI and no offers three more generations6 /'?FFF$ /'JFFF$ and /'IFFF. Although the
/'?FFF de(ices are still idely used$ e ill focus on the more recent and more popular
/'JFFF family.
<e note that /'IFFF is similar to /'JFFF$ but has been engineered to offer similar
features at a more attracti(e price$ ith some penalty in speed. <e should also note that /ilin-
has recently introduced an FPGA family based on anti-fuses$ called the /'H*FF. The /'H*FF
has many interesting features$ but since it is not yet in idespread use.
For instance$ each '#= contains circuitry that allos it to efficiently perform arithmetic
(i.e.$ a circuit that can implement a fast carry operation for adder-li,e circuits) and also the #>Ts
in a '#= can be configured as read5rite 1A9 cells. A ne (ersion of this family$ the JFFF8$
has the additional feature that the 1A9 can be configured as a dual port 1A9 ith a single
rite and to read ports.
&n the JFFF8$ 1A9 bloc,s can be synchronous 1A9. Also$ each /'JFFF chip includes
(ery ide A."-planes around the periphery of the logic bloc, array to facilitate implementing
circuit bloc,s such as ide decoders. =esides logic$ the other ,ey feature that characteri2es an
FPGA is its interconnecting structure.
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Chapter 1 - Introduction
The /'JFFF interconnect is arranged in hori2ontal and (ertical channels. 8ach channel
contains some number of short ire segments that span a single '#= (the number of segments in
each channel depends on the specific part number)$ longer segments that span to '#=s$ and
(ery long segments that span the entire length or idth of the chip.
Programmable sitches are a(ailable to connect the inputs and outputs of the '#=s to the
ire segments$ or to connect one ire segment to another. A small section of a routing channel
representati(e of an /'JFFF de(ice appears. The figure shos only the ire segments in a
hori2ontal channel$ and does not sho the (ertical routing channels$ the '#= inputs and outputs$
or the routing sitches.
An important point orth noting about the /ilin- interconnect is that signals must pass
through sitches to reach one '#= from another$ and the total number of sitches tra(ersed
depends on the particular set of ire segments used. Thus$ speed-performance of an implemented
circuit depends in part on ho the ire segments are allocated to indi(idual signals by 'A"
tools.
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